SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
tb.dut.hmac_csr_assert | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
84.91 | 95.81 | 83.54 | 100.00 | 40.00 | 90.11 | 100.00 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 2 | 2 | 100.00 | 2 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 2 | 2 | 100.00 | 2 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
TlulOOBAddrErr_A | 223719206 | 1320770 | 0 | 0 |
intr_enable_rd_A | 223719206 | 2010 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 223719206 | 1320770 | 0 | 0 |
T10 | 421190 | 184557 | 0 | 0 |
T11 | 0 | 396530 | 0 | 0 |
T12 | 0 | 64847 | 0 | 0 |
T13 | 0 | 58764 | 0 | 0 |
T42 | 12570 | 0 | 0 | 0 |
T44 | 22825 | 0 | 0 | 0 |
T50 | 0 | 2 | 0 | 0 |
T51 | 0 | 4 | 0 | 0 |
T55 | 0 | 12 | 0 | 0 |
T57 | 0 | 322 | 0 | 0 |
T58 | 0 | 996 | 0 | 0 |
T59 | 0 | 13 | 0 | 0 |
T60 | 5890 | 0 | 0 | 0 |
T61 | 856 | 0 | 0 | 0 |
T62 | 783 | 0 | 0 | 0 |
T63 | 5914 | 0 | 0 | 0 |
T64 | 33754 | 0 | 0 | 0 |
T65 | 30576 | 0 | 0 | 0 |
T66 | 40807 | 0 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 223719206 | 2010 | 0 | 0 |
T13 | 246143 | 64 | 0 | 0 |
T50 | 0 | 79 | 0 | 0 |
T53 | 0 | 23 | 0 | 0 |
T55 | 0 | 26 | 0 | 0 |
T56 | 0 | 28 | 0 | 0 |
T67 | 0 | 30 | 0 | 0 |
T68 | 0 | 45 | 0 | 0 |
T69 | 0 | 11 | 0 | 0 |
T70 | 0 | 7 | 0 | 0 |
T71 | 0 | 446 | 0 | 0 |
T72 | 20765 | 0 | 0 | 0 |
T73 | 36460 | 0 | 0 | 0 |
T74 | 380013 | 0 | 0 | 0 |
T75 | 252103 | 0 | 0 | 0 |
T76 | 93302 | 0 | 0 | 0 |
T77 | 3931 | 0 | 0 | 0 |
T78 | 440595 | 0 | 0 | 0 |
T79 | 2618 | 0 | 0 | 0 |
T80 | 1101 | 0 | 0 | 0 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |