Unified Coverage Report :: Module :: hmac_csr_assert_fpv

Module : hmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_hmac_csr_assert_0/hmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.hmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.hmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
84.91	95.81	83.54	100.00	40.00	90.11	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : hmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	223719206	1320770	0	0
intr_enable_rd_A	223719206	2010	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	223719206	1320770	0	0
T10	421190	184557	0	0
T11	0	396530	0	0
T12	0	64847	0	0
T13	0	58764	0	0
T42	12570	0	0	0
T44	22825	0	0	0
T50	0	2	0	0
T51	0	4	0	0
T55	0	12	0	0
T57	0	322	0	0
T58	0	996	0	0
T59	0	13	0	0
T60	5890	0	0	0
T61	856	0	0	0
T62	783	0	0	0
T63	5914	0	0	0
T64	33754	0	0	0
T65	30576	0	0	0
T66	40807	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	223719206	2010	0	0
T13	246143	64	0	0
T50	0	79	0	0
T53	0	23	0	0
T55	0	26	0	0
T56	0	28	0	0
T67	0	30	0	0
T68	0	45	0	0
T69	0	11	0	0
T70	0	7	0	0
T71	0	446	0	0
T72	20765	0	0	0
T73	36460	0	0	0
T74	380013	0	0	0
T75	252103	0	0	0
T76	93302	0	0	0
T77	3931	0	0	0
T78	440595	0	0	0
T79	2618	0	0	0
T80	1101	0	0	0