Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	18113931	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

19580484

1

T1

153

T2

1

T3

73808

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	14750385	1			T1	133		T2	1		T3	65836
values[0x0]	10683410	1			T1	76		T3	43110		T4	22115
values[0x1]	12260620	1			T1	98		T3	53885		T4	27622

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	13397477	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

24296938

1

T1

185

T2

1

T3

97823

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	133784	1			T1	5		T3	695		T4	320
valid_sources[0x01]	130030	1			T1	6		T3	475		T4	310
valid_sources[0x02]	146420	1			T3	700		T4	323		T5	4
valid_sources[0x03]	139394	1			T3	717		T4	342		T5	9
valid_sources[0x04]	185548	1			T3	711		T4	338		T5	7
valid_sources[0x05]	152086	1			T3	639		T4	324		T5	4
valid_sources[0x06]	126327	1			T1	3		T3	512		T4	291
valid_sources[0x07]	159264	1			T3	649		T4	327		T5	8
valid_sources[0x08]	154180	1			T1	1		T3	801		T4	357
valid_sources[0x09]	124291	1			T1	2		T3	693		T4	312
valid_sources[0x0a]	134298	1			T1	10		T3	602		T4	351
valid_sources[0x0b]	148519	1			T1	3		T3	902		T4	308
valid_sources[0x0c]	154669	1			T3	580		T4	292		T5	4
valid_sources[0x0d]	130423	1			T1	2		T3	707		T4	295
valid_sources[0x0e]	158427	1			T1	2		T3	613		T4	296
valid_sources[0x0f]	150576	1			T3	776		T4	341		T5	5
valid_sources[0x10]	129090	1			T1	5		T3	831		T4	369
valid_sources[0x11]	125947	1			T1	1		T3	911		T4	300
valid_sources[0x12]	140708	1			T3	699		T4	323		T5	4
valid_sources[0x13]	167111	1			T3	827		T4	306		T5	7
valid_sources[0x14]	145354	1			T1	1		T3	670		T4	346
valid_sources[0x15]	138852	1			T3	546		T4	345		T5	9
valid_sources[0x16]	151634	1			T1	5		T3	918		T4	312
valid_sources[0x17]	129683	1			T1	1		T3	675		T4	332
valid_sources[0x18]	219328	1			T1	1		T3	629		T4	296
valid_sources[0x19]	149625	1			T1	2		T3	408		T4	347
valid_sources[0x1a]	158829	1			T3	525		T4	321		T5	8
valid_sources[0x1b]	167022	1			T3	672		T4	306		T5	4
valid_sources[0x1c]	122765	1			T1	1		T3	827		T4	319
valid_sources[0x1d]	156673	1			T1	2		T3	418		T4	322
valid_sources[0x1e]	125627	1			T3	627		T4	360		T5	3
valid_sources[0x1f]	139827	1			T3	574		T4	338		T5	7
valid_sources[0x20]	149501	1			T1	2		T3	655		T4	328
valid_sources[0x21]	144721	1			T1	4		T3	633		T4	317
valid_sources[0x22]	142123	1			T1	1		T3	622		T4	351
valid_sources[0x23]	150943	1			T3	661		T4	331		T5	6
valid_sources[0x24]	136527	1			T3	572		T4	305		T5	6
valid_sources[0x25]	174990	1			T3	668		T4	328		T5	5
valid_sources[0x26]	138577	1			T1	2		T3	636		T4	332
valid_sources[0x27]	127375	1			T1	2		T3	664		T4	291
valid_sources[0x28]	131762	1			T1	1		T3	575		T4	322
valid_sources[0x29]	141836	1			T1	1		T3	732		T4	310
valid_sources[0x2a]	137613	1			T1	2		T3	723		T4	343
valid_sources[0x2b]	138453	1			T3	831		T4	308		T5	7
valid_sources[0x2c]	176188	1			T3	504		T4	333		T5	2
valid_sources[0x2d]	130903	1			T3	677		T4	351		T5	8
valid_sources[0x2e]	126477	1			T1	3		T3	697		T4	319
valid_sources[0x2f]	127683	1			T1	1		T3	589		T4	304
valid_sources[0x30]	151171	1			T3	681		T4	351		T5	7
valid_sources[0x31]	136076	1			T1	1		T3	510		T4	330
valid_sources[0x32]	125182	1			T1	1		T3	768		T4	332
valid_sources[0x33]	124427	1			T1	1		T3	740		T4	337
valid_sources[0x34]	156687	1			T1	1		T3	711		T4	337
valid_sources[0x35]	191805	1			T3	559		T4	299		T5	2
valid_sources[0x36]	183352	1			T3	689		T4	314		T5	6
valid_sources[0x37]	182024	1			T1	1		T3	755		T4	323
valid_sources[0x38]	144074	1			T3	621		T4	340		T5	12
valid_sources[0x39]	123830	1			T3	672		T4	347		T5	5
valid_sources[0x3a]	175252	1			T1	1		T3	563		T4	339
valid_sources[0x3b]	178796	1			T3	624		T4	315		T5	5
valid_sources[0x3c]	172603	1			T1	3		T3	693		T4	324
valid_sources[0x3d]	125582	1			T3	530		T4	299		T5	9
valid_sources[0x3e]	135096	1			T1	1		T3	501		T4	317
valid_sources[0x3f]	144852	1			T1	1		T3	610		T4	354
valid_sources[0x40]	165163	1			T3	561		T4	348		T5	9
valid_sources[0x41]	146798	1			T1	2		T3	555		T4	322
valid_sources[0x42]	127119	1			T3	676		T4	319		T5	9
valid_sources[0x43]	161321	1			T3	742		T4	317		T5	8
valid_sources[0x44]	159881	1			T3	615		T4	295		T5	6
valid_sources[0x45]	269732	1			T1	4		T3	603		T4	358
valid_sources[0x46]	160879	1			T1	1		T3	628		T4	364
valid_sources[0x47]	155050	1			T3	519		T4	310		T5	8
valid_sources[0x48]	156133	1			T1	1		T3	781		T4	322
valid_sources[0x49]	147329	1			T1	1		T3	812		T4	326
valid_sources[0x4a]	126650	1			T1	2		T3	442		T4	332
valid_sources[0x4b]	132213	1			T1	1		T3	676		T4	312
valid_sources[0x4c]	143963	1			T1	1		T3	489		T4	294
valid_sources[0x4d]	141732	1			T1	1		T3	544		T4	309
valid_sources[0x4e]	137924	1			T1	7		T3	614		T4	340
valid_sources[0x4f]	145901	1			T1	2		T3	730		T4	313
valid_sources[0x50]	174223	1			T1	2		T3	752		T4	338
valid_sources[0x51]	152396	1			T3	565		T4	360		T5	9
valid_sources[0x52]	123974	1			T1	1		T3	592		T4	346
valid_sources[0x53]	133772	1			T3	493		T4	338		T5	10
valid_sources[0x54]	123572	1			T3	678		T4	316		T5	4
valid_sources[0x55]	141692	1			T1	2		T3	509		T4	316
valid_sources[0x56]	125007	1			T1	2		T3	712		T4	303
valid_sources[0x57]	124972	1			T3	787		T4	321		T5	6
valid_sources[0x58]	153093	1			T1	3		T3	555		T4	314
valid_sources[0x59]	125171	1			T3	813		T4	336		T5	11
valid_sources[0x5a]	129674	1			T1	2		T3	557		T4	323
valid_sources[0x5b]	162379	1			T1	1		T3	652		T4	313
valid_sources[0x5c]	131398	1			T3	576		T4	300		T5	5
valid_sources[0x5d]	165399	1			T1	1		T3	454		T4	289
valid_sources[0x5e]	175963	1			T1	1		T3	703		T4	314
valid_sources[0x5f]	158895	1			T3	429		T4	369		T5	8
valid_sources[0x60]	122427	1			T3	580		T4	317		T5	3
valid_sources[0x61]	142538	1			T3	655		T4	306		T5	6
valid_sources[0x62]	160527	1			T1	1		T3	678		T4	322
valid_sources[0x63]	126434	1			T3	703		T4	327		T5	7
valid_sources[0x64]	124534	1			T1	2		T3	506		T4	324
valid_sources[0x65]	173307	1			T1	1		T3	539		T4	340
valid_sources[0x66]	130997	1			T1	2		T3	702		T4	356
valid_sources[0x67]	154312	1			T1	1		T3	586		T4	348
valid_sources[0x68]	172248	1			T1	1		T3	502		T4	346
valid_sources[0x69]	155507	1			T3	624		T4	293		T5	16
valid_sources[0x6a]	189620	1			T3	629		T4	328		T5	7
valid_sources[0x6b]	169741	1			T1	4		T3	827		T4	336
valid_sources[0x6c]	129219	1			T3	669		T4	333		T5	4
valid_sources[0x6d]	124634	1			T3	586		T4	306		T5	5
valid_sources[0x6e]	132486	1			T1	2		T3	684		T4	334
valid_sources[0x6f]	124174	1			T3	431		T4	297		T5	9
valid_sources[0x70]	153921	1			T3	562		T4	344		T5	8
valid_sources[0x71]	144324	1			T1	3		T3	624		T4	337
valid_sources[0x72]	131043	1			T1	6		T3	660		T4	329
valid_sources[0x73]	127938	1			T1	2		T3	501		T4	329
valid_sources[0x74]	226176	1			T3	713		T4	320		T5	7
valid_sources[0x75]	146566	1			T3	719		T4	316		T5	9
valid_sources[0x76]	164092	1			T3	586		T4	319		T5	11
valid_sources[0x77]	133946	1			T3	720		T4	298		T5	4
valid_sources[0x78]	131829	1			T1	2		T3	819		T4	356
valid_sources[0x79]	123011	1			T1	1		T3	578		T4	302
valid_sources[0x7a]	158122	1			T1	2		T3	637		T4	322
valid_sources[0x7b]	133475	1			T1	1		T3	563		T4	339
valid_sources[0x7c]	161379	1			T1	1		T3	509		T4	361
valid_sources[0x7d]	134632	1			T1	3		T3	611		T4	325
valid_sources[0x7e]	170619	1			T3	604		T4	354		T5	3
valid_sources[0x7f]	144287	1			T1	1		T3	538		T4	315
valid_sources[0x80]	131096	1			T3	716		T4	340		T5	5

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

7316878

1

T1

61

T2

1

T3

32614

values[0x0]

all_enables

biggest_size

6465892

1

T1

43

T3

21915

T4

11130

values[0x1]

all_enables

biggest_size

5797714

1

T1

49

T3

19279

T4

9984