SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
86.67 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
tl_errors_cgs_wrap[hmac_reg_block] | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 15 | 2 | 13 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_csr_size_err | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_instr_type_err | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_mem_byte_access_err | 2 | 1 | 1 | 50.00 | 100 | 0 | 0 | 2 | |
cp_mem_ro_err | 2 | 1 | 1 | 50.00 | 100 | 0 | 0 | 2 | |
cp_mem_wo_err | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_tl_protocol_err | 1 | 0 | 1 | 100.00 | 100 | 1 | 1 | 0 | |
cp_unmapped_err | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_write_w_instr_type_err | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 658559 | 1 | T10 | 92872 | T13 | 29406 | T11 | 200735 | ||||
auto[1] | 136232 | 1 | T10 | 18024 | T13 | 6383 | T11 | 40990 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 695599 | 1 | T10 | 97129 | T13 | 31295 | T11 | 211447 | ||||
auto[1] | 99192 | 1 | T10 | 13767 | T13 | 4494 | T11 | 30278 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 1 | 1 | 50.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
[auto[1]] | 0 | 0 | - | - | - | - | - | - | ||||
auto[0] | 794791 | 0 | T10 | 110896 | T13 | 35789 | T11 | 241725 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 1 | 1 | 50.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
[auto[1]] | 0 | 0 | - | - | - | - | - | - | ||||
auto[0] | 794791 | 0 | T10 | 110896 | T13 | 35789 | T11 | 241725 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 713124 | 1 | T10 | 99415 | T13 | 32015 | T11 | 217088 | ||||
auto[1] | 81667 | 1 | T10 | 11481 | T13 | 3774 | T11 | 24637 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 1 | 0 | 1 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
covered | 266620 | 1 | T10 | 38247 | T13 | 11618 | T11 | 81123 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 771541 | 1 | T10 | 107679 | T13 | 34746 | T11 | 234859 | ||||
auto[1] | 23250 | 1 | T10 | 3217 | T13 | 1043 | T11 | 6866 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 607042 | 1 | T10 | 84736 | T13 | 27312 | T11 | 183894 | ||||
auto[1] | 187749 | 1 | T10 | 26160 | T13 | 8477 | T11 | 57831 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |