SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
100.00 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
tl_intg_err_cgs_wrap[hmac_reg_block] | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 14 | 0 | 14 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_is_mem | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_num_cmd_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_num_data_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_tl_intg_err_type | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 28607931 | 1 | T1 | 260 | T2 | 1 | T3 | 99407 | ||||
auto[1] | 11537492 | 1 | T1 | 47 | T3 | 63424 | T4 | 32629 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 40145182 | 1 | T1 | 307 | T2 | 1 | T3 | 162831 | ||||
values[1] | 29 | 1 | T50 | 1 | T51 | 2 | T52 | 3 | ||||
values[2] | 2 | 1 | T127 | 1 | T128 | 1 | - | - | ||||
values[3] | 126 | 1 | T50 | 3 | T51 | 3 | T52 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 40145196 | 1 | T1 | 307 | T2 | 1 | T3 | 162831 | ||||
values[1] | 20 | 1 | T51 | 1 | T127 | 2 | T129 | 1 | ||||
values[2] | 3 | 1 | T130 | 1 | T131 | 1 | T132 | 1 | ||||
values[3] | 113 | 1 | T50 | 4 | T51 | 3 | T52 | 4 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[TlIntgErrNone] | 40145073 | 1 | T1 | 307 | T2 | 1 | T3 | 162831 | ||||
auto[TlIntgErrCmd] | 123 | 1 | T50 | 2 | T51 | 3 | T52 | 4 | ||||
auto[TlIntgErrData] | 109 | 1 | T50 | 6 | T51 | 4 | T52 | 2 | ||||
auto[TlIntgErrBoth] | 118 | 1 | T50 | 2 | T51 | 3 | T52 | 4 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |