Unified Coverage Report :: Module :: hmac

Module : hmac

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
84.68	95.81	82.14	100.00	40.00	90.11	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_hmac_0.1/rtl/hmac.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut	85.18	95.81	85.19	100.00	40.00	90.11	100.00

---

Module Instance : tb.dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.18	95.81	85.19	100.00	40.00	90.11	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.71	95.58	93.55	100.00	76.32	91.33	99.49

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_alert_tx[0].u_prim_alert_sender	100.00			100.00
hmac_csr_assert	100.00						100.00
intr_hw_fifo_empty	100.00	100.00	100.00			100.00	100.00
intr_hw_hmac_done	100.00	100.00	100.00			100.00	100.00
intr_hw_hmac_err	100.00	100.00	100.00			100.00	100.00
tlul_assert_device	100.00	100.00				100.00	100.00
u_hmac	93.46	95.45	90.16		100.00	88.24
u_msg_fifo	100.00	100.00	100.00			100.00	100.00
u_packer	100.00	100.00	100.00			100.00	100.00
u_prim_sha2_512	88.39	96.75	91.64		76.00	89.18
u_reg	98.20	94.80	97.48	100.00		98.72	100.00
u_tlul_adapter	88.53	94.06	87.20			80.25	92.59

Line Coverage for Module : hmac

	Line No.	Total	Covered	Percent
TOTAL		191	183	95.81
CONT_ASSIGN	135	1	1	100.00
CONT_ASSIGN	136	1	1	100.00
CONT_ASSIGN	137	1	1	100.00
ALWAYS	149	15	9	60.00
ALWAYS	191	3	3	100.00
CONT_ASSIGN	198	1	1	100.00
CONT_ASSIGN	199	1	1	100.00
ALWAYS	203	7	7	100.00
ALWAYS	217	3	3	100.00
ALWAYS	227	0	0
ALWAYS	227	21	21	100.00
CONT_ASSIGN	270	1	1	100.00
CONT_ASSIGN	274	1	1	100.00
CONT_ASSIGN	275	1	1	100.00
CONT_ASSIGN	277	1	1	100.00
ALWAYS	279	4	4	100.00
CONT_ASSIGN	291	1	1	100.00
ALWAYS	294	3	3	100.00
CONT_ASSIGN	298	1	1	100.00
ALWAYS	300	6	6	100.00
CONT_ASSIGN	313	1	1	100.00
CONT_ASSIGN	314	1	1	100.00
CONT_ASSIGN	316	1	1	100.00
CONT_ASSIGN	317	1	1	100.00
CONT_ASSIGN	318	1	1	100.00
CONT_ASSIGN	319	1	1	100.00
CONT_ASSIGN	320	1	1	100.00
CONT_ASSIGN	321	1	1	100.00
CONT_ASSIGN	323	1	1	100.00
CONT_ASSIGN	324	1	1	100.00
CONT_ASSIGN	325	1	1	100.00
CONT_ASSIGN	326	1	1	100.00
CONT_ASSIGN	329	1	1	100.00
CONT_ASSIGN	330	1	1	100.00
CONT_ASSIGN	335	1	1	100.00
CONT_ASSIGN	336	1	1	100.00
CONT_ASSIGN	337	1	1	100.00
CONT_ASSIGN	338	1	1	100.00
ALWAYS	341	6	6	100.00
ALWAYS	351	4	4	100.00
ALWAYS	386	6	6	100.00
CONT_ASSIGN	435	1	1	100.00
CONT_ASSIGN	442	1	1	100.00
CONT_ASSIGN	450	1	1	100.00
CONT_ASSIGN	452	1	1	100.00
ALWAYS	455	5	5	100.00
CONT_ASSIGN	496	1	1	100.00
CONT_ASSIGN	499	1	1	100.00
CONT_ASSIGN	505	1	1	100.00
CONT_ASSIGN	510	1	1	100.00
CONT_ASSIGN	511	1	1	100.00
CONT_ASSIGN	513	1	1	100.00
CONT_ASSIGN	514	1	1	100.00
CONT_ASSIGN	515	1	1	100.00
ALWAYS	519	8	8	100.00
CONT_ASSIGN	588	1	1	100.00
ALWAYS	593	3	3	100.00
ALWAYS	601	3	3	100.00
ALWAYS	606	10	8	80.00
CONT_ASSIGN	623	1	1	100.00
CONT_ASSIGN	624	1	1	100.00
CONT_ASSIGN	631	1	1	100.00
CONT_ASSIGN	632	1	1	100.00
CONT_ASSIGN	743	1	1	100.00
CONT_ASSIGN	772	1	1	100.00
CONT_ASSIGN	773	1	1	100.00
CONT_ASSIGN	774	1	1	100.00
CONT_ASSIGN	779	1	1	100.00
CONT_ASSIGN	784	1	1	100.00
ALWAYS	787	6	6	100.00
CONT_ASSIGN	803	1	1	100.00
ALWAYS	808	7	7	100.00
CONT_ASSIGN	849	1	1	100.00
CONT_ASSIGN	853	1	1	100.00
ALWAYS	855	3	3	100.00
CONT_ASSIGN	861	1	1	100.00
ALWAYS	883	6	6	100.00
ALWAYS	890	6	6	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_hmac_0.1/rtl/hmac.sv' or '../src/lowrisc_ip_hmac_0.1/rtl/hmac.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
135	1	1
136	1	1
137	1	1
149	1	1
150	1	1
152	1	1
154	1	1
156	1	1
157	1	1
159	0	1
			MISSING_ELSE
164	1	1
165	1	1
166	1	1
			MISSING_ELSE
171	0	1
175	0	1
			==> MISSING_ELSE
180	0	1
181	0	1
182	0	1
			==> MISSING_ELSE
191	1	1
192	1	1
194	1	1
198	1	1
199	1	1
203	1	1
204	1	1
205	1	1
206	1	1
208	1	1
209	1	1
210	1	1
			MISSING_ELSE
			MISSING_ELSE
217	2	2
218	1	1
227	1	1
229	1	1
231	1	1
232	1	1
			MISSING_ELSE
235	1	1
237	1	1
238	1	1
240	1	1
242	1	1
243	1	1
248	1	1
250	1	1
251	1	1
253	1	1
254	1	1
256	1	1
257	1	1
259	1	1
260	1	1
262	1	1
263	1	1
			MISSING_ELSE
270	1	1
274	1	1
275	1	1
277	1	1
279	1	1
280	1	1
281	1	1
282	1	1
291	1	1
294	2	2
295	1	1
298	1	1
300	1	1
301	1	1
302	1	1
303	1	1
304	1	1
305	1	1
313	1	1
314	1	1
316	1	1
317	1	1
318	1	1
319	1	1
320	1	1
321	1	1
323	1	1
324	1	1
325	1	1
326	1	1
329	1	1
330	1	1
335	1	1
336	1	1
337	1	1
338	1	1
341	1	1
342	1	1
343	1	1
344	1	1
345	1	1
346	1	1
			MISSING_ELSE
351	1	1
352	1	1
379	1	1
380	1	1
			MISSING_ELSE
386	1	1
387	1	1
388	1	1
389	1	1
390	1	1
391	1	1
			MISSING_ELSE
435	1	1
442	1	1
450	1	1
452	1	1
455	1	1
456	1	1
457	1	1
459	1	1
460	1	1
496	1	1
499	1	1
505	1	1
510	1	1
511	1	1
513	1	1
514	1	1
515	1	1
519	1	1
520	1	1
521	1	1
523	1	1
524	1	1
526	1	1
527	1	1
			==> MISSING_ELSE
530	1	1
588	1	1
593	1	1
594	1	1
595	1	1
601	2	2
602	1	1
606	1	1
607	1	1
608	1	1
609	0	1
			MISSING_ELSE
611	1	1
612	0	1
			MISSING_ELSE
			MISSING_ELSE
616	1	1
617	1	1
618	1	1
619	1	1
			MISSING_ELSE
623	1	1
624	1	1
631	1	1
632	1	1
743	1	1
772	1	1
773	1	1
774	1	1
779	1	1
784	1	1
787	1	1
788	1	1
789	1	1
790	1	1
791	1	1
			MISSING_ELSE
795	1	1
803	1	1
808	1	1
809	1	1
811	1	1
815	1	1
819	1	1
823	1	1
827	1	1
849	1	1
853	1	1
855	1	1
856	1	1
858	1	1
861	1	1
883	2	2
884	2	2
885	2	2
			MISSING_ELSE
890	2	2
891	2	2
892	2	2
			MISSING_ELSE

---

Cond Coverage for Module : hmac

	Total	Covered	Percent
Conditions	168	138	82.14
Logical	168	138	82.14
Non-Logical	0	0
Event	0	0

 LINE       237
 EXPRESSION (digest_size_started_q == SHA2_256)
            -----------------1-----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       250
 EXPRESSION ((digest_size_started_q == SHA2_384) || (digest_size_started_q == SHA2_512))
             -----------------1-----------------    -----------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T4,T5
1	0	Covered	T1,T3,T4

 LINE       250
 SUB-EXPRESSION (digest_size_started_q == SHA2_384)
                -----------------1-----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       250
 SUB-EXPRESSION (digest_size_started_q == SHA2_512)
                -----------------1-----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T5

 LINE       251
 EXPRESSION (((i % 2) == 0) && (i < 15))
             -------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Not Covered
1	1	Covered	T1,T3,T4

 LINE       251
 SUB-EXPRESSION ((i % 2) == 0)
                -------1------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T3,T4

 LINE       257
 EXPRESSION (reg2hw.digest[i].qe | reg2hw.digest[(i + 1)].qe)
             ---------1---------   ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T4
0	1	Not Covered
1	0	Not Covered

 LINE       263
 EXPRESSION (reg2hw.digest[i].qe | reg2hw.digest[(i - 1)].qe)
             ---------1---------   ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T4
0	1	Not Covered
1	0	Not Covered

 LINE       291
 EXPRESSION (hash_start_or_continue ? digest_size : digest_size_started_q)
             -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       323
 EXPRESSION (reg2hw.cmd.hash_start.qe & reg2hw.cmd.hash_start.q)
             ------------1-----------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       324
 EXPRESSION (reg2hw.cmd.hash_stop.qe & reg2hw.cmd.hash_stop.q)
             -----------1-----------   -----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       325
 EXPRESSION (reg2hw.cmd.hash_continue.qe & reg2hw.cmd.hash_continue.q)
             -------------1-------------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       326
 EXPRESSION (reg2hw.cmd.hash_process.qe & reg2hw.cmd.hash_process.q)
             -------------1------------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       335
 EXPRESSION (reg_hash_start & sha_en & ((~cfg_block)) & ((~invalid_config)))
             -------1------   ---2--   -------3------   ---------4---------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Covered	T1,T2,T3
1	0	1	1	Covered	T23,T24,T25
1	1	0	1	Covered	T23,T26,T11
1	1	1	0	Covered	T1,T3,T4
1	1	1	1	Covered	T1,T2,T3

 LINE       336
 EXPRESSION (reg_hash_continue & sha_en & ((~cfg_block)) & ((~invalid_config)))
             --------1--------   ---2--   -------3------   ---------4---------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Covered	T1,T2,T3
1	0	1	1	Not Covered
1	1	0	1	Not Covered
1	1	1	0	Not Covered
1	1	1	1	Not Covered

 LINE       337
 EXPRESSION (reg_hash_process & sha_en & cfg_block & ((~invalid_config)))
             --------1-------   ---2--   ----3----   ---------4---------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Covered	T1,T2,T3
1	0	1	1	Not Covered
1	1	0	1	Covered	T27
1	1	1	0	Not Covered
1	1	1	1	Covered	T1,T2,T3

 LINE       338
 EXPRESSION (hash_start | hash_continue)
             -----1----   ------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T2,T3

 LINE       345
 EXPRESSION (reg_hash_done || reg_hash_stop)
             ------1------    ------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T2,T3

 LINE       379
 EXPRESSION (((!cfg_block)) && reg2hw.cfg.hmac_en.qe)
             -------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T7,T28
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       435
 EXPRESSION (fifo_empty_q & ((~fifo_empty)))
             ------1-----   -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       442
 EXPRESSION 
 Number  Term
      1  fifo_full ? 1'b1 : (fifo_empty_negedge ? 1'b0 : ((reg_hash_start || reg_hash_continue || reg_hash_process || reg_hash_stop) ? 1'b0 : fifo_full_seen_q)))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       442
 SUB-EXPRESSION (fifo_empty_negedge ? 1'b0 : ((reg_hash_start || reg_hash_continue || reg_hash_process || reg_hash_stop) ? 1'b0 : fifo_full_seen_q))
                 ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       442
 SUB-EXPRESSION ((reg_hash_start || reg_hash_continue || reg_hash_process || reg_hash_stop) ? 1'b0 : fifo_full_seen_q)
                 -------------------------------------1------------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       442
 SUB-EXPRESSION (reg_hash_start || reg_hash_continue || reg_hash_process || reg_hash_stop)
                 -------1------    --------2--------    --------3-------    ------4------

-1-	-2-	-3-	-4-	Status	Tests
0	0	0	0	Covered	T1,T2,T3
0	0	0	1	Not Covered
0	0	1	0	Covered	T1,T2,T3
0	1	0	0	Not Covered
1	0	0	0	Covered	T1,T2,T3

 LINE       450
 EXPRESSION (((~msg_allowed)) || ((~fifo_full_seen_q)))
             --------1-------    ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T16,T29,T30
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       452
 EXPRESSION (fifo_empty_gate ? 1'b0 : fifo_empty)
             -------1-------

-1-	Status	Tests
0	Covered	T16,T29,T30
1	Covered	T1,T2,T3

 LINE       496
 EXPRESSION (msg_fifo_req & ((~msg_fifo_we)))
             ------1-----   --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       499
 EXPRESSION (msg_fifo_req & ((~hmac_fifo_wsel)) & packer_ready)
             ------1-----   ---------2---------   ------3-----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Unreachable	T17,T18,T19
1	1	1	Covered	T1,T2,T3

 LINE       515
 EXPRESSION ((hmac_fifo_wsel && fifo_wready) ? hmac_fifo_wvalid : reg_fifo_wvalid)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       515
 SUB-EXPRESSION (hmac_fifo_wsel && fifo_wready)
                 -------1------    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       521
 EXPRESSION (digest_size == SHA2_256)
            ------------1------------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T2,T4

 LINE       524
 EXPRESSION ((digest_size == SHA2_384) || (digest_size == SHA2_512))
             ------------1------------    ------------2------------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Covered	T3,T4,T9
1	0	Covered	T1,T3,T4

 LINE       524
 SUB-EXPRESSION (digest_size == SHA2_384)
                ------------1------------

-1-	Status	Tests
0	Covered	T3,T4,T9
1	Covered	T1,T3,T4

 LINE       524
 SUB-EXPRESSION (digest_size == SHA2_512)
                ------------1------------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T3,T4,T9

 LINE       540
 EXPRESSION (fifo_wvalid & sha_en)
             -----1-----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       588
 EXPRESSION (msg_fifo_req & msg_fifo_we & ((~hmac_fifo_wsel)) & msg_allowed)
             ------1-----   -----2-----   ---------3---------   -----4-----

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Covered	T1,T2,T3
1	0	1	1	Not Covered
1	1	0	1	Not Covered
1	1	1	0	Covered	T1,T3,T4
1	1	1	1	Covered	T1,T2,T3

 LINE       618
 EXPRESSION (msg_write && sha_en && packer_ready)
             ----1----    ---2--    ------3-----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Unreachable	T17,T18,T19
1	1	1	Covered	T1,T2,T3

 LINE       638
 EXPRESSION (msg_write & sha_en)
             ----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       638
 EXPRESSION (fifo_wready & ((~hmac_fifo_wsel)))
             -----1-----   ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       743
 SUB-EXPRESSION (reg2hw.alert_test.q & reg2hw.alert_test.qe)
                 ---------1---------   ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T20,T21,T22
1	0	Covered	T1,T2,T3
1	1	Covered	T20,T22,T31

 LINE       772
 EXPRESSION ((reg_hash_start | reg_hash_continue) & ((~sha_en)))
             ------------------1-----------------   -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T23,T24,T11

 LINE       772
 SUB-EXPRESSION (reg_hash_start | reg_hash_continue)
                 -------1------   --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T2,T3

 LINE       773
 EXPRESSION ((reg_hash_start | reg_hash_continue) & cfg_block)
             ------------------1-----------------   ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T23,T26,T11

 LINE       773
 SUB-EXPRESSION (reg_hash_start | reg_hash_continue)
                 -------1------   --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T2,T3

 LINE       774
 EXPRESSION (msg_fifo_req & ((~msg_allowed)))
             ------1-----   --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T4

 LINE       779
 EXPRESSION ((digest_size == SHA2_None) | ((key_length == Key_None) && hmac_en) | ((key_length == Key_1024) && (digest_size == SHA2_256) && hmac_en))
             -------------1------------   ------------------2------------------   ---------------------------------3--------------------------------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T4,T5,T6
0	1	0	Covered	T1,T3,T4
1	0	0	Covered	T1,T2,T3

 LINE       779
 SUB-EXPRESSION (digest_size == SHA2_None)
                -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       779
 SUB-EXPRESSION ((key_length == Key_None) && hmac_en)
                 ------------1-----------    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T4

 LINE       779
 SUB-EXPRESSION (key_length == Key_None)
                ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       779
 SUB-EXPRESSION ((key_length == Key_1024) && (digest_size == SHA2_256) && hmac_en)
                 ------------1-----------    ------------2------------    ---3---

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T4
1	0	1	Covered	T4,T15,T9
1	1	0	Covered	T4,T5,T9
1	1	1	Covered	T4,T5,T6

 LINE       779
 SUB-EXPRESSION (key_length == Key_1024)
                ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T15

 LINE       779
 SUB-EXPRESSION (digest_size == SHA2_256)
                ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       784
 EXPRESSION (reg_hash_start & invalid_config)
             -------1------   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T4

 LINE       803
 EXPRESSION 
 Number  Term
      1  ((~reg2hw.intr_state.hmac_err.q)) & 
      2  (hash_start_sha_disabled | update_seckey_inprocess | hash_start_active | msg_push_not_allowed | invalid_config_atstart))

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       803
 SUB-EXPRESSION (hash_start_sha_disabled | update_seckey_inprocess | hash_start_active | msg_push_not_allowed | invalid_config_atstart)
                 -----------1-----------   -----------2-----------   --------3--------   ----------4---------   -----------5----------

-1-	-2-	-3-	-4-	-5-	Status	Tests
0	0	0	0	0	Covered	T1,T2,T3
0	0	0	0	1	Covered	T1,T3,T4
0	0	0	1	0	Covered	T1,T3,T4
0	0	1	0	0	Covered	T23,T26,T11
0	1	0	0	0	Covered	T2,T32,T7
1	0	0	0	0	Covered	T23,T24,T25

 LINE       849
 EXPRESSION (((!reg_fifo_wvalid)) && ((!fifo_rvalid)) && hmac_core_idle && sha_core_idle)
             ----------1---------    --------2-------    -------3------    ------4------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Not Covered
1	0	1	1	Not Covered
1	1	0	1	Covered	T1,T2,T3
1	1	1	0	Covered	T3,T4,T5
1	1	1	1	Covered	T1,T2,T3

---

Toggle Coverage for Module : hmac

	Total	Covered	Percent
Totals	30	30	100.00
Total Bits	346	346	100.00
Total Bits 0->1	173	173	100.00
Total Bits 1->0	173	173	100.00

Ports	30	30	100.00
Port Bits	346	346	100.00
Port Bits 0->1	173	173	100.00
Port Bits 1->0	173	173	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T33,T34,T35	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T2,T3,T15	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T3,T4,T15	Yes	T3,T4,T15	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_error	Yes	Yes	T11,T12,T13	Yes	T11,T12,T13	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T20,T22,T31	Yes	T20,T22,T31	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T20,T22,T31	Yes	T20,T22,T31	OUTPUT
intr_hmac_done_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
intr_fifo_empty_o	Yes	Yes	T16,T29,T36	Yes	T16,T29,T36	OUTPUT
intr_hmac_err_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
idle_o[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT

*Tests covering at least one bit in the range

---

FSM Coverage for Module : hmac

Summary for FSM :: done_state_q

	Total	Covered	Percent
States	4	2	50.00	(Not included in score)
Transitions	5	2	40.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: done_state_q

---

states	Line No.	Covered	Tests
DoneAwaitCmd	166	Covered	T1,T2,T3
DoneAwaitHashComplete	175	Not Covered
DoneAwaitHashDone	156	Covered	T1,T2,T3
DoneAwaitMessageComplete	159	Not Covered

transitions	Line No.	Covered	Tests
DoneAwaitCmd->DoneAwaitHashDone	156	Covered	T1,T2,T3
DoneAwaitCmd->DoneAwaitMessageComplete	159	Not Covered
DoneAwaitHashComplete->DoneAwaitCmd	182	Not Covered
DoneAwaitHashDone->DoneAwaitCmd	166	Covered	T1,T2,T3
DoneAwaitMessageComplete->DoneAwaitHashComplete	175	Not Covered

---

Branch Coverage for Module : hmac

	Line No.	Total	Covered	Percent
Branches		91	82	90.11
TERNARY	291	2	2	100.00
TERNARY	442	4	4	100.00
TERNARY	452	2	2	100.00
TERNARY	515	2	2	100.00
CASE	152	10	4	40.00
IF	191	2	2	100.00
IF	204	3	3	100.00
IF	217	2	2	100.00
IF	229	2	2	100.00
IF	237	5	5	100.00
CASE	279	4	4	100.00
IF	294	2	2	100.00
CASE	300	6	6	100.00
IF	341	4	4	100.00
IF	351	3	3	100.00
IF	386	4	4	100.00
IF	455	2	2	100.00
IF	519	4	3	75.00
IF	601	2	2	100.00
IF	607	5	3	60.00
IF	616	3	3	100.00
IF	788	2	2	100.00
CASE	809	6	6	100.00
IF	855	2	2	100.00
IF	883	4	4	100.00
IF	890	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_hmac_0.1/rtl/hmac.sv' or '../src/lowrisc_ip_hmac_0.1/rtl/hmac.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	291	(hash_start_or_continue) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	442	(fifo_full) ? 
-2-:	442	(fifo_empty_negedge) ? 
-3-:	442	((((reg_hash_start || reg_hash_continue) || reg_hash_process) || reg_hash_stop)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	452	(fifo_empty_gate) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T16,T29,T30

	LineNo.	Expression
-1-:	515	((hmac_fifo_wsel && fifo_wready)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	152	case (done_state_q)
-2-:	154	if (sha_hash_process)
-3-:	157	if (reg_hash_stop)
-4-:	164	if (reg_hash_done)
-5-:	171	if (digest_on_blk)
-6-:	180	if ((!hash_running))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	Status	Tests
DoneAwaitCmd	1	-	-	-	-	Covered	T1,T2,T3
DoneAwaitCmd	0	1	-	-	-	Not Covered
DoneAwaitCmd	0	0	-	-	-	Covered	T1,T2,T3
DoneAwaitHashDone	-	-	1	-	-	Covered	T1,T2,T3
DoneAwaitHashDone	-	-	0	-	-	Covered	T1,T2,T3
DoneAwaitMessageComplete	-	-	-	1	-	Not Covered
DoneAwaitMessageComplete	-	-	-	0	-	Not Covered
DoneAwaitHashComplete	-	-	-	-	1	Not Covered
DoneAwaitHashComplete	-	-	-	-	0	Not Covered
default	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	191	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	204	if (wipe_secret)
-2-:	206	if ((!cfg_block))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T37,T38,T39
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	217	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	229	if ((i < 8))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	237	if ((digest_size_started_q == SHA2_256))
-2-:	238	if ((i < 8))
-3-:	250	if (((digest_size_started_q == SHA2_384) || (digest_size_started_q == SHA2_512)))
-4-:	251	if ((((i % 2) == 0) && (i < 15)))

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	1	-	-	Covered	T1,T2,T4
1	0	-	-	Covered	T1,T2,T4
0	-	1	1	Covered	T1,T3,T4
0	-	1	0	Covered	T1,T3,T4
0	-	0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	279	case (digest_size_supplied)

Branches:

-1-	Status	Tests
SHA2_256	Covered	T1,T2,T4
SHA2_384	Covered	T1,T3,T4
SHA2_512	Covered	T1,T3,T4
default	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	294	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	300	case (key_length_supplied)

Branches:

-1-	Status	Tests
Key_128	Covered	T1,T4,T5
Key_256	Covered	T1,T2,T3
Key_384	Covered	T1,T3,T4
Key_512	Covered	T1,T3,T4
Key_1024	Covered	T3,T4,T15
default	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	341	if ((!rst_ni))
-2-:	343	if (hash_start_or_continue)
-3-:	345	if ((reg_hash_done || reg_hash_stop))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	351	if ((!rst_ni))
-2-:	379	if (((!cfg_block) && reg2hw.cfg.hmac_en.qe))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	386	if ((!rst_ni))
-2-:	388	if (hash_start_or_continue)
-3-:	390	if (packer_flush_done)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	455	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	519	if (hmac_fifo_wsel)
-2-:	521	if ((digest_size == SHA2_256))
-3-:	524	if (((digest_size == SHA2_384) || (digest_size == SHA2_512)))

Branches:

-1-	-2-	-3-	Status	Tests
1	1	-	Covered	T1,T2,T4
1	0	1	Covered	T1,T3,T4
1	0	0	Not Covered
0	-	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	601	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	607	if ((!cfg_block))
-2-:	608	if (reg2hw.msg_length_lower.qe)
-3-:	611	if (reg2hw.msg_length_upper.qe)

Branches:

-1-	-2-	-3-	Status	Tests
1	1	-	Not Covered
1	0	-	Covered	T1,T2,T3
1	-	1	Not Covered
1	-	0	Covered	T1,T2,T3
0	-	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	616	if (hash_start)
-2-:	618	if (((msg_write && sha_en) && packer_ready))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	788	if (cfg_block)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	809	case (1'b1)

Branches:

-1-	Status	Tests
hash_start_sha_disabled	Covered	T23,T24,T11
update_seckey_inprocess	Covered	T2,T32,T7
hash_start_active	Covered	T23,T26,T11
msg_push_not_allowed	Covered	T1,T3,T4
invalid_config_atstart	Covered	T1,T3,T4
default	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	855	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	883	if ((!rst_ni))
-2-:	884	if (hash_process)
-3-:	885	if (reg_hash_done)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	890	if ((!rst_ni))
-2-:	891	if (hash_start_or_continue)
-3-:	892	if (hash_process)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Module : hmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertKnownO_A	233497995	233450128	0	0
FpvSecCmRegWeOnehotCheck_A	233497995	100	0	0
IntrFifoEmptyOKnown	233497995	233450128	0	0
IntrHmacDoneOKnown	233497995	233450128	0	0
TlOAReadyKnown	233497995	233450128	0	0
TlODValidKnown	233497995	233450128	0	0
ValidHashProcessAssert	233497995	18424	0	0
ValidHmacEnConditionAssert	233497995	9771	0	0
ValidWriteAssert	233497995	13097116	0	0
gen_assert_wmask_bytealign[0].unnamed$$_0	233497995	13097116	0	0
gen_assert_wmask_bytealign[1].unnamed$$_0	233497995	13097116	0	0
gen_assert_wmask_bytealign[2].unnamed$$_0	233497995	13097116	0	0
gen_assert_wmask_bytealign[3].unnamed$$_0	233497995	13097116	0	0

AlertKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	233497995	233450128	0	0
T1	78654	78562	0	0
T2	6197	6118	0	0
T3	94746	94653	0	0
T4	130171	130082	0	0
T5	6197	6126	0	0
T9	653915	653820	0	0
T15	9925	9858	0	0
T20	1091	1034	0	0
T21	657	557	0	0
T22	1067	1000	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	233497995	100	0	0
T33	3153	10	0	0
T36	15497	0	0	0
T40	0	20	0	0
T41	0	20	0	0
T42	0	20	0	0
T43	0	30	0	0
T44	3278	0	0	0
T45	283883	0	0	0
T46	369098	0	0	0
T47	51147	0	0	0
T48	125850	0	0	0
T49	25218	0	0	0
T50	12264	0	0	0
T51	94188	0	0	0

IntrFifoEmptyOKnown

Name	Attempts	Real Successes	Failures	Incomplete
Total	233497995	233450128	0	0
T1	78654	78562	0	0
T2	6197	6118	0	0
T3	94746	94653	0	0
T4	130171	130082	0	0
T5	6197	6126	0	0
T9	653915	653820	0	0
T15	9925	9858	0	0
T20	1091	1034	0	0
T21	657	557	0	0
T22	1067	1000	0	0

IntrHmacDoneOKnown

Name	Attempts	Real Successes	Failures	Incomplete
Total	233497995	233450128	0	0
T1	78654	78562	0	0
T2	6197	6118	0	0
T3	94746	94653	0	0
T4	130171	130082	0	0
T5	6197	6126	0	0
T9	653915	653820	0	0
T15	9925	9858	0	0
T20	1091	1034	0	0
T21	657	557	0	0
T22	1067	1000	0	0

TlOAReadyKnown

Name	Attempts	Real Successes	Failures	Incomplete
Total	233497995	233450128	0	0
T1	78654	78562	0	0
T2	6197	6118	0	0
T3	94746	94653	0	0
T4	130171	130082	0	0
T5	6197	6126	0	0
T9	653915	653820	0	0
T15	9925	9858	0	0
T20	1091	1034	0	0
T21	657	557	0	0
T22	1067	1000	0	0

TlODValidKnown

Name	Attempts	Real Successes	Failures	Incomplete
Total	233497995	233450128	0	0
T1	78654	78562	0	0
T2	6197	6118	0	0
T3	94746	94653	0	0
T4	130171	130082	0	0
T5	6197	6126	0	0
T9	653915	653820	0	0
T15	9925	9858	0	0
T20	1091	1034	0	0
T21	657	557	0	0
T22	1067	1000	0	0

ValidHashProcessAssert

Name	Attempts	Real Successes	Failures	Incomplete
Total	233497995	18424	0	0
T1	78654	7	0	0
T2	6197	4	0	0
T3	94746	4	0	0
T4	130171	10	0	0
T5	6197	8	0	0
T6	0	13	0	0
T9	653915	18	0	0
T10	0	22	0	0
T15	9925	1	0	0
T20	1091	0	0	0
T21	657	0	0	0
T22	1067	0	0	0
T52	0	8	0	0

ValidHmacEnConditionAssert

Name	Attempts	Real Successes	Failures	Incomplete
Total	233497995	9771	0	0
T1	78654	1	0	0
T2	6197	1	0	0
T3	94746	4	0	0
T4	130171	17	0	0
T5	6197	3	0	0
T6	0	16	0	0
T9	653915	25	0	0
T10	0	29	0	0
T15	9925	1	0	0
T20	1091	0	0	0
T21	657	0	0	0
T22	1067	0	0	0
T52	0	7	0	0

ValidWriteAssert

Name	Attempts	Real Successes	Failures	Incomplete
Total	233497995	13097116	0	0
T1	78654	14506	0	0
T2	6197	57	0	0
T3	94746	5688	0	0
T4	130171	23749	0	0
T5	6197	143	0	0
T6	0	25018	0	0
T9	653915	23961	0	0
T10	0	29499	0	0
T15	9925	388	0	0
T20	1091	0	0	0
T21	657	0	0	0
T22	1067	0	0	0
T52	0	179	0	0

gen_assert_wmask_bytealign[0].unnamed$$_0

Name	Attempts	Real Successes	Failures	Incomplete
Total	233497995	13097116	0	0
T1	78654	14506	0	0
T2	6197	57	0	0
T3	94746	5688	0	0
T4	130171	23749	0	0
T5	6197	143	0	0
T6	0	25018	0	0
T9	653915	23961	0	0
T10	0	29499	0	0
T15	9925	388	0	0
T20	1091	0	0	0
T21	657	0	0	0
T22	1067	0	0	0
T52	0	179	0	0

gen_assert_wmask_bytealign[1].unnamed$$_0

Name	Attempts	Real Successes	Failures	Incomplete
Total	233497995	13097116	0	0
T1	78654	14506	0	0
T2	6197	57	0	0
T3	94746	5688	0	0
T4	130171	23749	0	0
T5	6197	143	0	0
T6	0	25018	0	0
T9	653915	23961	0	0
T10	0	29499	0	0
T15	9925	388	0	0
T20	1091	0	0	0
T21	657	0	0	0
T22	1067	0	0	0
T52	0	179	0	0

gen_assert_wmask_bytealign[2].unnamed$$_0

Name	Attempts	Real Successes	Failures	Incomplete
Total	233497995	13097116	0	0
T1	78654	14506	0	0
T2	6197	57	0	0
T3	94746	5688	0	0
T4	130171	23749	0	0
T5	6197	143	0	0
T6	0	25018	0	0
T9	653915	23961	0	0
T10	0	29499	0	0
T15	9925	388	0	0
T20	1091	0	0	0
T21	657	0	0	0
T22	1067	0	0	0
T52	0	179	0	0

gen_assert_wmask_bytealign[3].unnamed$$_0

Name	Attempts	Real Successes	Failures	Incomplete
Total	233497995	13097116	0	0
T1	78654	14506	0	0
T2	6197	57	0	0
T3	94746	5688	0	0
T4	130171	23749	0	0
T5	6197	143	0	0
T6	0	25018	0	0
T9	653915	23961	0	0
T10	0	29499	0	0
T15	9925	388	0	0
T20	1091	0	0	0
T21	657	0	0	0
T22	1067	0	0	0
T52	0	179	0	0

Line Coverage for Instance : tb.dut

	Line No.	Total	Covered	Percent
TOTAL		191	183	95.81
CONT_ASSIGN	135	1	1	100.00
CONT_ASSIGN	136	1	1	100.00
CONT_ASSIGN	137	1	1	100.00
ALWAYS	149	15	9	60.00
ALWAYS	191	3	3	100.00
CONT_ASSIGN	198	1	1	100.00
CONT_ASSIGN	199	1	1	100.00
ALWAYS	203	7	7	100.00
ALWAYS	217	3	3	100.00
ALWAYS	227	0	0
ALWAYS	227	21	21	100.00
CONT_ASSIGN	270	1	1	100.00
CONT_ASSIGN	274	1	1	100.00
CONT_ASSIGN	275	1	1	100.00
CONT_ASSIGN	277	1	1	100.00
ALWAYS	279	4	4	100.00
CONT_ASSIGN	291	1	1	100.00
ALWAYS	294	3	3	100.00
CONT_ASSIGN	298	1	1	100.00
ALWAYS	300	6	6	100.00
CONT_ASSIGN	313	1	1	100.00
CONT_ASSIGN	314	1	1	100.00
CONT_ASSIGN	316	1	1	100.00
CONT_ASSIGN	317	1	1	100.00
CONT_ASSIGN	318	1	1	100.00
CONT_ASSIGN	319	1	1	100.00
CONT_ASSIGN	320	1	1	100.00
CONT_ASSIGN	321	1	1	100.00
CONT_ASSIGN	323	1	1	100.00
CONT_ASSIGN	324	1	1	100.00
CONT_ASSIGN	325	1	1	100.00
CONT_ASSIGN	326	1	1	100.00
CONT_ASSIGN	329	1	1	100.00
CONT_ASSIGN	330	1	1	100.00
CONT_ASSIGN	335	1	1	100.00
CONT_ASSIGN	336	1	1	100.00
CONT_ASSIGN	337	1	1	100.00
CONT_ASSIGN	338	1	1	100.00
ALWAYS	341	6	6	100.00
ALWAYS	351	4	4	100.00
ALWAYS	386	6	6	100.00
CONT_ASSIGN	435	1	1	100.00
CONT_ASSIGN	442	1	1	100.00
CONT_ASSIGN	450	1	1	100.00
CONT_ASSIGN	452	1	1	100.00
ALWAYS	455	5	5	100.00
CONT_ASSIGN	496	1	1	100.00
CONT_ASSIGN	499	1	1	100.00
CONT_ASSIGN	505	1	1	100.00
CONT_ASSIGN	510	1	1	100.00
CONT_ASSIGN	511	1	1	100.00
CONT_ASSIGN	513	1	1	100.00
CONT_ASSIGN	514	1	1	100.00
CONT_ASSIGN	515	1	1	100.00
ALWAYS	519	8	8	100.00
CONT_ASSIGN	588	1	1	100.00
ALWAYS	593	3	3	100.00
ALWAYS	601	3	3	100.00
ALWAYS	606	10	8	80.00
CONT_ASSIGN	623	1	1	100.00
CONT_ASSIGN	624	1	1	100.00
CONT_ASSIGN	631	1	1	100.00
CONT_ASSIGN	632	1	1	100.00
CONT_ASSIGN	743	1	1	100.00
CONT_ASSIGN	772	1	1	100.00
CONT_ASSIGN	773	1	1	100.00
CONT_ASSIGN	774	1	1	100.00
CONT_ASSIGN	779	1	1	100.00
CONT_ASSIGN	784	1	1	100.00
ALWAYS	787	6	6	100.00
CONT_ASSIGN	803	1	1	100.00
ALWAYS	808	7	7	100.00
CONT_ASSIGN	849	1	1	100.00
CONT_ASSIGN	853	1	1	100.00
ALWAYS	855	3	3	100.00
CONT_ASSIGN	861	1	1	100.00
ALWAYS	883	6	6	100.00
ALWAYS	890	6	6	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_hmac_0.1/rtl/hmac.sv' or '../src/lowrisc_ip_hmac_0.1/rtl/hmac.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
135	1	1
136	1	1
137	1	1
149	1	1
150	1	1
152	1	1
154	1	1
156	1	1
157	1	1
159	0	1
			MISSING_ELSE
164	1	1
165	1	1
166	1	1
			MISSING_ELSE
171	0	1
175	0	1
			==> MISSING_ELSE
180	0	1
181	0	1
182	0	1
			==> MISSING_ELSE
191	1	1
192	1	1
194	1	1
198	1	1
199	1	1
203	1	1
204	1	1
205	1	1
206	1	1
208	1	1
209	1	1
210	1	1
			MISSING_ELSE
			MISSING_ELSE
217	2	2
218	1	1
227	1	1
229	1	1
231	1	1
232	1	1
			MISSING_ELSE
235	1	1
237	1	1
238	1	1
240	1	1
242	1	1
243	1	1
248	1	1
250	1	1
251	1	1
253	1	1
254	1	1
256	1	1
257	1	1
259	1	1
260	1	1
262	1	1
263	1	1
			MISSING_ELSE
270	1	1
274	1	1
275	1	1
277	1	1
279	1	1
280	1	1
281	1	1
282	1	1
291	1	1
294	2	2
295	1	1
298	1	1
300	1	1
301	1	1
302	1	1
303	1	1
304	1	1
305	1	1
313	1	1
314	1	1
316	1	1
317	1	1
318	1	1
319	1	1
320	1	1
321	1	1
323	1	1
324	1	1
325	1	1
326	1	1
329	1	1
330	1	1
335	1	1
336	1	1
337	1	1
338	1	1
341	1	1
342	1	1
343	1	1
344	1	1
345	1	1
346	1	1
			MISSING_ELSE
351	1	1
352	1	1
379	1	1
380	1	1
			MISSING_ELSE
386	1	1
387	1	1
388	1	1
389	1	1
390	1	1
391	1	1
			MISSING_ELSE
435	1	1
442	1	1
450	1	1
452	1	1
455	1	1
456	1	1
457	1	1
459	1	1
460	1	1
496	1	1
499	1	1
505	1	1
510	1	1
511	1	1
513	1	1
514	1	1
515	1	1
519	1	1
520	1	1
521	1	1
523	1	1
524	1	1
526	1	1
527	1	1
			==> MISSING_ELSE
530	1	1
588	1	1
593	1	1
594	1	1
595	1	1
601	2	2
602	1	1
606	1	1
607	1	1
608	1	1
609	0	1
			MISSING_ELSE
611	1	1
612	0	1
			MISSING_ELSE
			MISSING_ELSE
616	1	1
617	1	1
618	1	1
619	1	1
			MISSING_ELSE
623	1	1
624	1	1
631	1	1
632	1	1
743	1	1
772	1	1
773	1	1
774	1	1
779	1	1
784	1	1
787	1	1
788	1	1
789	1	1
790	1	1
791	1	1
			MISSING_ELSE
795	1	1
803	1	1
808	1	1
809	1	1
811	1	1
815	1	1
819	1	1
823	1	1
827	1	1
849	1	1
853	1	1
855	1	1
856	1	1
858	1	1
861	1	1
883	2	2
884	2	2
885	2	2
			MISSING_ELSE
890	2	2
891	2	2
892	2	2
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut

	Total	Covered	Percent
Conditions	162	138	85.19
Logical	162	138	85.19
Non-Logical	0	0
Event	0	0

 LINE       237
 EXPRESSION (digest_size_started_q == SHA2_256)
            -----------------1-----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       250
 EXPRESSION ((digest_size_started_q == SHA2_384) || (digest_size_started_q == SHA2_512))
             -----------------1-----------------    -----------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T4,T5
1	0	Covered	T1,T3,T4

 LINE       250
 SUB-EXPRESSION (digest_size_started_q == SHA2_384)
                -----------------1-----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       250
 SUB-EXPRESSION (digest_size_started_q == SHA2_512)
                -----------------1-----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T5

 LINE       251
 EXPRESSION (((i % 2) == 0) && (i < 15))
             -------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Not Covered
1	1	Covered	T1,T3,T4

 LINE       251
 SUB-EXPRESSION ((i % 2) == 0)
                -------1------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T3,T4

 LINE       257
 EXPRESSION (reg2hw.digest[i].qe | reg2hw.digest[(i + 1)].qe)
             ---------1---------   ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T4
0	1	Not Covered
1	0	Not Covered

 LINE       263
 EXPRESSION (reg2hw.digest[i].qe | reg2hw.digest[(i - 1)].qe)
             ---------1---------   ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T4
0	1	Not Covered
1	0	Not Covered

 LINE       291
 EXPRESSION (hash_start_or_continue ? digest_size : digest_size_started_q)
             -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       323
 EXPRESSION (reg2hw.cmd.hash_start.qe & reg2hw.cmd.hash_start.q)
             ------------1-----------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       324
 EXPRESSION (reg2hw.cmd.hash_stop.qe & reg2hw.cmd.hash_stop.q)
             -----------1-----------   -----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       325
 EXPRESSION (reg2hw.cmd.hash_continue.qe & reg2hw.cmd.hash_continue.q)
             -------------1-------------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       326
 EXPRESSION (reg2hw.cmd.hash_process.qe & reg2hw.cmd.hash_process.q)
             -------------1------------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       335
 EXPRESSION (reg_hash_start & sha_en & ((~cfg_block)) & ((~invalid_config)))
             -------1------   ---2--   -------3------   ---------4---------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Covered	T1,T2,T3
1	0	1	1	Covered	T23,T24,T25
1	1	0	1	Covered	T23,T26,T11
1	1	1	0	Covered	T1,T3,T4
1	1	1	1	Covered	T1,T2,T3

 LINE       336
 EXPRESSION (reg_hash_continue & sha_en & ((~cfg_block)) & ((~invalid_config)))
             --------1--------   ---2--   -------3------   ---------4---------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Covered	T1,T2,T3
1	0	1	1	Not Covered
1	1	0	1	Not Covered
1	1	1	0	Not Covered
1	1	1	1	Not Covered

 LINE       337
 EXPRESSION (reg_hash_process & sha_en & cfg_block & ((~invalid_config)))
             --------1-------   ---2--   ----3----   ---------4---------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Covered	T1,T2,T3
1	0	1	1	Not Covered
1	1	0	1	Covered	T27
1	1	1	0	Not Covered
1	1	1	1	Covered	T1,T2,T3

 LINE       338
 EXPRESSION (hash_start | hash_continue)
             -----1----   ------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T2,T3

 LINE       345
 EXPRESSION (reg_hash_done || reg_hash_stop)
             ------1------    ------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T2,T3

 LINE       379
 EXPRESSION (((!cfg_block)) && reg2hw.cfg.hmac_en.qe)
             -------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T7,T28
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       435
 EXPRESSION (fifo_empty_q & ((~fifo_empty)))
             ------1-----   -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       442
 EXPRESSION 
 Number  Term
      1  fifo_full ? 1'b1 : (fifo_empty_negedge ? 1'b0 : ((reg_hash_start || reg_hash_continue || reg_hash_process || reg_hash_stop) ? 1'b0 : fifo_full_seen_q)))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       442
 SUB-EXPRESSION (fifo_empty_negedge ? 1'b0 : ((reg_hash_start || reg_hash_continue || reg_hash_process || reg_hash_stop) ? 1'b0 : fifo_full_seen_q))
                 ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       442
 SUB-EXPRESSION ((reg_hash_start || reg_hash_continue || reg_hash_process || reg_hash_stop) ? 1'b0 : fifo_full_seen_q)
                 -------------------------------------1------------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       442
 SUB-EXPRESSION (reg_hash_start || reg_hash_continue || reg_hash_process || reg_hash_stop)
                 -------1------    --------2--------    --------3-------    ------4------

-1-	-2-	-3-	-4-	Status	Tests
0	0	0	0	Covered	T1,T2,T3
0	0	0	1	Not Covered
0	0	1	0	Covered	T1,T2,T3
0	1	0	0	Not Covered
1	0	0	0	Covered	T1,T2,T3

 LINE       450
 EXPRESSION (((~msg_allowed)) || ((~fifo_full_seen_q)))
             --------1-------    ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T16,T29,T30
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       452
 EXPRESSION (fifo_empty_gate ? 1'b0 : fifo_empty)
             -------1-------

-1-	Status	Tests
0	Covered	T16,T29,T30
1	Covered	T1,T2,T3

 LINE       496
 EXPRESSION (msg_fifo_req & ((~msg_fifo_we)))
             ------1-----   --------2-------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Excluded		VC_COV_UNR

 LINE       499
 EXPRESSION (msg_fifo_req & ((~hmac_fifo_wsel)) & packer_ready)
             ------1-----   ---------2---------   ------3-----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Unreachable	T17,T18,T19
1	1	1	Covered	T1,T2,T3

 LINE       515
 EXPRESSION ((hmac_fifo_wsel && fifo_wready) ? hmac_fifo_wvalid : reg_fifo_wvalid)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       515
 SUB-EXPRESSION (hmac_fifo_wsel && fifo_wready)
                 -------1------    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       521
 EXPRESSION (digest_size == SHA2_256)
            ------------1------------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T2,T4

 LINE       524
 EXPRESSION ((digest_size == SHA2_384) || (digest_size == SHA2_512))
             ------------1------------    ------------2------------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Covered	T3,T4,T9
1	0	Covered	T1,T3,T4

 LINE       524
 SUB-EXPRESSION (digest_size == SHA2_384)
                ------------1------------

-1-	Status	Tests
0	Covered	T3,T4,T9
1	Covered	T1,T3,T4

 LINE       524
 SUB-EXPRESSION (digest_size == SHA2_512)
                ------------1------------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T3,T4,T9

 LINE       540
 EXPRESSION (fifo_wvalid & sha_en)
             -----1-----   ---2--

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T2,T3
1	0	Excluded		VC_COV_UNR
1	1	Covered	T1,T2,T3

 LINE       588
 EXPRESSION (msg_fifo_req & msg_fifo_we & ((~hmac_fifo_wsel)) & msg_allowed)
             ------1-----   -----2-----   ---------3---------   -----4-----

-1-	-2-	-3-	-4-	Status	Tests	Exclude Annotation
0	1	1	1	Covered	T1,T2,T3
1	0	1	1	Excluded		VC_COV_UNR
1	1	0	1	Excluded		VC_COV_UNR
1	1	1	0	Covered	T1,T3,T4
1	1	1	1	Covered	T1,T2,T3

 LINE       618
 EXPRESSION (msg_write && sha_en && packer_ready)
             ----1----    ---2--    ------3-----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Unreachable	T17,T18,T19
1	1	1	Covered	T1,T2,T3

 LINE       638
 EXPRESSION (msg_write & sha_en)
             ----1----   ---2--

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T2,T3
1	0	Excluded		VC_COV_UNR
1	1	Covered	T1,T2,T3

 LINE       638
 EXPRESSION (fifo_wready & ((~hmac_fifo_wsel)))
             -----1-----   ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       743
 SUB-EXPRESSION (reg2hw.alert_test.q & reg2hw.alert_test.qe)
                 ---------1---------   ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T20,T21,T22
1	0	Covered	T1,T2,T3
1	1	Covered	T20,T22,T31

 LINE       772
 EXPRESSION ((reg_hash_start | reg_hash_continue) & ((~sha_en)))
             ------------------1-----------------   -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T23,T24,T11

 LINE       772
 SUB-EXPRESSION (reg_hash_start | reg_hash_continue)
                 -------1------   --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T2,T3

 LINE       773
 EXPRESSION ((reg_hash_start | reg_hash_continue) & cfg_block)
             ------------------1-----------------   ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T23,T26,T11

 LINE       773
 SUB-EXPRESSION (reg_hash_start | reg_hash_continue)
                 -------1------   --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T2,T3

 LINE       774
 EXPRESSION (msg_fifo_req & ((~msg_allowed)))
             ------1-----   --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T4

 LINE       779
 EXPRESSION ((digest_size == SHA2_None) | ((key_length == Key_None) && hmac_en) | ((key_length == Key_1024) && (digest_size == SHA2_256) && hmac_en))
             -------------1------------   ------------------2------------------   ---------------------------------3--------------------------------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T4,T5,T6
0	1	0	Covered	T1,T3,T4
1	0	0	Covered	T1,T2,T3

 LINE       779
 SUB-EXPRESSION (digest_size == SHA2_None)
                -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       779
 SUB-EXPRESSION ((key_length == Key_None) && hmac_en)
                 ------------1-----------    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T4

 LINE       779
 SUB-EXPRESSION (key_length == Key_None)
                ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       779
 SUB-EXPRESSION ((key_length == Key_1024) && (digest_size == SHA2_256) && hmac_en)
                 ------------1-----------    ------------2------------    ---3---

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T4
1	0	1	Covered	T4,T15,T9
1	1	0	Covered	T4,T5,T9
1	1	1	Covered	T4,T5,T6

 LINE       779
 SUB-EXPRESSION (key_length == Key_1024)
                ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T15

 LINE       779
 SUB-EXPRESSION (digest_size == SHA2_256)
                ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       784
 EXPRESSION (reg_hash_start & invalid_config)
             -------1------   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T4

 LINE       803
 EXPRESSION 
 Number  Term
      1  ((~reg2hw.intr_state.hmac_err.q)) & 
      2  (hash_start_sha_disabled | update_seckey_inprocess | hash_start_active | msg_push_not_allowed | invalid_config_atstart))

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       803
 SUB-EXPRESSION (hash_start_sha_disabled | update_seckey_inprocess | hash_start_active | msg_push_not_allowed | invalid_config_atstart)
                 -----------1-----------   -----------2-----------   --------3--------   ----------4---------   -----------5----------

-1-	-2-	-3-	-4-	-5-	Status	Tests
0	0	0	0	0	Covered	T1,T2,T3
0	0	0	0	1	Covered	T1,T3,T4
0	0	0	1	0	Covered	T1,T3,T4
0	0	1	0	0	Covered	T23,T26,T11
0	1	0	0	0	Covered	T2,T32,T7
1	0	0	0	0	Covered	T23,T24,T25

 LINE       849
 EXPRESSION (((!reg_fifo_wvalid)) && ((!fifo_rvalid)) && hmac_core_idle && sha_core_idle)
             ----------1---------    --------2-------    -------3------    ------4------

-1-	-2-	-3-	-4-	Status	Tests	Exclude Annotation
0	1	1	1	Excluded		VC_COV_UNR
1	0	1	1	Not Covered
1	1	0	1	Covered	T1,T2,T3
1	1	1	0	Covered	T3,T4,T5
1	1	1	1	Covered	T1,T2,T3

---

Toggle Coverage for Instance : tb.dut

	Total	Covered	Percent
Totals	30	30	100.00
Total Bits	346	346	100.00
Total Bits 0->1	173	173	100.00
Total Bits 1->0	173	173	100.00

Ports	30	30	100.00
Port Bits	346	346	100.00
Port Bits 0->1	173	173	100.00
Port Bits 1->0	173	173	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T33,T34,T35	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T2,T3,T15	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T3,T4,T15	Yes	T3,T4,T15	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_error	Yes	Yes	T11,T12,T13	Yes	T11,T12,T13	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T20,T22,T31	Yes	T20,T22,T31	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T20,T22,T31	Yes	T20,T22,T31	OUTPUT
intr_hmac_done_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
intr_fifo_empty_o	Yes	Yes	T16,T29,T36	Yes	T16,T29,T36	OUTPUT
intr_hmac_err_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
idle_o[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT

*Tests covering at least one bit in the range

---

FSM Coverage for Instance : tb.dut

Summary for FSM :: done_state_q

	Total	Covered	Percent
States	4	2	50.00	(Not included in score)
Transitions	5	2	40.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: done_state_q

---

states	Line No.	Covered	Tests
DoneAwaitCmd	166	Covered	T1,T2,T3
DoneAwaitHashComplete	175	Not Covered
DoneAwaitHashDone	156	Covered	T1,T2,T3
DoneAwaitMessageComplete	159	Not Covered

transitions	Line No.	Covered	Tests
DoneAwaitCmd->DoneAwaitHashDone	156	Covered	T1,T2,T3
DoneAwaitCmd->DoneAwaitMessageComplete	159	Not Covered
DoneAwaitHashComplete->DoneAwaitCmd	182	Not Covered
DoneAwaitHashDone->DoneAwaitCmd	166	Covered	T1,T2,T3
DoneAwaitMessageComplete->DoneAwaitHashComplete	175	Not Covered

---

Branch Coverage for Instance : tb.dut

	Line No.	Total	Covered	Percent
Branches		91	82	90.11
TERNARY	291	2	2	100.00
TERNARY	442	4	4	100.00
TERNARY	452	2	2	100.00
TERNARY	515	2	2	100.00
CASE	152	10	4	40.00
IF	191	2	2	100.00
IF	204	3	3	100.00
IF	217	2	2	100.00
IF	229	2	2	100.00
IF	237	5	5	100.00
CASE	279	4	4	100.00
IF	294	2	2	100.00
CASE	300	6	6	100.00
IF	341	4	4	100.00
IF	351	3	3	100.00
IF	386	4	4	100.00
IF	455	2	2	100.00
IF	519	4	3	75.00
IF	601	2	2	100.00
IF	607	5	3	60.00
IF	616	3	3	100.00
IF	788	2	2	100.00
CASE	809	6	6	100.00
IF	855	2	2	100.00
IF	883	4	4	100.00
IF	890	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_hmac_0.1/rtl/hmac.sv' or '../src/lowrisc_ip_hmac_0.1/rtl/hmac.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	291	(hash_start_or_continue) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	442	(fifo_full) ? 
-2-:	442	(fifo_empty_negedge) ? 
-3-:	442	((((reg_hash_start || reg_hash_continue) || reg_hash_process) || reg_hash_stop)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	452	(fifo_empty_gate) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T16,T29,T30

	LineNo.	Expression
-1-:	515	((hmac_fifo_wsel && fifo_wready)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	152	case (done_state_q)
-2-:	154	if (sha_hash_process)
-3-:	157	if (reg_hash_stop)
-4-:	164	if (reg_hash_done)
-5-:	171	if (digest_on_blk)
-6-:	180	if ((!hash_running))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	Status	Tests
DoneAwaitCmd	1	-	-	-	-	Covered	T1,T2,T3
DoneAwaitCmd	0	1	-	-	-	Not Covered
DoneAwaitCmd	0	0	-	-	-	Covered	T1,T2,T3
DoneAwaitHashDone	-	-	1	-	-	Covered	T1,T2,T3
DoneAwaitHashDone	-	-	0	-	-	Covered	T1,T2,T3
DoneAwaitMessageComplete	-	-	-	1	-	Not Covered
DoneAwaitMessageComplete	-	-	-	0	-	Not Covered
DoneAwaitHashComplete	-	-	-	-	1	Not Covered
DoneAwaitHashComplete	-	-	-	-	0	Not Covered
default	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	191	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	204	if (wipe_secret)
-2-:	206	if ((!cfg_block))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T37,T38,T39
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	217	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	229	if ((i < 8))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	237	if ((digest_size_started_q == SHA2_256))
-2-:	238	if ((i < 8))
-3-:	250	if (((digest_size_started_q == SHA2_384) || (digest_size_started_q == SHA2_512)))
-4-:	251	if ((((i % 2) == 0) && (i < 15)))

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	1	-	-	Covered	T1,T2,T4
1	0	-	-	Covered	T1,T2,T4
0	-	1	1	Covered	T1,T3,T4
0	-	1	0	Covered	T1,T3,T4
0	-	0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	279	case (digest_size_supplied)

Branches:

-1-	Status	Tests
SHA2_256	Covered	T1,T2,T4
SHA2_384	Covered	T1,T3,T4
SHA2_512	Covered	T1,T3,T4
default	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	294	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	300	case (key_length_supplied)

Branches:

-1-	Status	Tests
Key_128	Covered	T1,T4,T5
Key_256	Covered	T1,T2,T3
Key_384	Covered	T1,T3,T4
Key_512	Covered	T1,T3,T4
Key_1024	Covered	T3,T4,T15
default	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	341	if ((!rst_ni))
-2-:	343	if (hash_start_or_continue)
-3-:	345	if ((reg_hash_done || reg_hash_stop))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	351	if ((!rst_ni))
-2-:	379	if (((!cfg_block) && reg2hw.cfg.hmac_en.qe))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	386	if ((!rst_ni))
-2-:	388	if (hash_start_or_continue)
-3-:	390	if (packer_flush_done)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	455	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	519	if (hmac_fifo_wsel)
-2-:	521	if ((digest_size == SHA2_256))
-3-:	524	if (((digest_size == SHA2_384) || (digest_size == SHA2_512)))

Branches:

-1-	-2-	-3-	Status	Tests
1	1	-	Covered	T1,T2,T4
1	0	1	Covered	T1,T3,T4
1	0	0	Not Covered
0	-	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	601	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	607	if ((!cfg_block))
-2-:	608	if (reg2hw.msg_length_lower.qe)
-3-:	611	if (reg2hw.msg_length_upper.qe)

Branches:

-1-	-2-	-3-	Status	Tests
1	1	-	Not Covered
1	0	-	Covered	T1,T2,T3
1	-	1	Not Covered
1	-	0	Covered	T1,T2,T3
0	-	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	616	if (hash_start)
-2-:	618	if (((msg_write && sha_en) && packer_ready))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	788	if (cfg_block)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	809	case (1'b1)

Branches:

-1-	Status	Tests
hash_start_sha_disabled	Covered	T23,T24,T11
update_seckey_inprocess	Covered	T2,T32,T7
hash_start_active	Covered	T23,T26,T11
msg_push_not_allowed	Covered	T1,T3,T4
invalid_config_atstart	Covered	T1,T3,T4
default	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	855	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	883	if ((!rst_ni))
-2-:	884	if (hash_process)
-3-:	885	if (reg_hash_done)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	890	if ((!rst_ni))
-2-:	891	if (hash_start_or_continue)
-3-:	892	if (hash_process)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertKnownO_A	233497995	233450128	0	0
FpvSecCmRegWeOnehotCheck_A	233497995	100	0	0
IntrFifoEmptyOKnown	233497995	233450128	0	0
IntrHmacDoneOKnown	233497995	233450128	0	0
TlOAReadyKnown	233497995	233450128	0	0
TlODValidKnown	233497995	233450128	0	0
ValidHashProcessAssert	233497995	18424	0	0
ValidHmacEnConditionAssert	233497995	9771	0	0
ValidWriteAssert	233497995	13097116	0	0
gen_assert_wmask_bytealign[0].unnamed$$_0	233497995	13097116	0	0
gen_assert_wmask_bytealign[1].unnamed$$_0	233497995	13097116	0	0
gen_assert_wmask_bytealign[2].unnamed$$_0	233497995	13097116	0	0
gen_assert_wmask_bytealign[3].unnamed$$_0	233497995	13097116	0	0

AlertKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	233497995	233450128	0	0
T1	78654	78562	0	0
T2	6197	6118	0	0
T3	94746	94653	0	0
T4	130171	130082	0	0
T5	6197	6126	0	0
T9	653915	653820	0	0
T15	9925	9858	0	0
T20	1091	1034	0	0
T21	657	557	0	0
T22	1067	1000	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	233497995	100	0	0
T33	3153	10	0	0
T36	15497	0	0	0
T40	0	20	0	0
T41	0	20	0	0
T42	0	20	0	0
T43	0	30	0	0
T44	3278	0	0	0
T45	283883	0	0	0
T46	369098	0	0	0
T47	51147	0	0	0
T48	125850	0	0	0
T49	25218	0	0	0
T50	12264	0	0	0
T51	94188	0	0	0

IntrFifoEmptyOKnown

Name	Attempts	Real Successes	Failures	Incomplete
Total	233497995	233450128	0	0
T1	78654	78562	0	0
T2	6197	6118	0	0
T3	94746	94653	0	0
T4	130171	130082	0	0
T5	6197	6126	0	0
T9	653915	653820	0	0
T15	9925	9858	0	0
T20	1091	1034	0	0
T21	657	557	0	0
T22	1067	1000	0	0

IntrHmacDoneOKnown

Name	Attempts	Real Successes	Failures	Incomplete
Total	233497995	233450128	0	0
T1	78654	78562	0	0
T2	6197	6118	0	0
T3	94746	94653	0	0
T4	130171	130082	0	0
T5	6197	6126	0	0
T9	653915	653820	0	0
T15	9925	9858	0	0
T20	1091	1034	0	0
T21	657	557	0	0
T22	1067	1000	0	0

TlOAReadyKnown

Name	Attempts	Real Successes	Failures	Incomplete
Total	233497995	233450128	0	0
T1	78654	78562	0	0
T2	6197	6118	0	0
T3	94746	94653	0	0
T4	130171	130082	0	0
T5	6197	6126	0	0
T9	653915	653820	0	0
T15	9925	9858	0	0
T20	1091	1034	0	0
T21	657	557	0	0
T22	1067	1000	0	0

TlODValidKnown

Name	Attempts	Real Successes	Failures	Incomplete
Total	233497995	233450128	0	0
T1	78654	78562	0	0
T2	6197	6118	0	0
T3	94746	94653	0	0
T4	130171	130082	0	0
T5	6197	6126	0	0
T9	653915	653820	0	0
T15	9925	9858	0	0
T20	1091	1034	0	0
T21	657	557	0	0
T22	1067	1000	0	0

ValidHashProcessAssert

Name	Attempts	Real Successes	Failures	Incomplete
Total	233497995	18424	0	0
T1	78654	7	0	0
T2	6197	4	0	0
T3	94746	4	0	0
T4	130171	10	0	0
T5	6197	8	0	0
T6	0	13	0	0
T9	653915	18	0	0
T10	0	22	0	0
T15	9925	1	0	0
T20	1091	0	0	0
T21	657	0	0	0
T22	1067	0	0	0
T52	0	8	0	0

ValidHmacEnConditionAssert

Name	Attempts	Real Successes	Failures	Incomplete
Total	233497995	9771	0	0
T1	78654	1	0	0
T2	6197	1	0	0
T3	94746	4	0	0
T4	130171	17	0	0
T5	6197	3	0	0
T6	0	16	0	0
T9	653915	25	0	0
T10	0	29	0	0
T15	9925	1	0	0
T20	1091	0	0	0
T21	657	0	0	0
T22	1067	0	0	0
T52	0	7	0	0

ValidWriteAssert

Name	Attempts	Real Successes	Failures	Incomplete
Total	233497995	13097116	0	0
T1	78654	14506	0	0
T2	6197	57	0	0
T3	94746	5688	0	0
T4	130171	23749	0	0
T5	6197	143	0	0
T6	0	25018	0	0
T9	653915	23961	0	0
T10	0	29499	0	0
T15	9925	388	0	0
T20	1091	0	0	0
T21	657	0	0	0
T22	1067	0	0	0
T52	0	179	0	0

gen_assert_wmask_bytealign[0].unnamed$$_0

Name	Attempts	Real Successes	Failures	Incomplete
Total	233497995	13097116	0	0
T1	78654	14506	0	0
T2	6197	57	0	0
T3	94746	5688	0	0
T4	130171	23749	0	0
T5	6197	143	0	0
T6	0	25018	0	0
T9	653915	23961	0	0
T10	0	29499	0	0
T15	9925	388	0	0
T20	1091	0	0	0
T21	657	0	0	0
T22	1067	0	0	0
T52	0	179	0	0

gen_assert_wmask_bytealign[1].unnamed$$_0

Name	Attempts	Real Successes	Failures	Incomplete
Total	233497995	13097116	0	0
T1	78654	14506	0	0
T2	6197	57	0	0
T3	94746	5688	0	0
T4	130171	23749	0	0
T5	6197	143	0	0
T6	0	25018	0	0
T9	653915	23961	0	0
T10	0	29499	0	0
T15	9925	388	0	0
T20	1091	0	0	0
T21	657	0	0	0
T22	1067	0	0	0
T52	0	179	0	0

gen_assert_wmask_bytealign[2].unnamed$$_0

Name	Attempts	Real Successes	Failures	Incomplete
Total	233497995	13097116	0	0
T1	78654	14506	0	0
T2	6197	57	0	0
T3	94746	5688	0	0
T4	130171	23749	0	0
T5	6197	143	0	0
T6	0	25018	0	0
T9	653915	23961	0	0
T10	0	29499	0	0
T15	9925	388	0	0
T20	1091	0	0	0
T21	657	0	0	0
T22	1067	0	0	0
T52	0	179	0	0

gen_assert_wmask_bytealign[3].unnamed$$_0

Name	Attempts	Real Successes	Failures	Incomplete
Total	233497995	13097116	0	0
T1	78654	14506	0	0
T2	6197	57	0	0
T3	94746	5688	0	0
T4	130171	23749	0	0
T5	6197	143	0	0
T6	0	25018	0	0
T9	653915	23961	0	0
T10	0	29499	0	0
T15	9925	388	0	0
T20	1091	0	0	0
T21	657	0	0	0
T22	1067	0	0	0
T52	0	179	0	0