Unified Coverage Report :: Module :: hmac_csr_assert_fpv

Module : hmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_hmac_csr_assert_0/hmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.hmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.hmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
85.18	95.81	85.19	100.00	40.00	90.11	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : hmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	265562534	1716106	0	0
intr_enable_rd_A	265562534	2809	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	265562534	1716106	0	0
T11	105477	47103	0	0
T12	140211	4832	0	0
T13	0	48252	0	0
T14	0	261190	0	0
T70	0	11	0	0
T73	0	211251	0	0
T74	0	180395	0	0
T75	0	338	0	0
T76	0	504	0	0
T77	0	189	0	0
T78	265934	0	0	0
T79	403310	0	0	0
T80	80937	0	0	0
T81	39030	0	0	0
T82	59343	0	0	0
T83	9393	0	0	0
T84	48289	0	0	0
T85	10228	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	265562534	2809	0	0
T65	0	200	0	0
T72	0	194	0	0
T86	927877	5	0	0
T87	0	69	0	0
T88	0	15	0	0
T89	0	41	0	0
T90	0	12	0	0
T91	0	9	0	0
T92	0	688	0	0
T93	0	16	0	0
T94	342743	0	0	0
T95	277323	0	0	0
T96	1157	0	0	0
T97	96234	0	0	0
T98	12968	0	0	0
T99	13850	0	0	0
T100	252721	0	0	0
T101	11540	0	0	0
T102	790695	0	0	0