Unified Coverage Report :: Module :: hmac

Module : hmac

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
84.40	95.83	82.39	100.00	40.00	88.17	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_hmac_0.1/rtl/hmac.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut	84.88	95.83	85.29	100.00	40.00	88.17	100.00

---

Module Instance : tb.dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
84.88	95.83	85.29	100.00	40.00	88.17	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.11	95.60	93.58	100.00	78.95	91.06	99.49

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_alert_tx[0].u_prim_alert_sender	100.00			100.00
hmac_csr_assert	100.00						100.00
intr_hw_fifo_empty	100.00	100.00	100.00			100.00	100.00
intr_hw_hmac_done	100.00	100.00	100.00			100.00	100.00
intr_hw_hmac_err	100.00	100.00	100.00			100.00	100.00
tlul_assert_device	100.00	100.00				100.00	100.00
u_hmac	93.46	95.45	90.16		100.00	88.24
u_msg_fifo	100.00	100.00	100.00			100.00	100.00
u_packer	100.00	100.00	100.00			100.00	100.00
u_prim_sha2_512	89.39	96.75	91.64		80.00	89.18
u_reg	98.23	94.86	97.60	100.00		98.72	100.00
u_tlul_adapter	88.61	94.06	87.26			80.25	92.86

Line Coverage for Module : hmac

	Line No.	Total	Covered	Percent
TOTAL		192	184	95.83
CONT_ASSIGN	135	1	1	100.00
CONT_ASSIGN	136	1	1	100.00
CONT_ASSIGN	137	1	1	100.00
CONT_ASSIGN	138	1	1	100.00
ALWAYS	150	15	9	60.00
ALWAYS	192	3	3	100.00
CONT_ASSIGN	199	1	1	100.00
CONT_ASSIGN	200	1	1	100.00
ALWAYS	204	7	7	100.00
ALWAYS	219	3	3	100.00
ALWAYS	231	19	19	100.00
CONT_ASSIGN	277	1	1	100.00
CONT_ASSIGN	282	1	1	100.00
CONT_ASSIGN	283	1	1	100.00
CONT_ASSIGN	285	1	1	100.00
ALWAYS	287	4	4	100.00
CONT_ASSIGN	299	1	1	100.00
ALWAYS	302	3	3	100.00
CONT_ASSIGN	306	1	1	100.00
ALWAYS	308	6	6	100.00
CONT_ASSIGN	321	1	1	100.00
CONT_ASSIGN	322	1	1	100.00
CONT_ASSIGN	323	1	1	100.00
CONT_ASSIGN	325	1	1	100.00
CONT_ASSIGN	326	1	1	100.00
CONT_ASSIGN	327	1	1	100.00
CONT_ASSIGN	328	1	1	100.00
CONT_ASSIGN	329	1	1	100.00
CONT_ASSIGN	330	1	1	100.00
CONT_ASSIGN	331	1	1	100.00
CONT_ASSIGN	333	1	1	100.00
CONT_ASSIGN	334	1	1	100.00
CONT_ASSIGN	335	1	1	100.00
CONT_ASSIGN	336	1	1	100.00
CONT_ASSIGN	339	1	1	100.00
CONT_ASSIGN	340	1	1	100.00
CONT_ASSIGN	345	1	1	100.00
CONT_ASSIGN	346	1	1	100.00
CONT_ASSIGN	347	1	1	100.00
CONT_ASSIGN	348	1	1	100.00
ALWAYS	351	6	6	100.00
ALWAYS	361	4	4	100.00
ALWAYS	400	6	6	100.00
CONT_ASSIGN	449	1	1	100.00
CONT_ASSIGN	456	1	1	100.00
CONT_ASSIGN	464	1	1	100.00
CONT_ASSIGN	466	1	1	100.00
ALWAYS	469	5	5	100.00
CONT_ASSIGN	510	1	1	100.00
CONT_ASSIGN	513	1	1	100.00
CONT_ASSIGN	519	1	1	100.00
CONT_ASSIGN	524	1	1	100.00
CONT_ASSIGN	525	1	1	100.00
CONT_ASSIGN	527	1	1	100.00
CONT_ASSIGN	528	1	1	100.00
CONT_ASSIGN	529	1	1	100.00
ALWAYS	533	8	8	100.00
CONT_ASSIGN	607	1	1	100.00
ALWAYS	612	3	3	100.00
ALWAYS	620	3	3	100.00
ALWAYS	625	10	8	80.00
CONT_ASSIGN	642	1	1	100.00
CONT_ASSIGN	643	1	1	100.00
CONT_ASSIGN	650	1	1	100.00
CONT_ASSIGN	651	1	1	100.00
CONT_ASSIGN	761	1	1	100.00
CONT_ASSIGN	790	1	1	100.00
CONT_ASSIGN	791	1	1	100.00
CONT_ASSIGN	792	1	1	100.00
CONT_ASSIGN	797	1	1	100.00
CONT_ASSIGN	802	1	1	100.00
ALWAYS	805	6	6	100.00
CONT_ASSIGN	821	1	1	100.00
ALWAYS	826	7	7	100.00
CONT_ASSIGN	868	1	1	100.00
CONT_ASSIGN	872	1	1	100.00
ALWAYS	874	3	3	100.00
CONT_ASSIGN	880	1	1	100.00
ALWAYS	902	6	6	100.00
ALWAYS	909	6	6	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_hmac_0.1/rtl/hmac.sv' or '../src/lowrisc_ip_hmac_0.1/rtl/hmac.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
135	1	1
136	1	1
137	1	1
138	1	1
150	1	1
151	1	1
153	1	1
155	1	1
157	1	1
158	1	1
160	0	1
			MISSING_ELSE
165	1	1
166	1	1
167	1	1
			MISSING_ELSE
172	0	1
176	0	1
			==> MISSING_ELSE
181	0	1
182	0	1
183	0	1
			==> MISSING_ELSE
192	1	1
193	1	1
195	1	1
199	1	1
200	1	1
204	1	1
205	1	1
206	1	1
207	1	1
209	1	1
210	1	1
212	1	1
			MISSING_ELSE
			MISSING_ELSE
219	2	2
220	1	1
231	1	1
232	1	1
234	1	1
236	1	1
240	1	1
242	1	1
243	1	1
244	1	1
246	1	1
249	1	1
252	1	1
			MISSING_ELSE
256	1	1
257	1	1
261	1	1
262	1	1
266	1	1
267	1	1
270	1	1
271	1	1
277	1	1
282	1	1
283	1	1
285	1	1
287	1	1
288	1	1
289	1	1
290	1	1
299	1	1
302	2	2
303	1	1
306	1	1
308	1	1
309	1	1
310	1	1
311	1	1
312	1	1
313	1	1
321	1	1
322	1	1
323	1	1
325	1	1
326	1	1
327	1	1
328	1	1
329	1	1
330	1	1
331	1	1
333	1	1
334	1	1
335	1	1
336	1	1
339	1	1
340	1	1
345	1	1
346	1	1
347	1	1
348	1	1
351	1	1
352	1	1
353	1	1
354	1	1
355	1	1
356	1	1
			MISSING_ELSE
361	1	1
362	1	1
393	1	1
394	1	1
			MISSING_ELSE
400	1	1
401	1	1
402	1	1
403	1	1
404	1	1
405	1	1
			MISSING_ELSE
449	1	1
456	1	1
464	1	1
466	1	1
469	1	1
470	1	1
471	1	1
473	1	1
474	1	1
510	1	1
513	1	1
519	1	1
524	1	1
525	1	1
527	1	1
528	1	1
529	1	1
533	1	1
534	1	1
535	1	1
537	1	1
538	1	1
540	1	1
541	1	1
			==> MISSING_ELSE
544	1	1
607	1	1
612	1	1
613	1	1
614	1	1
620	2	2
621	1	1
625	1	1
626	1	1
627	1	1
628	0	1
			MISSING_ELSE
630	1	1
631	0	1
			MISSING_ELSE
			MISSING_ELSE
635	1	1
636	1	1
637	1	1
638	1	1
			MISSING_ELSE
642	1	1
643	1	1
650	1	1
651	1	1
761	1	1
790	1	1
791	1	1
792	1	1
797	1	1
802	1	1
805	1	1
806	1	1
807	1	1
808	1	1
809	1	1
			MISSING_ELSE
813	1	1
821	1	1
826	1	1
827	1	1
830	1	1
834	1	1
838	1	1
842	1	1
846	1	1
868	1	1
872	1	1
874	1	1
875	1	1
877	1	1
880	1	1
902	2	2
903	2	2
904	2	2
			MISSING_ELSE
909	2	2
910	2	2
911	2	2
			MISSING_ELSE

---

Cond Coverage for Module : hmac

	Total	Covered	Percent
Conditions	176	145	82.39
Logical	176	145	82.39
Non-Logical	0	0
Event	0	0

 LINE       240
 EXPRESSION (digest_size == SHA2_256)
            ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       244
 EXPRESSION ((digest_size == SHA2_384) || (digest_size == SHA2_512))
             ------------1------------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T7
1	0	Covered	T1,T2,T3

 LINE       244
 SUB-EXPRESSION (digest_size == SHA2_384)
                ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       244
 SUB-EXPRESSION (digest_size == SHA2_512)
                ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T7

 LINE       246
 EXPRESSION (reg2hw.digest[(2 * i)].qe ? prim_sha2_pkg::conv_endian32(reg2hw.digest[(2 * i)].q, digest_swap) : digest[i][63:32])
             ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       249
 EXPRESSION (reg2hw.digest[((2 * i) + 1)].qe ? prim_sha2_pkg::conv_endian32(reg2hw.digest[((2 * i) + 1)].q, digest_swap) : digest[i][31:0])
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       252
 EXPRESSION (reg2hw.digest[(2 * i)].qe | reg2hw.digest[((2 * i) + 1)].qe)
             ------------1------------   ---------------2---------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Not Covered

 LINE       256
 EXPRESSION (digest_size_started_q == SHA2_256)
            -----------------1-----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       262
 EXPRESSION ((digest_size_started_q == SHA2_384) || (digest_size_started_q == SHA2_512))
             -----------------1-----------------    -----------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3

 LINE       262
 SUB-EXPRESSION (digest_size_started_q == SHA2_384)
                -----------------1-----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       262
 SUB-EXPRESSION (digest_size_started_q == SHA2_512)
                -----------------1-----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       299
 EXPRESSION (hash_start_or_continue ? digest_size : digest_size_started_q)
             -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       333
 EXPRESSION (reg2hw.cmd.hash_start.qe & reg2hw.cmd.hash_start.q)
             ------------1-----------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       334
 EXPRESSION (reg2hw.cmd.hash_stop.qe & reg2hw.cmd.hash_stop.q)
             -----------1-----------   -----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       335
 EXPRESSION (reg2hw.cmd.hash_continue.qe & reg2hw.cmd.hash_continue.q)
             -------------1-------------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       336
 EXPRESSION (reg2hw.cmd.hash_process.qe & reg2hw.cmd.hash_process.q)
             -------------1------------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       345
 EXPRESSION (reg_hash_start & sha_en & ((~cfg_block)) & ((~invalid_config)))
             -------1------   ---2--   -------3------   ---------4---------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Covered	T1,T2,T3
1	0	1	1	Covered	T2,T3,T7
1	1	0	1	Covered	T2,T3,T15
1	1	1	0	Covered	T1,T2,T3
1	1	1	1	Covered	T1,T2,T3

 LINE       346
 EXPRESSION (reg_hash_continue & sha_en & ((~cfg_block)) & ((~invalid_config)))
             --------1--------   ---2--   -------3------   ---------4---------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Covered	T1,T2,T3
1	0	1	1	Not Covered
1	1	0	1	Not Covered
1	1	1	0	Not Covered
1	1	1	1	Not Covered

 LINE       347
 EXPRESSION (reg_hash_process & sha_en & cfg_block & ((~invalid_config)))
             --------1-------   ---2--   ----3----   ---------4---------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Covered	T1,T2,T3
1	0	1	1	Not Covered
1	1	0	1	Not Covered
1	1	1	0	Not Covered
1	1	1	1	Covered	T1,T2,T3

 LINE       348
 EXPRESSION (hash_start | hash_continue)
             -----1----   ------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T2,T3

 LINE       355
 EXPRESSION (reg_hash_done || reg_hash_stop)
             ------1------    ------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T2,T3

 LINE       393
 EXPRESSION (((!cfg_block)) && reg2hw.cfg.hmac_en.qe)
             -------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T16
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       449
 EXPRESSION (fifo_empty_q & ((~fifo_empty)))
             ------1-----   -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       456
 EXPRESSION 
 Number  Term
      1  fifo_full ? 1'b1 : (fifo_empty_negedge ? 1'b0 : ((reg_hash_start || reg_hash_continue || reg_hash_process || reg_hash_stop) ? 1'b0 : fifo_full_seen_q)))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       456
 SUB-EXPRESSION (fifo_empty_negedge ? 1'b0 : ((reg_hash_start || reg_hash_continue || reg_hash_process || reg_hash_stop) ? 1'b0 : fifo_full_seen_q))
                 ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       456
 SUB-EXPRESSION ((reg_hash_start || reg_hash_continue || reg_hash_process || reg_hash_stop) ? 1'b0 : fifo_full_seen_q)
                 -------------------------------------1------------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       456
 SUB-EXPRESSION (reg_hash_start || reg_hash_continue || reg_hash_process || reg_hash_stop)
                 -------1------    --------2--------    --------3-------    ------4------

-1-	-2-	-3-	-4-	Status	Tests
0	0	0	0	Covered	T1,T2,T3
0	0	0	1	Not Covered
0	0	1	0	Covered	T1,T2,T3
0	1	0	0	Not Covered
1	0	0	0	Covered	T1,T2,T3

 LINE       464
 EXPRESSION (((~msg_allowed)) || ((~fifo_full_seen_q)))
             --------1-------    ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T14,T17,T18
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       466
 EXPRESSION (fifo_empty_gate ? 1'b0 : fifo_empty)
             -------1-------

-1-	Status	Tests
0	Covered	T14,T17,T18
1	Covered	T1,T2,T3

 LINE       510
 EXPRESSION (msg_fifo_req & ((~msg_fifo_we)))
             ------1-----   --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       513
 EXPRESSION (msg_fifo_req & ((~hmac_fifo_wsel)) & packer_ready)
             ------1-----   ---------2---------   ------3-----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Unreachable	T14,T17,T19
1	1	1	Covered	T1,T2,T3

 LINE       529
 EXPRESSION ((hmac_fifo_wsel && fifo_wready) ? hmac_fifo_wvalid : reg_fifo_wvalid)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       529
 SUB-EXPRESSION (hmac_fifo_wsel && fifo_wready)
                 -------1------    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       535
 EXPRESSION (digest_size == SHA2_256)
            ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       538
 EXPRESSION ((digest_size == SHA2_384) || (digest_size == SHA2_512))
             ------------1------------    ------------2------------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3

 LINE       538
 SUB-EXPRESSION (digest_size == SHA2_384)
                ------------1------------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T1,T2,T3

 LINE       538
 SUB-EXPRESSION (digest_size == SHA2_512)
                ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       554
 EXPRESSION (fifo_wvalid & sha_en)
             -----1-----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       607
 EXPRESSION (msg_fifo_req & msg_fifo_we & ((~hmac_fifo_wsel)) & msg_allowed)
             ------1-----   -----2-----   ---------3---------   -----4-----

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Covered	T1,T2,T3
1	0	1	1	Not Covered
1	1	0	1	Not Covered
1	1	1	0	Covered	T1,T2,T3
1	1	1	1	Covered	T1,T2,T3

 LINE       637
 EXPRESSION (msg_write && sha_en && packer_ready)
             ----1----    ---2--    ------3-----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Unreachable	T14,T17,T19
1	1	1	Covered	T1,T2,T3

 LINE       657
 EXPRESSION (msg_write & sha_en)
             ----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       657
 EXPRESSION (fifo_wready & ((~hmac_fifo_wsel)))
             -----1-----   ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       761
 SUB-EXPRESSION (reg2hw.alert_test.q & reg2hw.alert_test.qe)
                 ---------1---------   ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T20,T21,T22
1	0	Covered	T1,T2,T3
1	1	Covered	T23,T20,T21

 LINE       790
 EXPRESSION ((reg_hash_start | reg_hash_continue) & ((~sha_en)))
             ------------------1-----------------   -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T7

 LINE       790
 SUB-EXPRESSION (reg_hash_start | reg_hash_continue)
                 -------1------   --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T2,T3

 LINE       791
 EXPRESSION ((reg_hash_start | reg_hash_continue) & cfg_block)
             ------------------1-----------------   ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T15

 LINE       791
 SUB-EXPRESSION (reg_hash_start | reg_hash_continue)
                 -------1------   --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T2,T3

 LINE       792
 EXPRESSION (msg_fifo_req & ((~msg_allowed)))
             ------1-----   --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       797
 EXPRESSION ((digest_size == SHA2_None) | ((key_length == Key_None) && hmac_en) | ((key_length == Key_1024) && (digest_size == SHA2_256) && hmac_en))
             -------------1------------   ------------------2------------------   ---------------------------------3--------------------------------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T5
0	1	0	Covered	T1,T2,T3
1	0	0	Covered	T1,T2,T3

 LINE       797
 SUB-EXPRESSION (digest_size == SHA2_None)
                -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       797
 SUB-EXPRESSION ((key_length == Key_None) && hmac_en)
                 ------------1-----------    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       797
 SUB-EXPRESSION (key_length == Key_None)
                ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       797
 SUB-EXPRESSION ((key_length == Key_1024) && (digest_size == SHA2_256) && hmac_en)
                 ------------1-----------    ------------2------------    ---3---

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T2,T3,T14
1	1	1	Covered	T2,T3,T5

 LINE       797
 SUB-EXPRESSION (key_length == Key_1024)
                ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       797
 SUB-EXPRESSION (digest_size == SHA2_256)
                ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       802
 EXPRESSION ((reg_hash_start || reg_hash_continue) & invalid_config)
             ------------------1------------------   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       802
 SUB-EXPRESSION (reg_hash_start || reg_hash_continue)
                 -------1------    --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T2,T3

 LINE       821
 EXPRESSION 
 Number  Term
      1  ((~reg2hw.intr_state.hmac_err.q)) & 
      2  (hash_start_sha_disabled | update_seckey_inprocess | hash_start_active | msg_push_not_allowed | invalid_config_atstart))

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       821
 SUB-EXPRESSION (hash_start_sha_disabled | update_seckey_inprocess | hash_start_active | msg_push_not_allowed | invalid_config_atstart)
                 -----------1-----------   -----------2-----------   --------3--------   ----------4---------   -----------5----------

-1-	-2-	-3-	-4-	-5-	Status	Tests
0	0	0	0	0	Covered	T1,T2,T3
0	0	0	0	1	Covered	T1,T2,T3
0	0	0	1	0	Covered	T1,T2,T3
0	0	1	0	0	Covered	T2,T3,T15
0	1	0	0	0	Covered	T2,T3,T16
1	0	0	0	0	Covered	T2,T3,T7

 LINE       868
 EXPRESSION (((!reg_fifo_wvalid)) && ((!fifo_rvalid)) && hmac_core_idle && sha_core_idle)
             ----------1---------    --------2-------    -------3------    ------4------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Not Covered
1	0	1	1	Not Covered
1	1	0	1	Covered	T1,T2,T3
1	1	1	0	Covered	T1,T2,T3
1	1	1	1	Covered	T1,T2,T3

---

Toggle Coverage for Module : hmac

	Total	Covered	Percent
Totals	30	30	100.00
Total Bits	346	346	100.00
Total Bits 0->1	173	173	100.00
Total Bits 1->0	173	173	100.00

Ports	30	30	100.00
Port Bits	346	346	100.00
Port Bits 0->1	173	173	100.00
Port Bits 1->0	173	173	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T3,T14,T24	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T3,T16,T7	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T16,T7	Yes	T1,T16,T7	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_error	Yes	Yes	T24,T13,T25	Yes	T24,T13,T25	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T23,T20,T21	Yes	T23,T20,T21	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T23,T20,T21	Yes	T23,T20,T21	OUTPUT
intr_hmac_done_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
intr_fifo_empty_o	Yes	Yes	T3,T18,T24	Yes	T3,T18,T24	OUTPUT
intr_hmac_err_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
idle_o[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT

*Tests covering at least one bit in the range

---

FSM Coverage for Module : hmac

Summary for FSM :: done_state_q

	Total	Covered	Percent
States	4	2	50.00	(Not included in score)
Transitions	5	2	40.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: done_state_q

---

states	Line No.	Covered	Tests
DoneAwaitCmd	167	Covered	T1,T2,T3
DoneAwaitHashComplete	176	Not Covered
DoneAwaitHashDone	157	Covered	T1,T2,T3
DoneAwaitMessageComplete	160	Not Covered

transitions	Line No.	Covered	Tests
DoneAwaitCmd->DoneAwaitHashDone	157	Covered	T1,T2,T3
DoneAwaitCmd->DoneAwaitMessageComplete	160	Not Covered
DoneAwaitHashComplete->DoneAwaitCmd	183	Not Covered
DoneAwaitHashDone->DoneAwaitCmd	167	Covered	T1,T2,T3
DoneAwaitMessageComplete->DoneAwaitHashComplete	176	Not Covered

---

Branch Coverage for Module : hmac

	Line No.	Total	Covered	Percent
Branches		93	82	88.17
TERNARY	299	2	2	100.00
TERNARY	456	4	4	100.00
TERNARY	466	2	2	100.00
TERNARY	529	2	2	100.00
CASE	153	10	4	40.00
IF	192	2	2	100.00
IF	205	3	3	100.00
IF	219	2	2	100.00
IF	240	6	4	66.67
IF	256	3	3	100.00
CASE	287	4	4	100.00
IF	302	2	2	100.00
CASE	308	6	6	100.00
IF	351	4	4	100.00
IF	361	3	3	100.00
IF	400	4	4	100.00
IF	469	2	2	100.00
IF	533	4	3	75.00
IF	620	2	2	100.00
IF	626	5	3	60.00
IF	635	3	3	100.00
IF	806	2	2	100.00
CASE	827	6	6	100.00
IF	874	2	2	100.00
IF	902	4	4	100.00
IF	909	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_hmac_0.1/rtl/hmac.sv' or '../src/lowrisc_ip_hmac_0.1/rtl/hmac.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	299	(hash_start_or_continue) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	456	(fifo_full) ? 
-2-:	456	(fifo_empty_negedge) ? 
-3-:	456	((((reg_hash_start || reg_hash_continue) || reg_hash_process) || reg_hash_stop)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	466	(fifo_empty_gate) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T14,T17,T18

	LineNo.	Expression
-1-:	529	((hmac_fifo_wsel && fifo_wready)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	153	case (done_state_q)
-2-:	155	if (sha_hash_process)
-3-:	158	if (reg_hash_stop)
-4-:	165	if (reg_hash_done)
-5-:	172	if (digest_on_blk)
-6-:	181	if ((!hash_running))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	Status	Tests
DoneAwaitCmd	1	-	-	-	-	Covered	T1,T2,T3
DoneAwaitCmd	0	1	-	-	-	Not Covered
DoneAwaitCmd	0	0	-	-	-	Covered	T1,T2,T3
DoneAwaitHashDone	-	-	1	-	-	Covered	T1,T2,T3
DoneAwaitHashDone	-	-	0	-	-	Covered	T1,T2,T3
DoneAwaitMessageComplete	-	-	-	1	-	Not Covered
DoneAwaitMessageComplete	-	-	-	0	-	Not Covered
DoneAwaitHashComplete	-	-	-	-	1	Not Covered
DoneAwaitHashComplete	-	-	-	-	0	Not Covered
default	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	192	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	205	if (wipe_secret)
-2-:	207	if ((!cfg_block))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T3,T26,T27
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	240	if ((digest_size == SHA2_256))
-2-:	244	if (((digest_size == SHA2_384) || (digest_size == SHA2_512)))
-3-:	246	(reg2hw.digest[(2 * i)].qe) ? 
-4-:	249	(reg2hw.digest[((2 * i) + 1)].qe) ? 

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	1	-	Not Covered
0	1	0	-	Covered	T1,T2,T3
0	1	-	1	Not Covered
0	1	-	0	Covered	T1,T2,T3
0	0	-	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	256	if ((digest_size_started_q == SHA2_256))
-2-:	262	if (((digest_size_started_q == SHA2_384) || (digest_size_started_q == SHA2_512)))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	287	case (digest_size_supplied)

Branches:

-1-	Status	Tests
SHA2_256	Covered	T1,T2,T3
SHA2_384	Covered	T1,T2,T3
SHA2_512	Covered	T2,T3,T7
default	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	302	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	308	case (key_length_supplied)

Branches:

-1-	Status	Tests
Key_128	Covered	T1,T2,T3
Key_256	Covered	T1,T2,T3
Key_384	Covered	T2,T3,T7
Key_512	Covered	T1,T2,T3
Key_1024	Covered	T1,T2,T3
default	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	351	if ((!rst_ni))
-2-:	353	if (hash_start_or_continue)
-3-:	355	if ((reg_hash_done || reg_hash_stop))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	361	if ((!rst_ni))
-2-:	393	if (((!cfg_block) && reg2hw.cfg.hmac_en.qe))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	400	if ((!rst_ni))
-2-:	402	if (hash_start_or_continue)
-3-:	404	if (packer_flush_done)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	469	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	533	if (hmac_fifo_wsel)
-2-:	535	if ((digest_size == SHA2_256))
-3-:	538	if (((digest_size == SHA2_384) || (digest_size == SHA2_512)))

Branches:

-1-	-2-	-3-	Status	Tests
1	1	-	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	0	0	Not Covered
0	-	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	620	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	626	if ((!cfg_block))
-2-:	627	if (reg2hw.msg_length_lower.qe)
-3-:	630	if (reg2hw.msg_length_upper.qe)

Branches:

-1-	-2-	-3-	Status	Tests
1	1	-	Not Covered
1	0	-	Covered	T1,T2,T3
1	-	1	Not Covered
1	-	0	Covered	T1,T2,T3
0	-	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	635	if (hash_start)
-2-:	637	if (((msg_write && sha_en) && packer_ready))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	806	if (cfg_block)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	827	case (1'b1)

Branches:

-1-	Status	Tests
invalid_config_atstart	Covered	T1,T2,T3
hash_start_sha_disabled	Covered	T2,T3,T7
hash_start_active	Covered	T2,T3,T15
msg_push_not_allowed	Covered	T1,T2,T3
update_seckey_inprocess	Covered	T2,T3,T16
default	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	874	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	902	if ((!rst_ni))
-2-:	903	if (hash_process)
-3-:	904	if (reg_hash_done)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	909	if ((!rst_ni))
-2-:	910	if (hash_start_or_continue)
-3-:	911	if (hash_process)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Module : hmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertKnownO_A	389368484	389301884	0	0
FpvSecCmRegWeOnehotCheck_A	389368484	90	0	0
IntrFifoEmptyOKnown	389368484	389301884	0	0
IntrHmacDoneOKnown	389368484	389301884	0	0
TlOAReadyKnown	389368484	389301884	0	0
TlODValidKnown	389368484	389301884	0	0
ValidHashProcessAssert	389368484	35343	0	0
ValidHmacEnConditionAssert	389368484	9633	0	0
ValidWriteAssert	389368484	23150667	0	0
gen_assert_wmask_bytealign[0].unnamed$$_0	389368484	23150667	0	0
gen_assert_wmask_bytealign[1].unnamed$$_0	389368484	23150667	0	0
gen_assert_wmask_bytealign[2].unnamed$$_0	389368484	23150667	0	0
gen_assert_wmask_bytealign[3].unnamed$$_0	389368484	23150667	0	0

AlertKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389368484	389301884	0	0
T1	48200	48121	0	0
T2	202607	202537	0	0
T3	560284	560201	0	0
T4	489458	489389	0	0
T5	236355	236285	0	0
T6	90959	90861	0	0
T7	309839	309763	0	0
T14	66000	65868	0	0
T16	7299	7200	0	0
T23	767	675	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389368484	90	0	0
T28	3177	10	0	0
T29	0	10	0	0
T30	0	10	0	0
T31	0	30	0	0
T32	0	30	0	0
T33	17314	0	0	0
T34	182748	0	0	0
T35	868355	0	0	0
T36	63976	0	0	0
T37	284434	0	0	0
T38	789880	0	0	0
T39	9538	0	0	0
T40	12648	0	0	0
T41	509952	0	0	0

IntrFifoEmptyOKnown

Name	Attempts	Real Successes	Failures	Incomplete
Total	389368484	389301884	0	0
T1	48200	48121	0	0
T2	202607	202537	0	0
T3	560284	560201	0	0
T4	489458	489389	0	0
T5	236355	236285	0	0
T6	90959	90861	0	0
T7	309839	309763	0	0
T14	66000	65868	0	0
T16	7299	7200	0	0
T23	767	675	0	0

IntrHmacDoneOKnown

Name	Attempts	Real Successes	Failures	Incomplete
Total	389368484	389301884	0	0
T1	48200	48121	0	0
T2	202607	202537	0	0
T3	560284	560201	0	0
T4	489458	489389	0	0
T5	236355	236285	0	0
T6	90959	90861	0	0
T7	309839	309763	0	0
T14	66000	65868	0	0
T16	7299	7200	0	0
T23	767	675	0	0

TlOAReadyKnown

Name	Attempts	Real Successes	Failures	Incomplete
Total	389368484	389301884	0	0
T1	48200	48121	0	0
T2	202607	202537	0	0
T3	560284	560201	0	0
T4	489458	489389	0	0
T5	236355	236285	0	0
T6	90959	90861	0	0
T7	309839	309763	0	0
T14	66000	65868	0	0
T16	7299	7200	0	0
T23	767	675	0	0

TlODValidKnown

Name	Attempts	Real Successes	Failures	Incomplete
Total	389368484	389301884	0	0
T1	48200	48121	0	0
T2	202607	202537	0	0
T3	560284	560201	0	0
T4	489458	489389	0	0
T5	236355	236285	0	0
T6	90959	90861	0	0
T7	309839	309763	0	0
T14	66000	65868	0	0
T16	7299	7200	0	0
T23	767	675	0	0

ValidHashProcessAssert

Name	Attempts	Real Successes	Failures	Incomplete
Total	389368484	35343	0	0
T1	48200	7	0	0
T2	202607	10	0	0
T3	560284	407	0	0
T4	489458	21	0	0
T5	236355	15	0	0
T6	90959	7	0	0
T7	309839	1	0	0
T14	66000	23	0	0
T16	7299	4	0	0
T23	767	0	0	0
T42	0	34	0	0

ValidHmacEnConditionAssert

Name	Attempts	Real Successes	Failures	Incomplete
Total	389368484	9633	0	0
T1	48200	7	0	0
T2	202607	34	0	0
T3	560284	149	0	0
T4	489458	17	0	0
T5	236355	1	0	0
T6	90959	1	0	0
T7	309839	13	0	0
T14	66000	11	0	0
T16	7299	1	0	0
T23	767	0	0	0
T42	0	24	0	0

ValidWriteAssert

Name	Attempts	Real Successes	Failures	Incomplete
Total	389368484	23150667	0	0
T1	48200	8952	0	0
T2	202607	20356	0	0
T3	560284	276882	0	0
T4	489458	17712	0	0
T5	236355	44892	0	0
T6	90959	16926	0	0
T7	309839	9927	0	0
T14	66000	31724	0	0
T16	7299	51	0	0
T23	767	0	0	0
T42	0	584	0	0

gen_assert_wmask_bytealign[0].unnamed$$_0

Name	Attempts	Real Successes	Failures	Incomplete
Total	389368484	23150667	0	0
T1	48200	8952	0	0
T2	202607	20356	0	0
T3	560284	276882	0	0
T4	489458	17712	0	0
T5	236355	44892	0	0
T6	90959	16926	0	0
T7	309839	9927	0	0
T14	66000	31724	0	0
T16	7299	51	0	0
T23	767	0	0	0
T42	0	584	0	0

gen_assert_wmask_bytealign[1].unnamed$$_0

Name	Attempts	Real Successes	Failures	Incomplete
Total	389368484	23150667	0	0
T1	48200	8952	0	0
T2	202607	20356	0	0
T3	560284	276882	0	0
T4	489458	17712	0	0
T5	236355	44892	0	0
T6	90959	16926	0	0
T7	309839	9927	0	0
T14	66000	31724	0	0
T16	7299	51	0	0
T23	767	0	0	0
T42	0	584	0	0

gen_assert_wmask_bytealign[2].unnamed$$_0

Name	Attempts	Real Successes	Failures	Incomplete
Total	389368484	23150667	0	0
T1	48200	8952	0	0
T2	202607	20356	0	0
T3	560284	276882	0	0
T4	489458	17712	0	0
T5	236355	44892	0	0
T6	90959	16926	0	0
T7	309839	9927	0	0
T14	66000	31724	0	0
T16	7299	51	0	0
T23	767	0	0	0
T42	0	584	0	0

gen_assert_wmask_bytealign[3].unnamed$$_0

Name	Attempts	Real Successes	Failures	Incomplete
Total	389368484	23150667	0	0
T1	48200	8952	0	0
T2	202607	20356	0	0
T3	560284	276882	0	0
T4	489458	17712	0	0
T5	236355	44892	0	0
T6	90959	16926	0	0
T7	309839	9927	0	0
T14	66000	31724	0	0
T16	7299	51	0	0
T23	767	0	0	0
T42	0	584	0	0

Line Coverage for Instance : tb.dut

	Line No.	Total	Covered	Percent
TOTAL		192	184	95.83
CONT_ASSIGN	135	1	1	100.00
CONT_ASSIGN	136	1	1	100.00
CONT_ASSIGN	137	1	1	100.00
CONT_ASSIGN	138	1	1	100.00
ALWAYS	150	15	9	60.00
ALWAYS	192	3	3	100.00
CONT_ASSIGN	199	1	1	100.00
CONT_ASSIGN	200	1	1	100.00
ALWAYS	204	7	7	100.00
ALWAYS	219	3	3	100.00
ALWAYS	231	19	19	100.00
CONT_ASSIGN	277	1	1	100.00
CONT_ASSIGN	282	1	1	100.00
CONT_ASSIGN	283	1	1	100.00
CONT_ASSIGN	285	1	1	100.00
ALWAYS	287	4	4	100.00
CONT_ASSIGN	299	1	1	100.00
ALWAYS	302	3	3	100.00
CONT_ASSIGN	306	1	1	100.00
ALWAYS	308	6	6	100.00
CONT_ASSIGN	321	1	1	100.00
CONT_ASSIGN	322	1	1	100.00
CONT_ASSIGN	323	1	1	100.00
CONT_ASSIGN	325	1	1	100.00
CONT_ASSIGN	326	1	1	100.00
CONT_ASSIGN	327	1	1	100.00
CONT_ASSIGN	328	1	1	100.00
CONT_ASSIGN	329	1	1	100.00
CONT_ASSIGN	330	1	1	100.00
CONT_ASSIGN	331	1	1	100.00
CONT_ASSIGN	333	1	1	100.00
CONT_ASSIGN	334	1	1	100.00
CONT_ASSIGN	335	1	1	100.00
CONT_ASSIGN	336	1	1	100.00
CONT_ASSIGN	339	1	1	100.00
CONT_ASSIGN	340	1	1	100.00
CONT_ASSIGN	345	1	1	100.00
CONT_ASSIGN	346	1	1	100.00
CONT_ASSIGN	347	1	1	100.00
CONT_ASSIGN	348	1	1	100.00
ALWAYS	351	6	6	100.00
ALWAYS	361	4	4	100.00
ALWAYS	400	6	6	100.00
CONT_ASSIGN	449	1	1	100.00
CONT_ASSIGN	456	1	1	100.00
CONT_ASSIGN	464	1	1	100.00
CONT_ASSIGN	466	1	1	100.00
ALWAYS	469	5	5	100.00
CONT_ASSIGN	510	1	1	100.00
CONT_ASSIGN	513	1	1	100.00
CONT_ASSIGN	519	1	1	100.00
CONT_ASSIGN	524	1	1	100.00
CONT_ASSIGN	525	1	1	100.00
CONT_ASSIGN	527	1	1	100.00
CONT_ASSIGN	528	1	1	100.00
CONT_ASSIGN	529	1	1	100.00
ALWAYS	533	8	8	100.00
CONT_ASSIGN	607	1	1	100.00
ALWAYS	612	3	3	100.00
ALWAYS	620	3	3	100.00
ALWAYS	625	10	8	80.00
CONT_ASSIGN	642	1	1	100.00
CONT_ASSIGN	643	1	1	100.00
CONT_ASSIGN	650	1	1	100.00
CONT_ASSIGN	651	1	1	100.00
CONT_ASSIGN	761	1	1	100.00
CONT_ASSIGN	790	1	1	100.00
CONT_ASSIGN	791	1	1	100.00
CONT_ASSIGN	792	1	1	100.00
CONT_ASSIGN	797	1	1	100.00
CONT_ASSIGN	802	1	1	100.00
ALWAYS	805	6	6	100.00
CONT_ASSIGN	821	1	1	100.00
ALWAYS	826	7	7	100.00
CONT_ASSIGN	868	1	1	100.00
CONT_ASSIGN	872	1	1	100.00
ALWAYS	874	3	3	100.00
CONT_ASSIGN	880	1	1	100.00
ALWAYS	902	6	6	100.00
ALWAYS	909	6	6	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_hmac_0.1/rtl/hmac.sv' or '../src/lowrisc_ip_hmac_0.1/rtl/hmac.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
135	1	1
136	1	1
137	1	1
138	1	1
150	1	1
151	1	1
153	1	1
155	1	1
157	1	1
158	1	1
160	0	1
			MISSING_ELSE
165	1	1
166	1	1
167	1	1
			MISSING_ELSE
172	0	1
176	0	1
			==> MISSING_ELSE
181	0	1
182	0	1
183	0	1
			==> MISSING_ELSE
192	1	1
193	1	1
195	1	1
199	1	1
200	1	1
204	1	1
205	1	1
206	1	1
207	1	1
209	1	1
210	1	1
212	1	1
			MISSING_ELSE
			MISSING_ELSE
219	2	2
220	1	1
231	1	1
232	1	1
234	1	1
236	1	1
240	1	1
242	1	1
243	1	1
244	1	1
246	1	1
249	1	1
252	1	1
			MISSING_ELSE
256	1	1
257	1	1
261	1	1
262	1	1
266	1	1
267	1	1
270	1	1
271	1	1
277	1	1
282	1	1
283	1	1
285	1	1
287	1	1
288	1	1
289	1	1
290	1	1
299	1	1
302	2	2
303	1	1
306	1	1
308	1	1
309	1	1
310	1	1
311	1	1
312	1	1
313	1	1
321	1	1
322	1	1
323	1	1
325	1	1
326	1	1
327	1	1
328	1	1
329	1	1
330	1	1
331	1	1
333	1	1
334	1	1
335	1	1
336	1	1
339	1	1
340	1	1
345	1	1
346	1	1
347	1	1
348	1	1
351	1	1
352	1	1
353	1	1
354	1	1
355	1	1
356	1	1
			MISSING_ELSE
361	1	1
362	1	1
393	1	1
394	1	1
			MISSING_ELSE
400	1	1
401	1	1
402	1	1
403	1	1
404	1	1
405	1	1
			MISSING_ELSE
449	1	1
456	1	1
464	1	1
466	1	1
469	1	1
470	1	1
471	1	1
473	1	1
474	1	1
510	1	1
513	1	1
519	1	1
524	1	1
525	1	1
527	1	1
528	1	1
529	1	1
533	1	1
534	1	1
535	1	1
537	1	1
538	1	1
540	1	1
541	1	1
			==> MISSING_ELSE
544	1	1
607	1	1
612	1	1
613	1	1
614	1	1
620	2	2
621	1	1
625	1	1
626	1	1
627	1	1
628	0	1
			MISSING_ELSE
630	1	1
631	0	1
			MISSING_ELSE
			MISSING_ELSE
635	1	1
636	1	1
637	1	1
638	1	1
			MISSING_ELSE
642	1	1
643	1	1
650	1	1
651	1	1
761	1	1
790	1	1
791	1	1
792	1	1
797	1	1
802	1	1
805	1	1
806	1	1
807	1	1
808	1	1
809	1	1
			MISSING_ELSE
813	1	1
821	1	1
826	1	1
827	1	1
830	1	1
834	1	1
838	1	1
842	1	1
846	1	1
868	1	1
872	1	1
874	1	1
875	1	1
877	1	1
880	1	1
902	2	2
903	2	2
904	2	2
			MISSING_ELSE
909	2	2
910	2	2
911	2	2
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut

	Total	Covered	Percent
Conditions	170	145	85.29
Logical	170	145	85.29
Non-Logical	0	0
Event	0	0

 LINE       240
 EXPRESSION (digest_size == SHA2_256)
            ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       244
 EXPRESSION ((digest_size == SHA2_384) || (digest_size == SHA2_512))
             ------------1------------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T7
1	0	Covered	T1,T2,T3

 LINE       244
 SUB-EXPRESSION (digest_size == SHA2_384)
                ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       244
 SUB-EXPRESSION (digest_size == SHA2_512)
                ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T7

 LINE       246
 EXPRESSION (reg2hw.digest[(2 * i)].qe ? prim_sha2_pkg::conv_endian32(reg2hw.digest[(2 * i)].q, digest_swap) : digest[i][63:32])
             ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       249
 EXPRESSION (reg2hw.digest[((2 * i) + 1)].qe ? prim_sha2_pkg::conv_endian32(reg2hw.digest[((2 * i) + 1)].q, digest_swap) : digest[i][31:0])
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       252
 EXPRESSION (reg2hw.digest[(2 * i)].qe | reg2hw.digest[((2 * i) + 1)].qe)
             ------------1------------   ---------------2---------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Not Covered

 LINE       256
 EXPRESSION (digest_size_started_q == SHA2_256)
            -----------------1-----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       262
 EXPRESSION ((digest_size_started_q == SHA2_384) || (digest_size_started_q == SHA2_512))
             -----------------1-----------------    -----------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3

 LINE       262
 SUB-EXPRESSION (digest_size_started_q == SHA2_384)
                -----------------1-----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       262
 SUB-EXPRESSION (digest_size_started_q == SHA2_512)
                -----------------1-----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       299
 EXPRESSION (hash_start_or_continue ? digest_size : digest_size_started_q)
             -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       333
 EXPRESSION (reg2hw.cmd.hash_start.qe & reg2hw.cmd.hash_start.q)
             ------------1-----------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       334
 EXPRESSION (reg2hw.cmd.hash_stop.qe & reg2hw.cmd.hash_stop.q)
             -----------1-----------   -----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       335
 EXPRESSION (reg2hw.cmd.hash_continue.qe & reg2hw.cmd.hash_continue.q)
             -------------1-------------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       336
 EXPRESSION (reg2hw.cmd.hash_process.qe & reg2hw.cmd.hash_process.q)
             -------------1------------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       345
 EXPRESSION (reg_hash_start & sha_en & ((~cfg_block)) & ((~invalid_config)))
             -------1------   ---2--   -------3------   ---------4---------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Covered	T1,T2,T3
1	0	1	1	Covered	T2,T3,T7
1	1	0	1	Covered	T2,T3,T15
1	1	1	0	Covered	T1,T2,T3
1	1	1	1	Covered	T1,T2,T3

 LINE       346
 EXPRESSION (reg_hash_continue & sha_en & ((~cfg_block)) & ((~invalid_config)))
             --------1--------   ---2--   -------3------   ---------4---------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Covered	T1,T2,T3
1	0	1	1	Not Covered
1	1	0	1	Not Covered
1	1	1	0	Not Covered
1	1	1	1	Not Covered

 LINE       347
 EXPRESSION (reg_hash_process & sha_en & cfg_block & ((~invalid_config)))
             --------1-------   ---2--   ----3----   ---------4---------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Covered	T1,T2,T3
1	0	1	1	Not Covered
1	1	0	1	Not Covered
1	1	1	0	Not Covered
1	1	1	1	Covered	T1,T2,T3

 LINE       348
 EXPRESSION (hash_start | hash_continue)
             -----1----   ------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T2,T3

 LINE       355
 EXPRESSION (reg_hash_done || reg_hash_stop)
             ------1------    ------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T2,T3

 LINE       393
 EXPRESSION (((!cfg_block)) && reg2hw.cfg.hmac_en.qe)
             -------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T16
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       449
 EXPRESSION (fifo_empty_q & ((~fifo_empty)))
             ------1-----   -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       456
 EXPRESSION 
 Number  Term
      1  fifo_full ? 1'b1 : (fifo_empty_negedge ? 1'b0 : ((reg_hash_start || reg_hash_continue || reg_hash_process || reg_hash_stop) ? 1'b0 : fifo_full_seen_q)))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       456
 SUB-EXPRESSION (fifo_empty_negedge ? 1'b0 : ((reg_hash_start || reg_hash_continue || reg_hash_process || reg_hash_stop) ? 1'b0 : fifo_full_seen_q))
                 ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       456
 SUB-EXPRESSION ((reg_hash_start || reg_hash_continue || reg_hash_process || reg_hash_stop) ? 1'b0 : fifo_full_seen_q)
                 -------------------------------------1------------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       456
 SUB-EXPRESSION (reg_hash_start || reg_hash_continue || reg_hash_process || reg_hash_stop)
                 -------1------    --------2--------    --------3-------    ------4------

-1-	-2-	-3-	-4-	Status	Tests
0	0	0	0	Covered	T1,T2,T3
0	0	0	1	Not Covered
0	0	1	0	Covered	T1,T2,T3
0	1	0	0	Not Covered
1	0	0	0	Covered	T1,T2,T3

 LINE       464
 EXPRESSION (((~msg_allowed)) || ((~fifo_full_seen_q)))
             --------1-------    ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T14,T17,T18
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       466
 EXPRESSION (fifo_empty_gate ? 1'b0 : fifo_empty)
             -------1-------

-1-	Status	Tests
0	Covered	T14,T17,T18
1	Covered	T1,T2,T3

 LINE       510
 EXPRESSION (msg_fifo_req & ((~msg_fifo_we)))
             ------1-----   --------2-------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Excluded		VC_COV_UNR

 LINE       513
 EXPRESSION (msg_fifo_req & ((~hmac_fifo_wsel)) & packer_ready)
             ------1-----   ---------2---------   ------3-----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Unreachable	T14,T17,T19
1	1	1	Covered	T1,T2,T3

 LINE       529
 EXPRESSION ((hmac_fifo_wsel && fifo_wready) ? hmac_fifo_wvalid : reg_fifo_wvalid)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       529
 SUB-EXPRESSION (hmac_fifo_wsel && fifo_wready)
                 -------1------    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       535
 EXPRESSION (digest_size == SHA2_256)
            ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       538
 EXPRESSION ((digest_size == SHA2_384) || (digest_size == SHA2_512))
             ------------1------------    ------------2------------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3

 LINE       538
 SUB-EXPRESSION (digest_size == SHA2_384)
                ------------1------------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T1,T2,T3

 LINE       538
 SUB-EXPRESSION (digest_size == SHA2_512)
                ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       554
 EXPRESSION (fifo_wvalid & sha_en)
             -----1-----   ---2--

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T2,T3
1	0	Excluded		VC_COV_UNR
1	1	Covered	T1,T2,T3

 LINE       607
 EXPRESSION (msg_fifo_req & msg_fifo_we & ((~hmac_fifo_wsel)) & msg_allowed)
             ------1-----   -----2-----   ---------3---------   -----4-----

-1-	-2-	-3-	-4-	Status	Tests	Exclude Annotation
0	1	1	1	Covered	T1,T2,T3
1	0	1	1	Excluded		VC_COV_UNR
1	1	0	1	Excluded		VC_COV_UNR
1	1	1	0	Covered	T1,T2,T3
1	1	1	1	Covered	T1,T2,T3

 LINE       637
 EXPRESSION (msg_write && sha_en && packer_ready)
             ----1----    ---2--    ------3-----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Unreachable	T14,T17,T19
1	1	1	Covered	T1,T2,T3

 LINE       657
 EXPRESSION (msg_write & sha_en)
             ----1----   ---2--

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T2,T3
1	0	Excluded		VC_COV_UNR
1	1	Covered	T1,T2,T3

 LINE       657
 EXPRESSION (fifo_wready & ((~hmac_fifo_wsel)))
             -----1-----   ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       761
 SUB-EXPRESSION (reg2hw.alert_test.q & reg2hw.alert_test.qe)
                 ---------1---------   ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T20,T21,T22
1	0	Covered	T1,T2,T3
1	1	Covered	T23,T20,T21

 LINE       790
 EXPRESSION ((reg_hash_start | reg_hash_continue) & ((~sha_en)))
             ------------------1-----------------   -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T7

 LINE       790
 SUB-EXPRESSION (reg_hash_start | reg_hash_continue)
                 -------1------   --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T2,T3

 LINE       791
 EXPRESSION ((reg_hash_start | reg_hash_continue) & cfg_block)
             ------------------1-----------------   ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T15

 LINE       791
 SUB-EXPRESSION (reg_hash_start | reg_hash_continue)
                 -------1------   --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T2,T3

 LINE       792
 EXPRESSION (msg_fifo_req & ((~msg_allowed)))
             ------1-----   --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       797
 EXPRESSION ((digest_size == SHA2_None) | ((key_length == Key_None) && hmac_en) | ((key_length == Key_1024) && (digest_size == SHA2_256) && hmac_en))
             -------------1------------   ------------------2------------------   ---------------------------------3--------------------------------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T5
0	1	0	Covered	T1,T2,T3
1	0	0	Covered	T1,T2,T3

 LINE       797
 SUB-EXPRESSION (digest_size == SHA2_None)
                -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       797
 SUB-EXPRESSION ((key_length == Key_None) && hmac_en)
                 ------------1-----------    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       797
 SUB-EXPRESSION (key_length == Key_None)
                ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       797
 SUB-EXPRESSION ((key_length == Key_1024) && (digest_size == SHA2_256) && hmac_en)
                 ------------1-----------    ------------2------------    ---3---

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T2,T3,T14
1	1	1	Covered	T2,T3,T5

 LINE       797
 SUB-EXPRESSION (key_length == Key_1024)
                ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       797
 SUB-EXPRESSION (digest_size == SHA2_256)
                ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       802
 EXPRESSION ((reg_hash_start || reg_hash_continue) & invalid_config)
             ------------------1------------------   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       802
 SUB-EXPRESSION (reg_hash_start || reg_hash_continue)
                 -------1------    --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T2,T3

 LINE       821
 EXPRESSION 
 Number  Term
      1  ((~reg2hw.intr_state.hmac_err.q)) & 
      2  (hash_start_sha_disabled | update_seckey_inprocess | hash_start_active | msg_push_not_allowed | invalid_config_atstart))

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       821
 SUB-EXPRESSION (hash_start_sha_disabled | update_seckey_inprocess | hash_start_active | msg_push_not_allowed | invalid_config_atstart)
                 -----------1-----------   -----------2-----------   --------3--------   ----------4---------   -----------5----------

-1-	-2-	-3-	-4-	-5-	Status	Tests
0	0	0	0	0	Covered	T1,T2,T3
0	0	0	0	1	Covered	T1,T2,T3
0	0	0	1	0	Covered	T1,T2,T3
0	0	1	0	0	Covered	T2,T3,T15
0	1	0	0	0	Covered	T2,T3,T16
1	0	0	0	0	Covered	T2,T3,T7

 LINE       868
 EXPRESSION (((!reg_fifo_wvalid)) && ((!fifo_rvalid)) && hmac_core_idle && sha_core_idle)
             ----------1---------    --------2-------    -------3------    ------4------

-1-	-2-	-3-	-4-	Status	Tests	Exclude Annotation
0	1	1	1	Excluded		VC_COV_UNR
1	0	1	1	Not Covered
1	1	0	1	Covered	T1,T2,T3
1	1	1	0	Covered	T1,T2,T3
1	1	1	1	Covered	T1,T2,T3

---

Toggle Coverage for Instance : tb.dut

	Total	Covered	Percent
Totals	30	30	100.00
Total Bits	346	346	100.00
Total Bits 0->1	173	173	100.00
Total Bits 1->0	173	173	100.00

Ports	30	30	100.00
Port Bits	346	346	100.00
Port Bits 0->1	173	173	100.00
Port Bits 1->0	173	173	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T3,T14,T24	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T3,T16,T7	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T16,T7	Yes	T1,T16,T7	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_error	Yes	Yes	T24,T13,T25	Yes	T24,T13,T25	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T23,T20,T21	Yes	T23,T20,T21	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T23,T20,T21	Yes	T23,T20,T21	OUTPUT
intr_hmac_done_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
intr_fifo_empty_o	Yes	Yes	T3,T18,T24	Yes	T3,T18,T24	OUTPUT
intr_hmac_err_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
idle_o[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT

*Tests covering at least one bit in the range

---

FSM Coverage for Instance : tb.dut

Summary for FSM :: done_state_q

	Total	Covered	Percent
States	4	2	50.00	(Not included in score)
Transitions	5	2	40.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: done_state_q

---

states	Line No.	Covered	Tests
DoneAwaitCmd	167	Covered	T1,T2,T3
DoneAwaitHashComplete	176	Not Covered
DoneAwaitHashDone	157	Covered	T1,T2,T3
DoneAwaitMessageComplete	160	Not Covered

transitions	Line No.	Covered	Tests
DoneAwaitCmd->DoneAwaitHashDone	157	Covered	T1,T2,T3
DoneAwaitCmd->DoneAwaitMessageComplete	160	Not Covered
DoneAwaitHashComplete->DoneAwaitCmd	183	Not Covered
DoneAwaitHashDone->DoneAwaitCmd	167	Covered	T1,T2,T3
DoneAwaitMessageComplete->DoneAwaitHashComplete	176	Not Covered

---

Branch Coverage for Instance : tb.dut

	Line No.	Total	Covered	Percent
Branches		93	82	88.17
TERNARY	299	2	2	100.00
TERNARY	456	4	4	100.00
TERNARY	466	2	2	100.00
TERNARY	529	2	2	100.00
CASE	153	10	4	40.00
IF	192	2	2	100.00
IF	205	3	3	100.00
IF	219	2	2	100.00
IF	240	6	4	66.67
IF	256	3	3	100.00
CASE	287	4	4	100.00
IF	302	2	2	100.00
CASE	308	6	6	100.00
IF	351	4	4	100.00
IF	361	3	3	100.00
IF	400	4	4	100.00
IF	469	2	2	100.00
IF	533	4	3	75.00
IF	620	2	2	100.00
IF	626	5	3	60.00
IF	635	3	3	100.00
IF	806	2	2	100.00
CASE	827	6	6	100.00
IF	874	2	2	100.00
IF	902	4	4	100.00
IF	909	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_hmac_0.1/rtl/hmac.sv' or '../src/lowrisc_ip_hmac_0.1/rtl/hmac.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	299	(hash_start_or_continue) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	456	(fifo_full) ? 
-2-:	456	(fifo_empty_negedge) ? 
-3-:	456	((((reg_hash_start || reg_hash_continue) || reg_hash_process) || reg_hash_stop)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	466	(fifo_empty_gate) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T14,T17,T18

	LineNo.	Expression
-1-:	529	((hmac_fifo_wsel && fifo_wready)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	153	case (done_state_q)
-2-:	155	if (sha_hash_process)
-3-:	158	if (reg_hash_stop)
-4-:	165	if (reg_hash_done)
-5-:	172	if (digest_on_blk)
-6-:	181	if ((!hash_running))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	Status	Tests
DoneAwaitCmd	1	-	-	-	-	Covered	T1,T2,T3
DoneAwaitCmd	0	1	-	-	-	Not Covered
DoneAwaitCmd	0	0	-	-	-	Covered	T1,T2,T3
DoneAwaitHashDone	-	-	1	-	-	Covered	T1,T2,T3
DoneAwaitHashDone	-	-	0	-	-	Covered	T1,T2,T3
DoneAwaitMessageComplete	-	-	-	1	-	Not Covered
DoneAwaitMessageComplete	-	-	-	0	-	Not Covered
DoneAwaitHashComplete	-	-	-	-	1	Not Covered
DoneAwaitHashComplete	-	-	-	-	0	Not Covered
default	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	192	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	205	if (wipe_secret)
-2-:	207	if ((!cfg_block))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T3,T26,T27
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	240	if ((digest_size == SHA2_256))
-2-:	244	if (((digest_size == SHA2_384) || (digest_size == SHA2_512)))
-3-:	246	(reg2hw.digest[(2 * i)].qe) ? 
-4-:	249	(reg2hw.digest[((2 * i) + 1)].qe) ? 

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	1	-	Not Covered
0	1	0	-	Covered	T1,T2,T3
0	1	-	1	Not Covered
0	1	-	0	Covered	T1,T2,T3
0	0	-	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	256	if ((digest_size_started_q == SHA2_256))
-2-:	262	if (((digest_size_started_q == SHA2_384) || (digest_size_started_q == SHA2_512)))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	287	case (digest_size_supplied)

Branches:

-1-	Status	Tests
SHA2_256	Covered	T1,T2,T3
SHA2_384	Covered	T1,T2,T3
SHA2_512	Covered	T2,T3,T7
default	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	302	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	308	case (key_length_supplied)

Branches:

-1-	Status	Tests
Key_128	Covered	T1,T2,T3
Key_256	Covered	T1,T2,T3
Key_384	Covered	T2,T3,T7
Key_512	Covered	T1,T2,T3
Key_1024	Covered	T1,T2,T3
default	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	351	if ((!rst_ni))
-2-:	353	if (hash_start_or_continue)
-3-:	355	if ((reg_hash_done || reg_hash_stop))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	361	if ((!rst_ni))
-2-:	393	if (((!cfg_block) && reg2hw.cfg.hmac_en.qe))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	400	if ((!rst_ni))
-2-:	402	if (hash_start_or_continue)
-3-:	404	if (packer_flush_done)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	469	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	533	if (hmac_fifo_wsel)
-2-:	535	if ((digest_size == SHA2_256))
-3-:	538	if (((digest_size == SHA2_384) || (digest_size == SHA2_512)))

Branches:

-1-	-2-	-3-	Status	Tests
1	1	-	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	0	0	Not Covered
0	-	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	620	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	626	if ((!cfg_block))
-2-:	627	if (reg2hw.msg_length_lower.qe)
-3-:	630	if (reg2hw.msg_length_upper.qe)

Branches:

-1-	-2-	-3-	Status	Tests
1	1	-	Not Covered
1	0	-	Covered	T1,T2,T3
1	-	1	Not Covered
1	-	0	Covered	T1,T2,T3
0	-	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	635	if (hash_start)
-2-:	637	if (((msg_write && sha_en) && packer_ready))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	806	if (cfg_block)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	827	case (1'b1)

Branches:

-1-	Status	Tests
invalid_config_atstart	Covered	T1,T2,T3
hash_start_sha_disabled	Covered	T2,T3,T7
hash_start_active	Covered	T2,T3,T15
msg_push_not_allowed	Covered	T1,T2,T3
update_seckey_inprocess	Covered	T2,T3,T16
default	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	874	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	902	if ((!rst_ni))
-2-:	903	if (hash_process)
-3-:	904	if (reg_hash_done)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	909	if ((!rst_ni))
-2-:	910	if (hash_start_or_continue)
-3-:	911	if (hash_process)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertKnownO_A	389368484	389301884	0	0
FpvSecCmRegWeOnehotCheck_A	389368484	90	0	0
IntrFifoEmptyOKnown	389368484	389301884	0	0
IntrHmacDoneOKnown	389368484	389301884	0	0
TlOAReadyKnown	389368484	389301884	0	0
TlODValidKnown	389368484	389301884	0	0
ValidHashProcessAssert	389368484	35343	0	0
ValidHmacEnConditionAssert	389368484	9633	0	0
ValidWriteAssert	389368484	23150667	0	0
gen_assert_wmask_bytealign[0].unnamed$$_0	389368484	23150667	0	0
gen_assert_wmask_bytealign[1].unnamed$$_0	389368484	23150667	0	0
gen_assert_wmask_bytealign[2].unnamed$$_0	389368484	23150667	0	0
gen_assert_wmask_bytealign[3].unnamed$$_0	389368484	23150667	0	0

AlertKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389368484	389301884	0	0
T1	48200	48121	0	0
T2	202607	202537	0	0
T3	560284	560201	0	0
T4	489458	489389	0	0
T5	236355	236285	0	0
T6	90959	90861	0	0
T7	309839	309763	0	0
T14	66000	65868	0	0
T16	7299	7200	0	0
T23	767	675	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389368484	90	0	0
T28	3177	10	0	0
T29	0	10	0	0
T30	0	10	0	0
T31	0	30	0	0
T32	0	30	0	0
T33	17314	0	0	0
T34	182748	0	0	0
T35	868355	0	0	0
T36	63976	0	0	0
T37	284434	0	0	0
T38	789880	0	0	0
T39	9538	0	0	0
T40	12648	0	0	0
T41	509952	0	0	0

IntrFifoEmptyOKnown

Name	Attempts	Real Successes	Failures	Incomplete
Total	389368484	389301884	0	0
T1	48200	48121	0	0
T2	202607	202537	0	0
T3	560284	560201	0	0
T4	489458	489389	0	0
T5	236355	236285	0	0
T6	90959	90861	0	0
T7	309839	309763	0	0
T14	66000	65868	0	0
T16	7299	7200	0	0
T23	767	675	0	0

IntrHmacDoneOKnown

Name	Attempts	Real Successes	Failures	Incomplete
Total	389368484	389301884	0	0
T1	48200	48121	0	0
T2	202607	202537	0	0
T3	560284	560201	0	0
T4	489458	489389	0	0
T5	236355	236285	0	0
T6	90959	90861	0	0
T7	309839	309763	0	0
T14	66000	65868	0	0
T16	7299	7200	0	0
T23	767	675	0	0

TlOAReadyKnown

Name	Attempts	Real Successes	Failures	Incomplete
Total	389368484	389301884	0	0
T1	48200	48121	0	0
T2	202607	202537	0	0
T3	560284	560201	0	0
T4	489458	489389	0	0
T5	236355	236285	0	0
T6	90959	90861	0	0
T7	309839	309763	0	0
T14	66000	65868	0	0
T16	7299	7200	0	0
T23	767	675	0	0

TlODValidKnown

Name	Attempts	Real Successes	Failures	Incomplete
Total	389368484	389301884	0	0
T1	48200	48121	0	0
T2	202607	202537	0	0
T3	560284	560201	0	0
T4	489458	489389	0	0
T5	236355	236285	0	0
T6	90959	90861	0	0
T7	309839	309763	0	0
T14	66000	65868	0	0
T16	7299	7200	0	0
T23	767	675	0	0

ValidHashProcessAssert

Name	Attempts	Real Successes	Failures	Incomplete
Total	389368484	35343	0	0
T1	48200	7	0	0
T2	202607	10	0	0
T3	560284	407	0	0
T4	489458	21	0	0
T5	236355	15	0	0
T6	90959	7	0	0
T7	309839	1	0	0
T14	66000	23	0	0
T16	7299	4	0	0
T23	767	0	0	0
T42	0	34	0	0

ValidHmacEnConditionAssert

Name	Attempts	Real Successes	Failures	Incomplete
Total	389368484	9633	0	0
T1	48200	7	0	0
T2	202607	34	0	0
T3	560284	149	0	0
T4	489458	17	0	0
T5	236355	1	0	0
T6	90959	1	0	0
T7	309839	13	0	0
T14	66000	11	0	0
T16	7299	1	0	0
T23	767	0	0	0
T42	0	24	0	0

ValidWriteAssert

Name	Attempts	Real Successes	Failures	Incomplete
Total	389368484	23150667	0	0
T1	48200	8952	0	0
T2	202607	20356	0	0
T3	560284	276882	0	0
T4	489458	17712	0	0
T5	236355	44892	0	0
T6	90959	16926	0	0
T7	309839	9927	0	0
T14	66000	31724	0	0
T16	7299	51	0	0
T23	767	0	0	0
T42	0	584	0	0

gen_assert_wmask_bytealign[0].unnamed$$_0

Name	Attempts	Real Successes	Failures	Incomplete
Total	389368484	23150667	0	0
T1	48200	8952	0	0
T2	202607	20356	0	0
T3	560284	276882	0	0
T4	489458	17712	0	0
T5	236355	44892	0	0
T6	90959	16926	0	0
T7	309839	9927	0	0
T14	66000	31724	0	0
T16	7299	51	0	0
T23	767	0	0	0
T42	0	584	0	0

gen_assert_wmask_bytealign[1].unnamed$$_0

Name	Attempts	Real Successes	Failures	Incomplete
Total	389368484	23150667	0	0
T1	48200	8952	0	0
T2	202607	20356	0	0
T3	560284	276882	0	0
T4	489458	17712	0	0
T5	236355	44892	0	0
T6	90959	16926	0	0
T7	309839	9927	0	0
T14	66000	31724	0	0
T16	7299	51	0	0
T23	767	0	0	0
T42	0	584	0	0

gen_assert_wmask_bytealign[2].unnamed$$_0

Name	Attempts	Real Successes	Failures	Incomplete
Total	389368484	23150667	0	0
T1	48200	8952	0	0
T2	202607	20356	0	0
T3	560284	276882	0	0
T4	489458	17712	0	0
T5	236355	44892	0	0
T6	90959	16926	0	0
T7	309839	9927	0	0
T14	66000	31724	0	0
T16	7299	51	0	0
T23	767	0	0	0
T42	0	584	0	0

gen_assert_wmask_bytealign[3].unnamed$$_0

Name	Attempts	Real Successes	Failures	Incomplete
Total	389368484	23150667	0	0
T1	48200	8952	0	0
T2	202607	20356	0	0
T3	560284	276882	0	0
T4	489458	17712	0	0
T5	236355	44892	0	0
T6	90959	16926	0	0
T7	309839	9927	0	0
T14	66000	31724	0	0
T16	7299	51	0	0
T23	767	0	0	0
T42	0	584	0	0