Unified Coverage Report :: Module :: hmac_csr_assert_fpv

Module : hmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_hmac_csr_assert_0/hmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.hmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.hmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
84.88	95.83	85.29	100.00	40.00	88.17	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : hmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	400796218	2214639	0	0
intr_enable_rd_A	400796218	3134	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400796218	2214639	0	0
T8	0	20344	0	0
T9	0	39253	0	0
T10	0	232021	0	0
T11	0	265942	0	0
T12	0	82891	0	0
T13	0	122461	0	0
T19	90339	0	0	0
T24	154733	63326	0	0
T25	0	178961	0	0
T60	0	191867	0	0
T61	0	420725	0	0
T62	171747	0	0	0
T63	351686	0	0	0
T64	12876	0	0	0
T65	5852	0	0	0
T66	280667	0	0	0
T67	389873	0	0	0
T68	648267	0	0	0
T69	2393	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400796218	3134	0	0
T29	3193	0	0	0
T40	12648	44	0	0
T41	509952	0	0	0
T57	0	33	0	0
T58	0	5	0	0
T70	0	82	0	0
T71	0	34	0	0
T72	0	69	0	0
T73	0	23	0	0
T74	0	83	0	0
T75	0	24	0	0
T76	0	3	0	0
T77	83713	0	0	0
T78	212686	0	0	0
T79	773688	0	0	0
T80	1081	0	0	0
T81	1149	0	0	0
T82	669131	0	0	0
T83	196908	0	0	0