Unified Coverage Report :: Module :: prim_sha2

Module : prim_sha2

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.62	98.57	93.79		90.00	92.11

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_sha2_0/rtl/prim_sha2.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_prim_sha2_512.gen_multimode_logic.u_prim_sha2_multimode	93.62	98.57	93.79		90.00	92.11

---

Module Instance : tb.dut.u_prim_sha2_512.gen_multimode_logic.u_prim_sha2_multimode

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.62	98.57	93.79		90.00	92.11

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
87.34	95.54	90.97		76.00	86.84

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.33	100.00	94.37			97.62		u_prim_sha2_512

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_pad	82.15	92.25	88.11		66.67	81.58

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : prim_sha2

	Line No.	Total	Covered	Percent
TOTAL		140	138	98.57
CONT_ASSIGN	77	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
ALWAYS	91	14	14	100.00
ALWAYS	116	4	4	100.00
ALWAYS	122	10	10	100.00
ALWAYS	139	3	3	100.00
ALWAYS	145	19	19	100.00
ALWAYS	173	3	3	100.00
CONT_ASSIGN	178	1	1	100.00
ALWAYS	270	7	7	100.00
ALWAYS	287	3	3	100.00
CONT_ASSIGN	292	1	1	100.00
ALWAYS	297	3	3	100.00
CONT_ASSIGN	302	1	1	100.00
ALWAYS	305	3	3	100.00
ALWAYS	318	3	3	100.00
ALWAYS	323	26	26	100.00
ALWAYS	374	3	3	100.00
ALWAYS	388	3	3	100.00
ALWAYS	395	3	3	100.00
CONT_ASSIGN	399	1	1	100.00
ALWAYS	402	23	21	91.30
CONT_ASSIGN	452	1	1	100.00
CONT_ASSIGN	456	1	1	100.00
CONT_ASSIGN	483	1	1	100.00
CONT_ASSIGN	486	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_sha2_0/rtl/prim_sha2.sv' or '../src/lowrisc_prim_sha2_0/rtl/prim_sha2.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
77	1	1
79	1	1
91	1	1
92	1	1
93	1	1
94	1	1
95	1	1
96	1	1
99	1	1
100	1	1
101	1	1
103	1	1
105	1	1
106	1	1
			==> MISSING_ELSE
108	1	1
110	1	1
			MISSING_ELSE
116	2	2
117	2	2
			==> MISSING_ELSE
122	1	1
123	1	1
124	1	1
125	1	1
126	1	1
127	1	1
128	1	1
129	1	1
131	1	1
132	1	1
			==> MISSING_ELSE
			MISSING_ELSE
139	2	2
140	1	1
145	1	1
146	1	1
147	1	1
148	1	1
149	1	1
150	1	1
151	1	1
152	1	1
153	1	1
154	1	1
155	1	1
			==> MISSING_ELSE
158	1	1
159	1	1
160	1	1
161	1	1
162	1	1
164	1	1
165	1	1
166	1	1
			MISSING_ELSE
173	2	2
174	1	1
178	1	1
270	1	1
271	1	1
272	1	1
273	1	1
274	1	1
278	1	1
280	1	1
			MISSING_ELSE
287	2	2
288	1	1
292	1	1
297	2	2
298	1	1
302	1	1
305	2	2
306	1	1
318	2	2
319	1	1
323	1	1
324	1	1
325	1	1
327	1	1
329	2	2
330	1	1
334	1	1
336	1	1
337	1	1
338	1	1
339	1	1
341	1	1
343	1	1
344	1	1
349	1	1
350	1	1
352	1	1
353	1	1
354	1	1
356	1	1
365	1	1
366	1	1
367	1	1
368	1	1
369	1	1
			MISSING_ELSE
374	2	2
375	1	1
388	2	2
389	1	1
395	2	2
396	1	1
399	1	1
402	1	1
403	1	1
404	1	1
405	1	1
406	1	1
408	1	1
410	1	1
411	1	1
412	1	1
414	1	1
419	1	1
420	1	1
423	1	1
424	1	1
425	1	1
427	1	1
432	1	1
433	1	1
434	0	1
435	0	1
437	1	1
446	2	2
			MISSING_ELSE
452	1	1
456	1	1
483	1	1
486	1	1

---

Cond Coverage for Module : prim_sha2

	Total	Covered	Percent
Conditions	145	136	93.79
Logical	145	136	93.79
Non-Logical	0	0
Event	0	0

 LINE       77
 EXPRESSION (hash_start_i | hash_continue_i)
             ------1-----   -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T2,T3

 LINE       79
 EXPRESSION (hash_go ? digest_mode_i : (hash_done_o ? SHA2_None : digest_mode_flag_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       79
 SUB-EXPRESSION (hash_done_o ? SHA2_None : digest_mode_flag_q)
                 -----1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       94
 EXPRESSION (((!sha_en_i)) || hash_go)
             ------1------    ---2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       96
 EXPRESSION (((!run_hash)) && update_w_from_fifo)
             ------1------    ---------2--------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (digest_mode_flag_q == SHA2_256)
            ----------------1---------------

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T1,T2,T3

 LINE       105
 EXPRESSION ((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512))
             ----------------1---------------    ----------------2---------------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Covered	T2,T4,T5
1	0	Covered	T2,T5,T6

 LINE       105
 SUB-EXPRESSION (digest_mode_flag_q == SHA2_384)
                ----------------1---------------

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T2,T5,T6

 LINE       105
 SUB-EXPRESSION (digest_mode_flag_q == SHA2_512)
                ----------------1---------------

-1-	Status	Tests
0	Covered	T2,T5,T6
1	Covered	T2,T4,T5

 LINE       128
 EXPRESSION (digest_mode_flag_q == SHA2_256)
            ----------------1---------------

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T1,T2,T3

 LINE       131
 EXPRESSION ((digest_mode_flag_q == SHA2_512) || (digest_mode_flag_q == SHA2_384))
             ----------------1---------------    ----------------2---------------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Covered	T2,T5,T6
1	0	Covered	T2,T4,T5

 LINE       131
 SUB-EXPRESSION (digest_mode_flag_q == SHA2_512)
                ----------------1---------------

-1-	Status	Tests
0	Covered	T2,T5,T6
1	Covered	T2,T4,T5

 LINE       131
 SUB-EXPRESSION (digest_mode_flag_q == SHA2_384)
                ----------------1---------------

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T2,T5,T6

 LINE       150
 EXPRESSION (digest_mode_i == SHA2_256)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T1,T2,T3

 LINE       152
 EXPRESSION (digest_mode_i == SHA2_384)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T2,T5,T6

 LINE       154
 EXPRESSION (digest_mode_i == SHA2_512)
            -------------1-------------

-1-	Status	Tests
0	Not Covered
1	Covered	T2,T4,T5

 LINE       162
 EXPRESSION (digest_we_i[i] ? digest_i[i] : gen_multimode.digest_q[i])
             -------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       271
 EXPRESSION (((!sha_en_i)) || hash_go)
             ------1------    ---2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       292
 EXPRESSION ((((~sha_en_i)) || hash_go) ? '0 : (update_w_from_fifo ? ((w_index_q + 1)) : w_index_q))
             -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       292
 SUB-EXPRESSION (((~sha_en_i)) || hash_go)
                 ------1------    ---2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       292
 SUB-EXPRESSION (update_w_from_fifo ? ((w_index_q + 1)) : w_index_q)
                 ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       338
 EXPRESSION (w_index_q == 4'd15)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       349
 EXPRESSION (msg_feed_complete && one_chunk_done)
             --------1--------    -------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       399
 EXPRESSION (hash_start_i | (((~sha_en_i)) & sha_en_q))
             ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T45,T15,T16
1	0	Covered	T1,T2,T3

 LINE       399
 SUB-EXPRESSION (((~sha_en_i)) & sha_en_q)
                 ------1------   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T45,T15,T16

 LINE       410
 EXPRESSION (fifo_st_q == FifoWait)
            -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       420
 EXPRESSION 
 Number  Term
      1  (((digest_mode_flag_q == SHA2_256) || ((~MultimodeEn))) && (round_q < 7'h30)) || 
      2  (((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512)) && (round_q < 7'h40)))

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T4,T5
1	0	Covered	T1,T2,T3

 LINE       420
 SUB-EXPRESSION (((digest_mode_flag_q == SHA2_256) || ((~MultimodeEn))) && (round_q < 7'h30))
                 ---------------------------1--------------------------    --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       420
 SUB-EXPRESSION ((digest_mode_flag_q == SHA2_256) || ((~MultimodeEn)))
                 ----------------1---------------    --------2-------

-1-	-2-	Status	Tests
0	-	Covered	T2,T4,T5
1	-	Covered	T1,T2,T3

 LINE       420
 SUB-EXPRESSION (digest_mode_flag_q == SHA2_256)
                ----------------1---------------

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T1,T2,T3

 LINE       420
 SUB-EXPRESSION (((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512)) && (round_q < 7'h40))
                 -----------------------------------1----------------------------------    --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T5
1	1	Covered	T2,T4,T5

 LINE       420
 SUB-EXPRESSION ((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512))
                 ----------------1---------------    ----------------2---------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T4,T5
1	0	Covered	T2,T5,T6

 LINE       420
 SUB-EXPRESSION (digest_mode_flag_q == SHA2_384)
                ----------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T5,T6

 LINE       420
 SUB-EXPRESSION (digest_mode_flag_q == SHA2_512)
                ----------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T5

 LINE       433
 EXPRESSION (fifo_st_q == FifoWait)
            -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       446
 EXPRESSION (((!sha_en_i)) || hash_go)
             ------1------    ---2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       452
 EXPRESSION 
 Number  Term
      1  update_digest && 
      2  (fifo_st_q == FifoIdle) && 
      3  (((digest_mode_flag_q == SHA2_256) && (message_length_i[8:0] == '0)) || ((digest_mode_flag_q inside {SHA2_384, SHA2_512}) && (message_length_i[9:0] == '0))))

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T2,T3,T5
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T2,T3,T5

 LINE       452
 SUB-EXPRESSION (fifo_st_q == FifoIdle)
                -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       452
 SUB-EXPRESSION 
 Number  Term
      1  ((digest_mode_flag_q == SHA2_256) && (message_length_i[8:0] == '0)) || 
      2  ((digest_mode_flag_q inside {SHA2_384, SHA2_512}) && (message_length_i[9:0] == '0)))

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T4,T5
1	0	Covered	T1,T2,T3

 LINE       452
 SUB-EXPRESSION ((digest_mode_flag_q == SHA2_256) && (message_length_i[8:0] == '0))
                 ----------------1---------------    --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       452
 SUB-EXPRESSION (digest_mode_flag_q == SHA2_256)
                ----------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       452
 SUB-EXPRESSION (message_length_i[8:0] == '0)
                --------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       452
 SUB-EXPRESSION ((digest_mode_flag_q inside {SHA2_384, SHA2_512}) && (message_length_i[9:0] == '0))
                 ------------------------1-----------------------    --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T5
1	1	Covered	T2,T4,T5

 LINE       452
 SUB-EXPRESSION (message_length_i[9:0] == '0)
                --------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       456
 EXPRESSION 
 Number  Term
      1  (((digest_mode_flag_q == SHA2_256) || ((~MultimodeEn))) && (round_q == 7'd63)) ? 1'b1 : ((((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512)) && (round_q == 7'd79)) ? 1'b1 : 1'b0))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       456
 SUB-EXPRESSION (((digest_mode_flag_q == SHA2_256) || ((~MultimodeEn))) && (round_q == 7'd63))
                 ---------------------------1--------------------------    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       456
 SUB-EXPRESSION ((digest_mode_flag_q == SHA2_256) || ((~MultimodeEn)))
                 ----------------1---------------    --------2-------

-1-	-2-	Status	Tests
0	-	Covered	T1,T2,T3
1	-	Covered	T1,T2,T3

 LINE       456
 SUB-EXPRESSION (digest_mode_flag_q == SHA2_256)
                ----------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       456
 SUB-EXPRESSION (round_q == 7'd63)
                ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       456
 SUB-EXPRESSION ((((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512)) && (round_q == 7'd79)) ? 1'b1 : 1'b0)
                 -----------------------------------------------1----------------------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T5

 LINE       456
 SUB-EXPRESSION (((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512)) && (round_q == 7'd79))
                 -----------------------------------1----------------------------------    ---------2--------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T4,T5
1	1	Covered	T2,T4,T5

 LINE       456
 SUB-EXPRESSION ((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512))
                 ----------------1---------------    ----------------2---------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T4,T5
1	0	Covered	T2,T5,T6

 LINE       456
 SUB-EXPRESSION (digest_mode_flag_q == SHA2_384)
                ----------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T5,T6

 LINE       456
 SUB-EXPRESSION (digest_mode_flag_q == SHA2_512)
                ----------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T5

 LINE       456
 SUB-EXPRESSION (round_q == 7'd79)
                ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T5

 LINE       483
 EXPRESSION (init_hash | run_hash | update_digest)
             ----1----   ----2---   ------3------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	1	0	Covered	T1,T2,T3
1	0	0	Covered	T1,T2,T3

 LINE       486
 EXPRESSION ((fifo_st_q == FifoIdle) && (sha_st_q == ShaIdle) && ((!hash_go)))
             -----------1-----------    ----------2----------    ------3-----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       486
 SUB-EXPRESSION (fifo_st_q == FifoIdle)
                -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       486
 SUB-EXPRESSION (sha_st_q == ShaIdle)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

FSM Coverage for Module : prim_sha2

Summary for FSM :: fifo_st_q

	Total	Covered	Percent
States	3	3	100.00	(Not included in score)
Transitions	5	5	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: fifo_st_q

---

states	Line No.	Covered	Tests
FifoIdle	323	Covered	T1,T2,T3
FifoLoadFromFifo	329	Covered	T1,T2,T3
FifoWait	339	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
FifoIdle->FifoLoadFromFifo	329	Covered	T1,T2,T3
FifoLoadFromFifo->FifoIdle	323	Covered	T13,T11,T12
FifoLoadFromFifo->FifoWait	339	Covered	T1,T2,T3
FifoWait->FifoIdle	323	Covered	T1,T2,T3
FifoWait->FifoLoadFromFifo	354	Covered	T1,T2,T3

Summary for FSM :: sha_st_q

	Total	Covered	Percent
States	3	3	100.00	(Not included in score)
Transitions	5	4	80.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: sha_st_q

---

states	Line No.	Covered	Tests
ShaCompress	412	Covered	T1,T2,T3
ShaIdle	414	Covered	T1,T2,T3
ShaUpdateDigest	425	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
ShaCompress->ShaIdle	446	Covered	T10,T13,T28
ShaCompress->ShaUpdateDigest	425	Covered	T1,T2,T3
ShaIdle->ShaCompress	412	Covered	T1,T2,T3
ShaUpdateDigest->ShaCompress	435	Not Covered
ShaUpdateDigest->ShaIdle	437	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_sha2

	Line No.	Total	Covered	Percent
Branches		76	70	92.11
TERNARY	79	3	3	100.00
TERNARY	292	3	3	100.00
TERNARY	456	3	3	100.00
IF	271	4	4	100.00
IF	287	2	2	100.00
IF	297	2	2	100.00
IF	305	2	2	100.00
IF	318	2	2	100.00
CASE	327	9	8	88.89
IF	365	3	3	100.00
IF	374	2	2	100.00
IF	388	2	2	100.00
IF	395	2	2	100.00
CASE	408	8	6	75.00
IF	446	2	2	100.00
IF	92	8	7	87.50
IF	116	3	2	66.67
IF	123	6	5	83.33
IF	139	2	2	100.00
IF	146	6	6	100.00
IF	173	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_sha2_0/rtl/prim_sha2.sv' or '../src/lowrisc_prim_sha2_0/rtl/prim_sha2.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	79	(hash_go) ? 
-2-:	79	(hash_done_o) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	292	(((~sha_en_i) || hash_go)) ? 
-2-:	292	(update_w_from_fifo) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	456	((((digest_mode_flag_q == SHA2_256) || (~MultimodeEn)) && (round_q == 7'd63))) ? 
-2-:	456	((((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512)) && (round_q == 7'd79))) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T2,T4,T5
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	271	if (((!sha_en_i) || hash_go))
-2-:	273	if (run_hash)
-3-:	274	if ((((round_q[(RndWidth256 - 1):0] == 6'((unsigned'((prim_sha2_pkg::NumRound256 - 1))))) && ((digest_mode_flag_q == SHA2_256) || (!MultimodeEn))) || ((round_q == 7'((unsigned'((prim_sha2_pkg::NumRound512 - 1))))) && ((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512)))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	1	Covered	T1,T2,T3
0	1	0	Covered	T1,T2,T3
0	0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	287	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	297	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	318	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	327	case (fifo_st_q)
-2-:	329	if (hash_go)
-3-:	334	if ((!shaf_rvalid))
-4-:	338	if ((w_index_q == 4'd15))
-5-:	349	if ((msg_feed_complete && one_chunk_done))
-6-:	353	if (one_chunk_done)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	Status	Tests
FifoIdle	1	-	-	-	-	Covered	T1,T2,T3
FifoIdle	0	-	-	-	-	Covered	T1,T2,T3
FifoLoadFromFifo	-	1	-	-	-	Covered	T1,T2,T3
FifoLoadFromFifo	-	0	1	-	-	Covered	T1,T2,T3
FifoLoadFromFifo	-	0	0	-	-	Covered	T1,T2,T3
FifoWait	-	-	-	1	-	Covered	T1,T2,T3
FifoWait	-	-	-	0	1	Covered	T1,T2,T3
FifoWait	-	-	-	0	0	Covered	T1,T2,T3
default	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	365	if ((!sha_en_i))
-2-:	368	if (hash_go)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	374	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	388	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	395	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	408	case (sha_st_q)
-2-:	410	if ((fifo_st_q == FifoWait))
-3-:	420	if (((((digest_mode_flag_q == SHA2_256) || (~MultimodeEn)) && (round_q < 7'h30)) || (((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512)) && (round_q < 7'h40))))
-4-:	424	if (one_chunk_done)
-5-:	433	if ((fifo_st_q == FifoWait))

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
ShaIdle	1	-	-	-	Covered	T1,T2,T3
ShaIdle	0	-	-	-	Covered	T1,T2,T3
ShaCompress	-	1	-	-	Covered	T1,T2,T3
ShaCompress	-	0	1	-	Covered	T1,T2,T3
ShaCompress	-	0	0	-	Covered	T1,T2,T3
ShaUpdateDigest	-	-	-	1	Not Covered
ShaUpdateDigest	-	-	-	0	Covered	T1,T2,T3
default	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	446	if (((!sha_en_i) || hash_go))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	92	if (wipe_secret_i)
-2-:	94	if (((!sha_en_i) || hash_go))
-3-:	96	if (((!run_hash) && update_w_from_fifo))
-4-:	100	if (calculate_next_w)
-5-:	101	if ((digest_mode_flag_q == SHA2_256))
-6-:	105	if (((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512)))
-7-:	108	if (run_hash)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	Status	Tests
1	-	-	-	-	-	-	Covered	T4,T29,T17
0	1	-	-	-	-	-	Covered	T1,T2,T3
0	0	1	-	-	-	-	Covered	T1,T2,T3
0	0	0	1	1	-	-	Covered	T1,T2,T3
0	0	0	1	0	1	-	Covered	T2,T4,T5
0	0	0	1	0	0	-	Not Covered
0	0	0	0	-	-	1	Covered	T1,T2,T3
0	0	0	0	-	-	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	116	if ((!rst_ni))
-2-:	117	if (MultimodeEn)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Not Covered

	LineNo.	Expression
-1-:	123	if (wipe_secret_i)
-2-:	125	if (init_hash)
-3-:	127	if (run_hash)
-4-:	128	if ((digest_mode_flag_q == SHA2_256))
-5-:	131	if (((digest_mode_flag_q == SHA2_512) || (digest_mode_flag_q == SHA2_384)))

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
1	-	-	-	-	Covered	T4,T29,T17
0	1	-	-	-	Covered	T1,T2,T3
0	0	1	1	-	Covered	T1,T2,T3
0	0	1	0	1	Covered	T2,T4,T5
0	0	1	0	0	Not Covered
0	0	0	-	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	139	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	146	if (wipe_secret_i)
-2-:	148	if (hash_start_i)
-3-:	158	if (clear_digest)
-4-:	160	if ((!sha_en_i))
-5-:	164	if (update_digest)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
1	-	-	-	-	Covered	T4,T29,T17
0	1	-	-	-	Covered	T1,T2,T3
0	0	1	-	-	Covered	T45,T15,T16
0	0	0	1	-	Covered	T1,T2,T3
0	0	0	0	1	Covered	T1,T2,T3
0	0	0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	173	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3