Unified Coverage Report :: Module :: prim_sha2_32

Module : prim_sha2_32

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.33	100.00	94.37			97.62

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_sha2_0/rtl/prim_sha2_32.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_prim_sha2_512	97.33	100.00	94.37			97.62

---

Module Instance : tb.dut.u_prim_sha2_512

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.33	100.00	94.37			97.62

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
88.39	96.75	91.64		76.00	89.18

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
84.88	95.83	85.29	100.00	40.00	88.17	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_multimode_logic.u_prim_sha2_multimode	87.34	95.54	90.97		76.00	86.84

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : prim_sha2_32

	Line No.	Total	Covered	Percent
TOTAL		100	100	100.00
CONT_ASSIGN	44	1	1	100.00
ALWAYS	63	87	87	100.00
ALWAYS	214	3	3	100.00
ALWAYS	219	3	3	100.00
ALWAYS	224	3	3	100.00
ALWAYS	229	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_sha2_0/rtl/prim_sha2_32.sv' or '../src/lowrisc_prim_sha2_0/rtl/prim_sha2_32.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
63	1	1
64	1	1
65	1	1
66	1	1
67	1	1
68	1	1
69	1	1
72	2	2
73	1	1
75	1	1
76	1	1
77	1	1
79	1	1
80	1	1
81	1	1
82	1	1
84	1	1
86	1	1
87	1	1
89	1	1
90	1	1
91	1	1
92	1	1
			MISSING_ELSE
94	1	1
96	1	1
98	1	1
101	1	1
102	1	1
104	1	1
105	1	1
108	1	1
109	1	1
110	1	1
111	1	1
112	1	1
114	1	1
115	1	1
			MISSING_ELSE
117	1	1
119	1	1
120	1	1
121	1	1
123	1	1
124	1	1
126	1	1
128	1	1
129	1	1
130	1	1
131	1	1
132	1	1
			MISSING_ELSE
134	1	1
136	1	1
			MISSING_ELSE
			==> MISSING_ELSE
139	1	1
141	1	1
142	1	1
143	1	1
144	1	1
146	1	1
147	1	1
148	1	1
149	1	1
150	1	1
151	1	1
			MISSING_ELSE
153	1	1
154	1	1
155	1	1
157	1	1
158	1	1
159	1	1
160	1	1
			MISSING_ELSE
162	1	1
163	1	1
			MISSING_ELSE
			MISSING_ELSE
168	1	1
169	1	1
170	1	1
171	1	1
173	1	1
177	2	2
178	2	2
179	1	1
182	2	2
183	2	2
184	1	1
214	2	2
215	1	1
219	2	2
220	1	1
224	2	2
225	1	1
229	2	2
230	1	1

---

Cond Coverage for Module : prim_sha2_32

	Total	Covered	Percent
Conditions	71	67	94.37
Logical	71	67	94.37
Non-Logical	0	0
Event	0	0

 LINE       44
 EXPRESSION (hash_start_i | hash_continue_i)
             ------1-----   -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T2,T3

 LINE       72
 EXPRESSION (((!sha_en_i)) || hash_go)
             ------1------    ---2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       75
 EXPRESSION (sha_en_i && fifo_rvalid_i)
             ----1---    ------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       76
 EXPRESSION (gen_multimode_logic.word_part_count_q == 2'b0)
            -----------------------1-----------------------

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T1,T2,T3

 LINE       77
 EXPRESSION (gen_multimode_logic.digest_mode_flag_q != SHA2_256)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T5

 LINE       91
 EXPRESSION (hash_process_i || gen_multimode_logic.process_flag_q)
             -------1------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T5,T6
1	0	Covered	T1,T2,T3

 LINE       94
 EXPRESSION (sha_ready == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (gen_multimode_logic.word_part_count_q == 2'b1)
            -----------------------1-----------------------

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T2,T4,T5

 LINE       114
 EXPRESSION (hash_process_i || gen_multimode_logic.process_flag_q)
             -------1------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T4,T5
0	1	Covered	T2,T6,T7
1	0	Covered	T2,T7,T9

 LINE       117
 EXPRESSION (sha_ready == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T2,T4,T5

 LINE       126
 EXPRESSION (gen_multimode_logic.word_part_count_q == 2'b10)
            ------------------------1-----------------------

-1-	Status	Tests
0	Not Covered
1	Covered	T2,T4,T5

 LINE       131
 EXPRESSION (hash_process_i || gen_multimode_logic.process_flag_q)
             -------1------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T4,T5
0	1	Covered	T6,T25,T14
1	0	Covered	T6,T25,T14

 LINE       134
 EXPRESSION (sha_ready == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T2,T4,T5

 LINE       142
 EXPRESSION ((gen_multimode_logic.word_part_count_q == 2'b0) && (hash_process_i || gen_multimode_logic.process_flag_q))
             -----------------------1-----------------------    ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       142
 SUB-EXPRESSION (gen_multimode_logic.word_part_count_q == 2'b0)
                -----------------------1-----------------------

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T1,T2,T3

 LINE       142
 SUB-EXPRESSION (hash_process_i || gen_multimode_logic.process_flag_q)
                 -------1------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       144
 EXPRESSION ((gen_multimode_logic.word_part_count_q == 2'b1) && (hash_process_i || gen_multimode_logic.process_flag_q))
             -----------------------1-----------------------    ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T5
1	0	Covered	T2,T4,T5
1	1	Covered	T2,T4,T5

 LINE       144
 SUB-EXPRESSION (gen_multimode_logic.word_part_count_q == 2'b1)
                -----------------------1-----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T5

 LINE       144
 SUB-EXPRESSION (hash_process_i || gen_multimode_logic.process_flag_q)
                 -------1------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T4,T5
1	0	Covered	T2,T4,T5

 LINE       150
 EXPRESSION (sha_ready == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T2,T4,T5

 LINE       153
 EXPRESSION (gen_multimode_logic.word_part_count_q == 2'b1)
            -----------------------1-----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T5

 LINE       155
 EXPRESSION ((gen_multimode_logic.word_part_count_q == 2'b10) && (hash_process_i || gen_multimode_logic.process_flag_q))
             ------------------------1-----------------------    ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T4,T5
1	1	Covered	T2,T4,T5

 LINE       155
 SUB-EXPRESSION (gen_multimode_logic.word_part_count_q == 2'b10)
                ------------------------1-----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T5

 LINE       155
 SUB-EXPRESSION (hash_process_i || gen_multimode_logic.process_flag_q)
                 -------1------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T25,T14
1	0	Covered	T2,T4,T5

 LINE       159
 EXPRESSION (sha_ready == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T51,T20,T17
1	Covered	T2,T4,T5

 LINE       162
 EXPRESSION (gen_multimode_logic.word_part_count_q == 2'b10)
            ------------------------1-----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T5

 LINE       168
 EXPRESSION (gen_multimode_logic.word_part_reset || hash_go || ((!sha_en_i)))
             -----------------1-----------------    ---2---    ------3------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	1	0	Covered	T1,T2,T3
1	0	0	Covered	T2,T4,T5

 LINE       182
 EXPRESSION (((!sha_en_i)) || hash_go)
             ------1------    ---2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_sha2_32

	Line No.	Total	Covered	Percent
Branches		42	41	97.62
IF	72	2	2	100.00
IF	75	23	22	95.65
IF	168	3	3	100.00
IF	177	3	3	100.00
IF	182	3	3	100.00
IF	214	2	2	100.00
IF	219	2	2	100.00
IF	224	2	2	100.00
IF	229	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_sha2_0/rtl/prim_sha2_32.sv' or '../src/lowrisc_prim_sha2_0/rtl/prim_sha2_32.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	72	if (((!sha_en_i) || hash_go))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	75	if ((sha_en_i && fifo_rvalid_i))
-2-:	76	if ((gen_multimode_logic.word_part_count_q == 2'b0))
-3-:	77	if ((gen_multimode_logic.digest_mode_flag_q != SHA2_256))
-4-:	91	if ((hash_process_i || gen_multimode_logic.process_flag_q))
-5-:	94	if ((sha_ready == 1'b1))
-6-:	101	if ((gen_multimode_logic.word_part_count_q == 2'b1))
-7-:	114	if ((hash_process_i || gen_multimode_logic.process_flag_q))
-8-:	117	if ((sha_ready == 1'b1))
-9-:	126	if ((gen_multimode_logic.word_part_count_q == 2'b10))
-10-:	131	if ((hash_process_i || gen_multimode_logic.process_flag_q))
-11-:	134	if ((sha_ready == 1'b1))
-12-:	139	if (sha_en_i)
-13-:	142	if (((gen_multimode_logic.word_part_count_q == 2'b0) && (hash_process_i || gen_multimode_logic.process_flag_q)))
-14-:	144	if (((gen_multimode_logic.word_part_count_q == 2'b1) && (hash_process_i || gen_multimode_logic.process_flag_q)))
-15-:	150	if ((sha_ready == 1'b1))
-16-:	153	if ((gen_multimode_logic.word_part_count_q == 2'b1))
-17-:	155	if (((gen_multimode_logic.word_part_count_q == 2'b10) && (hash_process_i || gen_multimode_logic.process_flag_q)))
-18-:	159	if ((sha_ready == 1'b1))
-19-:	162	if ((gen_multimode_logic.word_part_count_q == 2'b10))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	-17-	-18-	-19-	Status	Tests
1	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T4,T5
1	1	0	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
1	1	0	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
1	1	0	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
1	1	0	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
1	0	-	-	-	1	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T6,T7
1	0	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T4,T5
1	0	-	-	-	1	-	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T4,T5
1	0	-	-	-	1	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T4,T5
1	0	-	-	-	0	-	-	1	1	-	-	-	-	-	-	-	-	-	Covered	T6,T25,T14
1	0	-	-	-	0	-	-	1	0	-	-	-	-	-	-	-	-	-	Covered	T2,T4,T5
1	0	-	-	-	0	-	-	1	-	1	-	-	-	-	-	-	-	-	Covered	T2,T4,T5
1	0	-	-	-	0	-	-	1	-	0	-	-	-	-	-	-	-	-	Covered	T2,T4,T5
1	0	-	-	-	0	-	-	0	-	-	-	-	-	-	-	-	-	-	Not Covered
0	-	-	-	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	Covered	T1,T2,T3
0	-	-	-	-	-	-	-	-	-	-	1	0	1	1	-	-	-	-	Covered	T2,T4,T5
0	-	-	-	-	-	-	-	-	-	-	1	0	1	0	-	-	-	-	Covered	T2,T4,T5
0	-	-	-	-	-	-	-	-	-	-	1	0	0	-	1	-	-	-	Covered	T2,T4,T5
0	-	-	-	-	-	-	-	-	-	-	1	0	0	-	0	1	1	-	Covered	T2,T4,T5
0	-	-	-	-	-	-	-	-	-	-	1	0	0	-	0	1	0	-	Covered	T51,T20,T17
0	-	-	-	-	-	-	-	-	-	-	1	0	0	-	0	0	-	1	Covered	T2,T4,T5
0	-	-	-	-	-	-	-	-	-	-	1	0	0	-	0	0	-	0	Covered	T1,T2,T3
0	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	168	if (((gen_multimode_logic.word_part_reset || hash_go) || (!sha_en_i)))
-2-:	170	if (gen_multimode_logic.word_part_inc)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T2,T4,T5
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	177	if (hash_go)
-2-:	178	if (hash_done_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	182	if (((!sha_en_i) || hash_go))
-2-:	183	if (hash_process_i)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	214	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	224	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	229	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3