Unified Coverage Report :: Module :: prim_fifo_sync

Module : prim_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
86.88	93.33	54.17			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_tlul_adapter.u_rspfifo	89.64	92.86	80.00			85.71	100.00
tb.dut.u_tlul_adapter.u_sramreqfifo	90.93	92.31	71.43			100.00	100.00
tb.dut.u_msg_fifo	100.00	100.00	100.00			100.00	100.00
tb.dut.u_tlul_adapter.u_reqfifo	100.00	100.00	100.00			100.00	100.00
tb.dut.u_reg.u_socket.fifo_h.reqfifo	100.00	100.00					100.00
tb.dut.u_reg.u_socket.fifo_h.rspfifo	100.00	100.00					100.00
tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo	100.00	100.00					100.00

---

Module Instance : tb.dut.u_tlul_adapter.u_rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.64	92.86	80.00			85.71	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
78.74	87.18	66.67			61.11	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.68	98.55	95.56			100.00	84.62	u_tlul_adapter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	63.15	84.00	60.00			45.45

---

Module Instance : tb.dut.u_tlul_adapter.u_sramreqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.93	92.31	71.43			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
78.08	86.84	62.96			62.50	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.68	98.55	95.56			100.00	84.62	u_tlul_adapter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	63.15	84.00	60.00			45.45

---

Module Instance : tb.dut.u_msg_fifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
84.84	95.88	84.97	100.00	40.00	88.17	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00			100.00

---

Module Instance : tb.dut.u_tlul_adapter.u_reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.36	95.00	87.10			83.33	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.68	98.55	95.56			100.00	84.62	u_tlul_adapter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	81.58	92.00	80.00			72.73

---

Module Instance : tb.dut.u_reg.u_socket.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg.u_socket.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_fifo_sync ( parameter Width=36,Pass=1,Depth=32,OutputZeroIfEmpty=1,Secure=0,DepthW=6,gen_normal_fifo.PtrW=5 )
Line Coverage for Module self-instances :

SCORE	LINE
100.00	100.00

tb.dut.u_msg_fifo

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	130	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
130	1	1
131	1	1
138	1	1

---

Line Coverage for Module : prim_fifo_sync ( parameter Width=17,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
100.00	100.00

tb.dut.u_tlul_adapter.u_reqfifo

	Line No.	Total	Covered	Percent
TOTAL		15	15	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
ALWAYS	111	2	2	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
108	1	1
111	1	1
112	1	1
			MISSING_ELSE
116	1	1
133	1	1
134	1	1
138	1	1

---

Line Coverage for Module : prim_fifo_sync ( parameter Width=5,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
90.93	92.31

tb.dut.u_tlul_adapter.u_sramreqfifo

	Line No.	Total	Covered	Percent
TOTAL		15	12	80.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	0	0.00
ALWAYS	111	2	1	50.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	133	1	0	0.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
108	0	1
111	1	1
112	0	1
			MISSING_ELSE
116	1	1
133	0	1
134	1	1
138	1	1

---

Line Coverage for Module : prim_fifo_sync ( parameter Width=40,Pass=1,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
89.64	92.86

tb.dut.u_tlul_adapter.u_rspfifo

	Line No.	Total	Covered	Percent
TOTAL		15	13	86.67
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	0	0.00
ALWAYS	111	2	1	50.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	130	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
108	0	1
111	1	1
112	0	1
			MISSING_ELSE
116	1	1
130	1	1
131	1	1
138	1	1

---

Line Coverage for Module : prim_fifo_sync ( parameter Width=108,Pass=1,Depth=0,OutputZeroIfEmpty=1,Secure=0,DepthW=1 + Width=65,Pass=1,Depth=0,OutputZeroIfEmpty=1,Secure=0,DepthW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_socket.fifo_h.reqfifo

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_socket.fifo_h.rspfifo

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Cond Coverage for Module : prim_fifo_sync ( parameter Width=5,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
90.93	71.43

tb.dut.u_tlul_adapter.u_sramreqfifo

	Total	Covered	Percent
Conditions	16	5	31.25
Logical	16	5	31.25
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Not Covered

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (5'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T2,T3

---

Cond Coverage for Module : prim_fifo_sync ( parameter Width=36,Pass=1,Depth=32,OutputZeroIfEmpty=1,Secure=0,DepthW=6,gen_normal_fifo.PtrW=5 )
Cond Coverage for Module self-instances :

SCORE	COND
100.00	100.00

tb.dut.u_msg_fifo

	Total	Covered	Percent
Conditions	24	20	83.33
Logical	24	20	83.33
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T12,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T5,T8,T19
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (36'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Cond Coverage for Module : prim_fifo_sync ( parameter Width=40,Pass=1,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
89.64	80.00

tb.dut.u_tlul_adapter.u_rspfifo

	Total	Covered	Percent
Conditions	24	8	33.33
Logical	24	8	33.33
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Not Covered

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (40'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T2,T3

---

Cond Coverage for Module : prim_fifo_sync ( parameter Width=17,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
100.00	100.00

tb.dut.u_tlul_adapter.u_reqfifo

	Total	Covered	Percent
Conditions	16	11	68.75
Logical	16	11	68.75
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T6,T4,T19
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (17'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_fifo_sync ( parameter Width=36,Pass=1,Depth=32,OutputZeroIfEmpty=1,Secure=0,DepthW=6,gen_normal_fifo.PtrW=5 + Width=40,Pass=1,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 )
Branch Coverage for Module self-instances :

SCORE	BRANCH
100.00	100.00

tb.dut.u_msg_fifo

SCORE	BRANCH
89.64	85.71

tb.dut.u_tlul_adapter.u_rspfifo

	Line No.	Total	Covered	Percent
Branches		9	9	100.00
TERNARY	130	2	2	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	130	((gen_normal_fifo.fifo_empty && wvalid_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_fifo_sync ( parameter Width=17,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 + Width=5,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 )
Branch Coverage for Module self-instances :

SCORE	BRANCH
100.00	100.00

tb.dut.u_tlul_adapter.u_reqfifo

SCORE	BRANCH
90.93	100.00

tb.dut.u_tlul_adapter.u_sramreqfifo

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	554509863	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	1721547904	80567499	0	0
gen_passthru_fifo.paramCheckPass	4380	4380	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	554509863	0	0
T1	51296	3066	0	0
T2	2022272	1663387	0	0
T3	318216	22104	0	0
T4	6802488	1098360	0	0
T5	521184	187796	0	0
T6	549544	88811	0	0
T7	1214248	252404	0	0
T8	749104	290254	0	0
T12	126456	45391	0	0
T19	0	126989	0	0
T31	14880	842	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	64120	63430	0	0
T2	2527840	2527750	0	0
T3	397770	396880	0	0
T4	8503110	8502120	0	0
T5	651480	650600	0	0
T6	686930	686240	0	0
T7	1517810	1517070	0	0
T8	936380	935450	0	0
T12	158070	157160	0	0
T31	18600	17880	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	64120	63430	0	0
T2	2527840	2527750	0	0
T3	397770	396880	0	0
T4	8503110	8502120	0	0
T5	651480	650600	0	0
T6	686930	686240	0	0
T7	1517810	1517070	0	0
T8	936380	935450	0	0
T12	158070	157160	0	0
T31	18600	17880	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	64120	63430	0	0
T2	2527840	2527750	0	0
T3	397770	396880	0	0
T4	8503110	8502120	0	0
T5	651480	650600	0	0
T6	686930	686240	0	0
T7	1517810	1517070	0	0
T8	936380	935450	0	0
T12	158070	157160	0	0
T31	18600	17880	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	1721547904	80567499	0	0
T1	12824	651	0	0
T2	505568	215066	0	0
T3	79554	4064	0	0
T4	1700622	172088	0	0
T5	130296	68020	0	0
T6	137386	13609	0	0
T7	303562	48291	0	0
T8	187276	98396	0	0
T12	31614	14689	0	0
T19	0	68240	0	0
T31	3720	0	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	4380	4380	0	0
T1	6	6	0	0
T2	6	6	0	0
T3	6	6	0	0
T4	6	6	0	0
T5	6	6	0	0
T6	6	6	0	0
T7	6	6	0	0
T8	6	6	0	0
T12	6	6	0	0
T31	6	6	0	0

Line Coverage for Instance : tb.dut.u_tlul_adapter.u_rspfifo

	Line No.	Total	Covered	Percent
TOTAL		14	13	92.86
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	0	0.00
ALWAYS	111	1	1	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	130	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
108	0	1
111	1	1
112		excluded
			Exclude Annotation: VC_COV_UNR
			MISSING_ELSE
116	1	1
130	1	1
131	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.u_tlul_adapter.u_rspfifo

	Total	Covered	Percent
Conditions	10	8	80.00
Logical	10	8	80.00
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T2,T3
1	0	Excluded		VC_COV_UNR
1	1	Excluded		VC_COV_UNR

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Excluded		VC_COV_UNR
1	1	1	Excluded		VC_COV_UNR

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Excluded		VC_COV_UNR
1	0	1	Excluded		VC_COV_UNR
1	1	0	Excluded		VC_COV_UNR
1	1	1	Excluded		VC_COV_UNR

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------

-1-	Status	Tests	Exclude Annotation
0	Covered	T1,T2,T3
1	Excluded		VC_COV_UNR

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Excluded		VC_COV_UNR
1	0	Covered	T1,T2,T3
1	1	Excluded		VC_COV_UNR

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Excluded		VC_COV_UNR
1	0	Excluded		VC_COV_UNR
1	1	Covered	T1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (40'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_tlul_adapter.u_rspfifo

	Line No.	Total	Covered	Percent
Branches		7	6	85.71
TERNARY	130	1	1	100.00
TERNARY	138	1	1	100.00
IF	69	3	3	100.00
IF	123	2	1	50.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	130	((gen_normal_fifo.fifo_empty && wvalid_i)) ? 

Branches:

-1-	Status	Tests	Exclude Annotation
1	Excluded		VC_COV_UNR
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests	Exclude Annotation
1	Covered	T1,T2,T3
0	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_tlul_adapter.u_rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete	Exclusion	Exclude Annotation
DataKnown_A					Excluded	[UNSUPPORTED] excluded by fpv
DepthKnown_A	430386976	430313743	0	0
RvalidKnown_A	430386976	430313743	0	0
WreadyKnown_A	430386976	430313743	0	0
gen_normal_fifo.depthShallNotExceedParamDepth					Excluded	[UNSUPPORTED] excluded by fpv

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430386976	430313743	0	0
T1	6412	6343	0	0
T2	252784	252775	0	0
T3	39777	39688	0	0
T4	850311	850212	0	0
T5	65148	65060	0	0
T6	68693	68624	0	0
T7	151781	151707	0	0
T8	93638	93545	0	0
T12	15807	15716	0	0
T31	1860	1788	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430386976	430313743	0	0
T1	6412	6343	0	0
T2	252784	252775	0	0
T3	39777	39688	0	0
T4	850311	850212	0	0
T5	65148	65060	0	0
T6	68693	68624	0	0
T7	151781	151707	0	0
T8	93638	93545	0	0
T12	15807	15716	0	0
T31	1860	1788	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430386976	430313743	0	0
T1	6412	6343	0	0
T2	252784	252775	0	0
T3	39777	39688	0	0
T4	850311	850212	0	0
T5	65148	65060	0	0
T6	68693	68624	0	0
T7	151781	151707	0	0
T8	93638	93545	0	0
T12	15807	15716	0	0
T31	1860	1788	0	0

Line Coverage for Instance : tb.dut.u_tlul_adapter.u_sramreqfifo

	Line No.	Total	Covered	Percent
TOTAL		13	12	92.31
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	0	0
ALWAYS	111	1	1	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	133	1	0	0.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
108		excluded
			Exclude Annotation: [UNR] Pass is always '1'
111	1	1
112		excluded
			Exclude Annotation: VC_COV_UNR
			MISSING_ELSE
116	1	1
133	0	1
134	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.u_tlul_adapter.u_sramreqfifo

	Total	Covered	Percent
Conditions	7	5	71.43
Logical	7	5	71.43
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T2,T3
1	0	Excluded		VC_COV_UNR
1	1	Excluded		VC_COV_UNR

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Excluded		VC_COV_UNR
1	1	1	Excluded		VC_COV_UNR

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Excluded		VC_COV_UNR
1	0	1	Excluded		VC_COV_UNR
1	1	0	Excluded		VC_COV_UNR
1	1	1	Excluded		VC_COV_UNR

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (5'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_tlul_adapter.u_sramreqfifo

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
TERNARY	138	1	1	100.00
IF	69	3	3	100.00
IF	111	1	1	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests	Exclude Annotation
1	Covered	T1,T2,T3
0	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests	Exclude Annotation
1	Excluded		VC_COV_UNR
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_tlul_adapter.u_sramreqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete	Exclusion	Exclude Annotation
DataKnown_A					Excluded	[UNSUPPORTED] excluded by fpv
DepthKnown_A	430386976	430313743	0	0
RvalidKnown_A	430386976	430313743	0	0
WreadyKnown_A	430386976	430313743	0	0
gen_normal_fifo.depthShallNotExceedParamDepth					Excluded	[UNSUPPORTED] excluded by fpv

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430386976	430313743	0	0
T1	6412	6343	0	0
T2	252784	252775	0	0
T3	39777	39688	0	0
T4	850311	850212	0	0
T5	65148	65060	0	0
T6	68693	68624	0	0
T7	151781	151707	0	0
T8	93638	93545	0	0
T12	15807	15716	0	0
T31	1860	1788	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430386976	430313743	0	0
T1	6412	6343	0	0
T2	252784	252775	0	0
T3	39777	39688	0	0
T4	850311	850212	0	0
T5	65148	65060	0	0
T6	68693	68624	0	0
T7	151781	151707	0	0
T8	93638	93545	0	0
T12	15807	15716	0	0
T31	1860	1788	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430386976	430313743	0	0
T1	6412	6343	0	0
T2	252784	252775	0	0
T3	39777	39688	0	0
T4	850311	850212	0	0
T5	65148	65060	0	0
T6	68693	68624	0	0
T7	151781	151707	0	0
T8	93638	93545	0	0
T12	15807	15716	0	0
T31	1860	1788	0	0

Line Coverage for Instance : tb.dut.u_msg_fifo

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	130	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
130	1	1
131	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.u_msg_fifo

	Total	Covered	Percent
Conditions	20	20	100.00
Logical	20	20	100.00
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T12,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T2,T3
1	0	Excluded		VC_COV_UNR
1	1	Covered	T1,T2,T3

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T5,T8,T19
1	1	0	Excluded		VC_COV_UNR
1	1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Excluded		VC_COV_UNR
1	0	1	Covered	T1,T2,T3
1	1	0	Excluded		VC_COV_UNR
1	1	1	Covered	T1,T2,T3

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (36'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_msg_fifo

	Line No.	Total	Covered	Percent
Branches		9	9	100.00
TERNARY	130	2	2	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	130	((gen_normal_fifo.fifo_empty && wvalid_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_msg_fifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	430386976	43246606	0	0
DepthKnown_A	430386976	430313743	0	0
RvalidKnown_A	430386976	430313743	0	0
WreadyKnown_A	430386976	430313743	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	430386976	43246606	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430386976	43246606	0	0
T1	6412	597	0	0
T2	252784	140707	0	0
T3	39777	3638	0	0
T4	850311	27958	0	0
T5	65148	52688	0	0
T6	68693	4028	0	0
T7	151781	29914	0	0
T8	93638	74101	0	0
T12	15807	11149	0	0
T19	0	51879	0	0
T31	1860	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430386976	430313743	0	0
T1	6412	6343	0	0
T2	252784	252775	0	0
T3	39777	39688	0	0
T4	850311	850212	0	0
T5	65148	65060	0	0
T6	68693	68624	0	0
T7	151781	151707	0	0
T8	93638	93545	0	0
T12	15807	15716	0	0
T31	1860	1788	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430386976	430313743	0	0
T1	6412	6343	0	0
T2	252784	252775	0	0
T3	39777	39688	0	0
T4	850311	850212	0	0
T5	65148	65060	0	0
T6	68693	68624	0	0
T7	151781	151707	0	0
T8	93638	93545	0	0
T12	15807	15716	0	0
T31	1860	1788	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430386976	430313743	0	0
T1	6412	6343	0	0
T2	252784	252775	0	0
T3	39777	39688	0	0
T4	850311	850212	0	0
T5	65148	65060	0	0
T6	68693	68624	0	0
T7	151781	151707	0	0
T8	93638	93545	0	0
T12	15807	15716	0	0
T31	1860	1788	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	430386976	43246606	0	0
T1	6412	597	0	0
T2	252784	140707	0	0
T3	39777	3638	0	0
T4	850311	27958	0	0
T5	65148	52688	0	0
T6	68693	4028	0	0
T7	151781	29914	0	0
T8	93638	74101	0	0
T12	15807	11149	0	0
T19	0	51879	0	0
T31	1860	0	0	0

Line Coverage for Instance : tb.dut.u_tlul_adapter.u_reqfifo

	Line No.	Total	Covered	Percent
TOTAL		15	15	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
ALWAYS	111	2	2	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
108	1	1
111	1	1
112	1	1
			MISSING_ELSE
116	1	1
133	1	1
134	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.u_tlul_adapter.u_reqfifo

	Total	Covered	Percent
Conditions	11	11	100.00
Logical	11	11	100.00
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T2,T3
1	0	Excluded		VC_COV_UNR
1	1	Covered	T1,T2,T3

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Excluded		VC_COV_UNR
1	1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Excluded		VC_COV_UNR
1	0	1	Covered	T6,T4,T19
1	1	0	Excluded		VC_COV_UNR
1	1	1	Covered	T1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (17'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_tlul_adapter.u_reqfifo

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_tlul_adapter.u_reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	430386976	37320893	0	0
DepthKnown_A	430386976	430313743	0	0
RvalidKnown_A	430386976	430313743	0	0
WreadyKnown_A	430386976	430313743	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	430386976	37320893	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430386976	37320893	0	0
T1	6412	54	0	0
T2	252784	74359	0	0
T3	39777	426	0	0
T4	850311	144130	0	0
T5	65148	15332	0	0
T6	68693	9581	0	0
T7	151781	18377	0	0
T8	93638	24295	0	0
T12	15807	3540	0	0
T19	0	16361	0	0
T31	1860	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430386976	430313743	0	0
T1	6412	6343	0	0
T2	252784	252775	0	0
T3	39777	39688	0	0
T4	850311	850212	0	0
T5	65148	65060	0	0
T6	68693	68624	0	0
T7	151781	151707	0	0
T8	93638	93545	0	0
T12	15807	15716	0	0
T31	1860	1788	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430386976	430313743	0	0
T1	6412	6343	0	0
T2	252784	252775	0	0
T3	39777	39688	0	0
T4	850311	850212	0	0
T5	65148	65060	0	0
T6	68693	68624	0	0
T7	151781	151707	0	0
T8	93638	93545	0	0
T12	15807	15716	0	0
T31	1860	1788	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430386976	430313743	0	0
T1	6412	6343	0	0
T2	252784	252775	0	0
T3	39777	39688	0	0
T4	850311	850212	0	0
T5	65148	65060	0	0
T6	68693	68624	0	0
T7	151781	151707	0	0
T8	93638	93545	0	0
T12	15807	15716	0	0
T31	1860	1788	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	430386976	37320893	0	0
T1	6412	54	0	0
T2	252784	74359	0	0
T3	39777	426	0	0
T4	850311	144130	0	0
T5	65148	15332	0	0
T6	68693	9581	0	0
T7	151781	18377	0	0
T8	93638	24295	0	0
T12	15807	3540	0	0
T19	0	16361	0	0
T31	1860	0	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	443114881	98510104	0	0
DepthKnown_A	443114881	442992903	0	0
RvalidKnown_A	443114881	442992903	0	0
WreadyKnown_A	443114881	442992903	0	0
gen_passthru_fifo.paramCheckPass	730	730	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443114881	98510104	0	0
T1	6412	606	0	0
T2	252784	363422	0	0
T3	39777	4516	0	0
T4	850311	91471	0	0
T5	65148	42054	0	0
T6	68693	7530	0	0
T7	151781	53103	0	0
T8	93638	68512	0	0
T12	15807	8492	0	0
T31	1860	71	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443114881	442992903	0	0
T1	6412	6343	0	0
T2	252784	252775	0	0
T3	39777	39688	0	0
T4	850311	850212	0	0
T5	65148	65060	0	0
T6	68693	68624	0	0
T7	151781	151707	0	0
T8	93638	93545	0	0
T12	15807	15716	0	0
T31	1860	1788	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443114881	442992903	0	0
T1	6412	6343	0	0
T2	252784	252775	0	0
T3	39777	39688	0	0
T4	850311	850212	0	0
T5	65148	65060	0	0
T6	68693	68624	0	0
T7	151781	151707	0	0
T8	93638	93545	0	0
T12	15807	15716	0	0
T31	1860	1788	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443114881	442992903	0	0
T1	6412	6343	0	0
T2	252784	252775	0	0
T3	39777	39688	0	0
T4	850311	850212	0	0
T5	65148	65060	0	0
T6	68693	68624	0	0
T7	151781	151707	0	0
T8	93638	93545	0	0
T12	15807	15716	0	0
T31	1860	1788	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	730	730	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T12	1	1	0	0
T31	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	443114881	140598532	0	0
DepthKnown_A	443114881	442992903	0	0
RvalidKnown_A	443114881	442992903	0	0
WreadyKnown_A	443114881	442992903	0	0
gen_passthru_fifo.paramCheckPass	730	730	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443114881	140598532	0	0
T1	6412	603	0	0
T2	252784	361392	0	0
T3	39777	4504	0	0
T4	850311	371665	0	0
T5	65148	17834	0	0
T6	68693	30071	0	0
T7	151781	48955	0	0
T8	93638	27417	0	0
T12	15807	6859	0	0
T31	1860	350	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443114881	442992903	0	0
T1	6412	6343	0	0
T2	252784	252775	0	0
T3	39777	39688	0	0
T4	850311	850212	0	0
T5	65148	65060	0	0
T6	68693	68624	0	0
T7	151781	151707	0	0
T8	93638	93545	0	0
T12	15807	15716	0	0
T31	1860	1788	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443114881	442992903	0	0
T1	6412	6343	0	0
T2	252784	252775	0	0
T3	39777	39688	0	0
T4	850311	850212	0	0
T5	65148	65060	0	0
T6	68693	68624	0	0
T7	151781	151707	0	0
T8	93638	93545	0	0
T12	15807	15716	0	0
T31	1860	1788	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443114881	442992903	0	0
T1	6412	6343	0	0
T2	252784	252775	0	0
T3	39777	39688	0	0
T4	850311	850212	0	0
T5	65148	65060	0	0
T6	68693	68624	0	0
T7	151781	151707	0	0
T8	93638	93545	0	0
T12	15807	15716	0	0
T31	1860	1788	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	730	730	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T12	1	1	0	0
T31	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	443114881	30768896	0	0
DepthKnown_A	443114881	442992903	0	0
RvalidKnown_A	443114881	442992903	0	0
WreadyKnown_A	443114881	442992903	0	0
gen_passthru_fifo.paramCheckPass	730	730	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443114881	30768896	0	0
T1	6412	54	0	0
T2	252784	75082	0	0
T3	39777	438	0	0
T4	850311	40992	0	0
T5	65148	39552	0	0
T6	68693	3013	0	0
T7	151781	22522	0	0
T8	93638	65390	0	0
T12	15807	5173	0	0
T19	0	42388	0	0
T31	1860	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443114881	442992903	0	0
T1	6412	6343	0	0
T2	252784	252775	0	0
T3	39777	39688	0	0
T4	850311	850212	0	0
T5	65148	65060	0	0
T6	68693	68624	0	0
T7	151781	151707	0	0
T8	93638	93545	0	0
T12	15807	15716	0	0
T31	1860	1788	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443114881	442992903	0	0
T1	6412	6343	0	0
T2	252784	252775	0	0
T3	39777	39688	0	0
T4	850311	850212	0	0
T5	65148	65060	0	0
T6	68693	68624	0	0
T7	151781	151707	0	0
T8	93638	93545	0	0
T12	15807	15716	0	0
T31	1860	1788	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443114881	442992903	0	0
T1	6412	6343	0	0
T2	252784	252775	0	0
T3	39777	39688	0	0
T4	850311	850212	0	0
T5	65148	65060	0	0
T6	68693	68624	0	0
T7	151781	151707	0	0
T8	93638	93545	0	0
T12	15807	15716	0	0
T31	1860	1788	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	730	730	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T12	1	1	0	0
T31	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	443114881	37808574	0	0
DepthKnown_A	443114881	442992903	0	0
RvalidKnown_A	443114881	442992903	0	0
WreadyKnown_A	443114881	442992903	0	0
gen_passthru_fifo.paramCheckPass	730	730	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443114881	37808574	0	0
T1	6412	54	0	0
T2	252784	74359	0	0
T3	39777	426	0	0
T4	850311	144130	0	0
T5	65148	15332	0	0
T6	68693	9581	0	0
T7	151781	18377	0	0
T8	93638	24295	0	0
T12	15807	3540	0	0
T19	0	16361	0	0
T31	1860	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443114881	442992903	0	0
T1	6412	6343	0	0
T2	252784	252775	0	0
T3	39777	39688	0	0
T4	850311	850212	0	0
T5	65148	65060	0	0
T6	68693	68624	0	0
T7	151781	151707	0	0
T8	93638	93545	0	0
T12	15807	15716	0	0
T31	1860	1788	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443114881	442992903	0	0
T1	6412	6343	0	0
T2	252784	252775	0	0
T3	39777	39688	0	0
T4	850311	850212	0	0
T5	65148	65060	0	0
T6	68693	68624	0	0
T7	151781	151707	0	0
T8	93638	93545	0	0
T12	15807	15716	0	0
T31	1860	1788	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443114881	442992903	0	0
T1	6412	6343	0	0
T2	252784	252775	0	0
T3	39777	39688	0	0
T4	850311	850212	0	0
T5	65148	65060	0	0
T6	68693	68624	0	0
T7	151781	151707	0	0
T8	93638	93545	0	0
T12	15807	15716	0	0
T31	1860	1788	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	730	730	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T12	1	1	0	0
T31	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	443114881	63466300	0	0
DepthKnown_A	443114881	442992903	0	0
RvalidKnown_A	443114881	442992903	0	0
WreadyKnown_A	443114881	442992903	0	0
gen_passthru_fifo.paramCheckPass	730	730	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443114881	63466300	0	0
T1	6412	549	0	0
T2	252784	287033	0	0
T3	39777	4078	0	0
T4	850311	50479	0	0
T5	65148	2502	0	0
T6	68693	4517	0	0
T7	151781	30578	0	0
T8	93638	3122	0	0
T12	15807	3319	0	0
T31	1860	71	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443114881	442992903	0	0
T1	6412	6343	0	0
T2	252784	252775	0	0
T3	39777	39688	0	0
T4	850311	850212	0	0
T5	65148	65060	0	0
T6	68693	68624	0	0
T7	151781	151707	0	0
T8	93638	93545	0	0
T12	15807	15716	0	0
T31	1860	1788	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443114881	442992903	0	0
T1	6412	6343	0	0
T2	252784	252775	0	0
T3	39777	39688	0	0
T4	850311	850212	0	0
T5	65148	65060	0	0
T6	68693	68624	0	0
T7	151781	151707	0	0
T8	93638	93545	0	0
T12	15807	15716	0	0
T31	1860	1788	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443114881	442992903	0	0
T1	6412	6343	0	0
T2	252784	252775	0	0
T3	39777	39688	0	0
T4	850311	850212	0	0
T5	65148	65060	0	0
T6	68693	68624	0	0
T7	151781	151707	0	0
T8	93638	93545	0	0
T12	15807	15716	0	0
T31	1860	1788	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	730	730	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T12	1	1	0	0
T31	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	443114881	102789958	0	0
DepthKnown_A	443114881	442992903	0	0
RvalidKnown_A	443114881	442992903	0	0
WreadyKnown_A	443114881	442992903	0	0
gen_passthru_fifo.paramCheckPass	730	730	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443114881	102789958	0	0
T1	6412	549	0	0
T2	252784	287033	0	0
T3	39777	4078	0	0
T4	850311	227535	0	0
T5	65148	2502	0	0
T6	68693	20490	0	0
T7	151781	30578	0	0
T8	93638	3122	0	0
T12	15807	3319	0	0
T31	1860	350	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443114881	442992903	0	0
T1	6412	6343	0	0
T2	252784	252775	0	0
T3	39777	39688	0	0
T4	850311	850212	0	0
T5	65148	65060	0	0
T6	68693	68624	0	0
T7	151781	151707	0	0
T8	93638	93545	0	0
T12	15807	15716	0	0
T31	1860	1788	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443114881	442992903	0	0
T1	6412	6343	0	0
T2	252784	252775	0	0
T3	39777	39688	0	0
T4	850311	850212	0	0
T5	65148	65060	0	0
T6	68693	68624	0	0
T7	151781	151707	0	0
T8	93638	93545	0	0
T12	15807	15716	0	0
T31	1860	1788	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443114881	442992903	0	0
T1	6412	6343	0	0
T2	252784	252775	0	0
T3	39777	39688	0	0
T4	850311	850212	0	0
T5	65148	65060	0	0
T6	68693	68624	0	0
T7	151781	151707	0	0
T8	93638	93545	0	0
T12	15807	15716	0	0
T31	1860	1788	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	730	730	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T12	1	1	0	0
T31	1	1	0	0