Module Definition
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Module : tlul_adapter_sram
SCORELINECONDTOGGLEFSMBRANCHASSERT
84.49 97.14 75.44 80.77 84.62

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_tlul_adapter 94.68 98.55 95.56 100.00 84.62



Module Instance : tb.dut.u_tlul_adapter

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.68 98.55 95.56 100.00 84.62


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
88.51 94.09 86.85 80.25 92.86


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
84.84 95.88 84.97 100.00 40.00 88.17 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_err 100.00 100.00 100.00 100.00 100.00
u_reqfifo 91.36 95.00 87.10 83.33 100.00
u_rsp_gen 100.00 100.00 100.00
u_rspfifo 78.74 87.18 66.67 61.11 100.00
u_sram_byte 100.00 100.00 100.00
u_sramreqfifo 78.08 86.84 62.96 62.50 100.00

Line Coverage for Module : tlul_adapter_sram
Line No.TotalCoveredPercent
TOTAL706897.14
CONT_ASSIGN10700
CONT_ASSIGN11400
ALWAYS12933100.00
CONT_ASSIGN13811100.00
CONT_ASSIGN14411100.00
CONT_ASSIGN15111100.00
CONT_ASSIGN16211100.00
CONT_ASSIGN17611100.00
CONT_ASSIGN18811100.00
CONT_ASSIGN27411100.00
CONT_ASSIGN27511100.00
CONT_ASSIGN27611100.00
ALWAYS2818787.50
ALWAYS30166100.00
CONT_ASSIGN31511100.00
CONT_ASSIGN31911100.00
CONT_ASSIGN33811100.00
CONT_ASSIGN34311100.00
CONT_ASSIGN34911100.00
CONT_ASSIGN36111100.00
ALWAYS36433100.00
CONT_ASSIGN37111100.00
CONT_ASSIGN39211100.00
CONT_ASSIGN39311100.00
CONT_ASSIGN39411100.00
CONT_ASSIGN39511100.00
ALWAYS42566100.00
ALWAYS43755100.00
CONT_ASSIGN45211100.00
CONT_ASSIGN45311100.00
CONT_ASSIGN45411100.00
CONT_ASSIGN45811100.00
CONT_ASSIGN45911100.00
CONT_ASSIGN46111100.00
CONT_ASSIGN46211100.00
CONT_ASSIGN46911100.00
CONT_ASSIGN47211100.00
CONT_ASSIGN47611100.00
CONT_ASSIGN477100.00
CONT_ASSIGN47911100.00
CONT_ASSIGN48111100.00
CONT_ASSIGN49000
ALWAYS52133100.00
CONT_ASSIGN52711100.00
CONT_ASSIGN53011100.00
CONT_ASSIGN53511100.00
CONT_ASSIGN54000
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
107 unreachable
114 unreachable
129 1 1
130 1 1
131 1 1
132 unreachable
MISSING_ELSE
138 1 1
144 1 1
151 1 1
162 1 1
176 1 1
188 1 1
274 1 1
275 1 1
276 1 1
281 1 1
283 1 1
284 1 1
286 1 1
287 1 1
288 0 1
291 1 1
294 1 1
301 1 1
303 1 1
304 1 1
305 1 1
307 1 1
310 1 1
315 1 1
319 1 1
338 1 1
343 1 1
349 1 1
361 1 1
364 1 1
365 1 1
367 1 1
371 1 1
392 1 1
393 1 1
394 1 1
395 1 1
425 1 1
426 1 1
428 1 1
429 1 1
430 1 1
431 1 1
MISSING_ELSE
437 1 1
438 1 1
440 1 1
441 1 1
442 1 1
MISSING_ELSE
452 1 1
453 1 1
454 1 1
458 1 1
459 1 1
461 1 1
462 1 1
469 1 1
472 1 1
476 1 1
477 0 1
479 1 1
481 1 1
490 unreachable
521 1 1
522 1 1
523 1 1
527 1 1
530 1 1
535 1 1
540 unreachable


Cond Coverage for Module : tlul_adapter_sram
TotalCoveredPercent
Conditions1148675.44
Logical1148675.44
Non-Logical00
Event00

 LINE       114
 EXPRESSION (readback_error | readback_error_q)
             -------1------   --------2-------
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10Unreachable

 LINE       131
 EXPRESSION (intg_error || rsp_fifo_error || sramreqfifo_error || reqfifo_error)
             -----1----    -------2------    --------3--------    ------4------
-1--2--3--4-StatusTests
0000CoveredT1,T2,T3
0001Unreachable
0010Unreachable
0100Unreachable
1000Unreachable

 LINE       138
 EXPRESSION (intg_error | rsp_fifo_error | sramreqfifo_error | reqfifo_error | intg_error_q)
             -----1----   -------2------   --------3--------   ------4------   ------5-----
-1--2--3--4--5-StatusTests
00000CoveredT1,T2,T3
00001Not Covered
00010Unreachable
00100Unreachable
01000Unreachable
10000Unreachable

 LINE       144
 EXPRESSION 
 Number  Term
      1  ((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData)) ? (((ByteAccess == 1'b0) ? ((tl_i.a_mask != '1) || (tl_i.a_size != 2'h2)) : 1'b0)) : 1'b0)
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       144
 SUB-EXPRESSION ((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData))
                 ---------------1--------------    ----------------2----------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3

 LINE       144
 SUB-EXPRESSION (tl_i.a_opcode == PutFullData)
                ---------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       144
 SUB-EXPRESSION (tl_i.a_opcode == PutPartialData)
                ----------------1----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       162
 EXPRESSION (tl_i.a_opcode == Get)
            -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       176
 EXPRESSION (wr_attr_error | wr_vld_error | rd_vld_error | instr_error | tlul_error | intg_error)
             ------1------   ------2-----   ------3-----   -----4-----   -----5----   -----6----
-1--2--3--4--5--6-StatusTests
000000CoveredT1,T2,T3
000001Unreachable
000010CoveredT1,T2,T3
000100Not Covered
001000CoveredT24,T27,T28
010000Unreachable
100000Not Covered

 LINE       274
 EXPRESSION (tl_i_int.a_valid & tl_o_int.a_ready)
             --------1-------   --------2-------
-1--2-StatusTests
01CoveredT24,T27,T28
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       275
 EXPRESSION (tl_o_int.d_valid & tl_i_int.d_ready)
             --------1-------   --------2-------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT6,T4,T19
11CoveredT1,T2,T3

 LINE       276
 EXPRESSION (req_o & gnt_i)
             --1--   --2--
-1--2-StatusTests
01Not Covered
10CoveredT5,T8,T19
11CoveredT1,T2,T3

 LINE       287
 EXPRESSION (reqfifo_rdata.op == OpRead)
            --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       304
 EXPRESSION (reqfifo_rdata.op == OpRead)
            --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT24,T27,T28

 LINE       305
 EXPRESSION (rspfifo_rdata.error | reqfifo_rdata.error)
             ---------1---------   ---------2---------
-1--2-StatusTests
00Not Covered
01CoveredT24,T27,T28
10Not Covered

 LINE       315
 EXPRESSION (d_valid & reqfifo_rvalid & rspfifo_rvalid & (reqfifo_rdata.op == OpRead))
             ---1---   -------2------   -------3------   --------------4-------------
-1--2--3--4-StatusTests
0111Not Covered
1011Not Covered
1101CoveredT24,T27,T28
1110Not Covered
1111Not Covered

 LINE       315
 SUB-EXPRESSION (reqfifo_rdata.op == OpRead)
                --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT24,T27,T28

 LINE       343
 EXPRESSION ((vld_rd_rsp & ((~d_error))) ? rspfifo_rdata.data : error_blanking_data)
             -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       343
 SUB-EXPRESSION (vld_rd_rsp & ((~d_error)))
                 -----1----   ------2-----
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       349
 EXPRESSION ((vld_rd_rsp && reqfifo_rdata.error) ? error_blanking_integ : (vld_rd_rsp ? rspfifo_rdata.data_intg : prim_secded_pkg::SecdedInv3932ZeroEcc))
             -----------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       349
 SUB-EXPRESSION (vld_rd_rsp && reqfifo_rdata.error)
                 -----1----    ---------2---------
-1--2-StatusTests
01CoveredT24,T27,T28
10Not Covered
11Not Covered

 LINE       349
 SUB-EXPRESSION (vld_rd_rsp ? rspfifo_rdata.data_intg : prim_secded_pkg::SecdedInv3932ZeroEcc)
                 -----1----
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       361
 EXPRESSION (error_internal & tl_i_int.a_valid & ((~tl_o_int.a_ready)))
             -------1------   --------2-------   ----------3----------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T2,T3
110CoveredT24,T27,T28
111CoveredT24,T27,T28

 LINE       371
 EXPRESSION ((d_valid && (reqfifo_rdata.op != OpRead)) ? AccessAck : AccessAckData)
             --------------------1--------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       371
 SUB-EXPRESSION (d_valid && (reqfifo_rdata.op != OpRead))
                 ---1---    --------------2-------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT24,T27,T28
11CoveredT1,T2,T3

 LINE       371
 SUB-EXPRESSION (reqfifo_rdata.op != OpRead)
                --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       371
 EXPRESSION (d_valid ? reqfifo_rdata.size : '0)
             ---1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       371
 EXPRESSION (d_valid ? reqfifo_rdata.source : '0)
             ---1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       371
 EXPRESSION (d_valid && d_error)
             ---1---    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT24,T27,T28

 LINE       371
 EXPRESSION ((gnt_i | missed_err_gnt_q) & reqfifo_wready & sramreqfifo_wready & sramreqaddrfifo_wready)
             -------------1------------   -------2------   ---------3--------   -----------4----------
-1--2--3--4-StatusTests
0111CoveredT1,T2,T3
1011Not Covered
1101Not Covered
1110Unreachable
1111CoveredT1,T2,T3

 LINE       371
 SUB-EXPRESSION (gnt_i | missed_err_gnt_q)
                 --1--   --------2-------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT24,T27,T28
10CoveredT1,T2,T3

 LINE       392
 EXPRESSION (tl_i_int.a_valid & reqfifo_wready & ((~error_internal)))
             --------1-------   -------2------   ---------3---------
-1--2--3-StatusTests
011Not Covered
101CoveredT1,T2,T3
110CoveredT24,T27,T28
111CoveredT1,T2,T3

 LINE       394
 EXPRESSION (tl_i_int.a_valid & (tl_i_int.a_opcode inside {PutFullData, PutPartialData}))
             --------1-------   ----------------------------2---------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT24,T27,T28
11CoveredT1,T2,T3

 LINE       395
 EXPRESSION (tl_i_int.a_valid ? tl_i_int.a_address[DataBitWidth+:SramAw] : '0)
             --------1-------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       431
 EXPRESSION ((tl_i_int.a_mask[i] && we_o) ? tl_i_int.a_data[(8 * i)+:8] : '0)
             --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       431
 SUB-EXPRESSION (tl_i_int.a_mask[i] && we_o)
                 ---------1--------    --2-
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT24,T27,T28
11CoveredT1,T2,T3

 LINE       454
 EXPRESSION (((|wmask_intg)) & ((|wdata_intg)))
             -------1-------   -------2-------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       462
 EXPRESSION ((tl_i_int.a_opcode != Get) ? OpWrite : OpRead)
             -------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       462
 SUB-EXPRESSION (tl_i_int.a_opcode != Get)
                -------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       476
 EXPRESSION (sram_ack & ((~we_o)))
             ----1---   ----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11Not Covered

 LINE       479
 EXPRESSION (rvalid_i & reqfifo_rvalid)
             ----1---   -------2------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       535
 EXPRESSION (((reqfifo_rdata.op == OpRead) & ((~reqfifo_rdata.error))) ? reqfifo_rready : 1'b0)
             ----------------------------1----------------------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       535
 SUB-EXPRESSION ((reqfifo_rdata.op == OpRead) & ((~reqfifo_rdata.error)))
                 --------------1-------------   ------------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT24,T27,T28
11Not Covered

 LINE       535
 SUB-EXPRESSION (reqfifo_rdata.op == OpRead)
                --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT24,T27,T28

Branch Coverage for Module : tlul_adapter_sram
Line No.TotalCoveredPercent
Branches 26 21 80.77
TERNARY 144 2 2 100.00
TERNARY 343 2 1 50.00
TERNARY 349 3 1 33.33
TERNARY 395 2 2 100.00
TERNARY 535 2 1 50.00
IF 129 2 2 100.00
IF 283 4 3 75.00
IF 303 3 3 100.00
IF 364 2 2 100.00
IF 428 2 2 100.00
IF 440 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 144 (((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData))) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 343 ((vld_rd_rsp & (~d_error))) ?

Branches:
-1-StatusTests
1 Not Covered
0 Covered T1,T2,T3


LineNo. Expression -1-: 349 ((vld_rd_rsp && reqfifo_rdata.error)) ? -2-: 349 (vld_rd_rsp) ?

Branches:
-1--2-StatusTests
1 - Not Covered
0 1 Not Covered
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 395 (tl_i_int.a_valid) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 535 (((reqfifo_rdata.op == OpRead) & (~reqfifo_rdata.error))) ?

Branches:
-1-StatusTests
1 Not Covered
0 Covered T1,T2,T3


LineNo. Expression -1-: 129 if ((!rst_ni)) -2-: 131 if ((((intg_error || rsp_fifo_error) || sramreqfifo_error) || reqfifo_error))

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Unreachable
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 283 if (reqfifo_rvalid) -2-: 284 if (reqfifo_rdata.error) -3-: 287 if ((reqfifo_rdata.op == OpRead))

Branches:
-1--2--3-StatusTests
1 1 - Covered T24,T27,T28
1 0 1 Not Covered
1 0 0 Covered T1,T2,T3
0 - - Covered T1,T2,T3


LineNo. Expression -1-: 303 if (reqfifo_rvalid) -2-: 304 if ((reqfifo_rdata.op == OpRead))

Branches:
-1--2-StatusTests
1 1 Covered T24,T27,T28
1 0 Covered T1,T2,T3
0 - Covered T1,T2,T3


LineNo. Expression -1-: 364 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 428 if (tl_i_int.a_valid)

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 440 if (tl_i_int.a_valid)

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Module : tlul_adapter_sram
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 13 13 100.00 11 84.62
Cover properties 0 0 0
Cover sequences 0 0 0
Total 13 13 100.00 11 84.62




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AddrOutKnown_A 430386976 430313743 0 0
DataIntgOptions_A 565 565 0 0
ReqOutKnown_A 430386976 430313743 0 0
SramDwHasByteGranularity_A 565 565 0 0
SramDwIsMultipleOfTlulWidth_A 565 565 0 0
TlOutKnownIfFifoKnown_A 430386976 430313743 0 0
TlOutValidKnown_A 430386976 430313743 0 0
WdataOutKnown_A 430386976 430313743 0 0
WeOutKnown_A 430386976 430313743 0 0
WmaskOutKnown_A 430386976 430313743 0 0
adapterNoReadOrWrite 565 565 0 0
rvalidHighReqFifoEmpty 430386976 0 0 0
rvalidHighWhenRspFifoFull 430386976 0 0 0


AddrOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 430386976 430313743 0 0
T1 6412 6343 0 0
T2 252784 252775 0 0
T3 39777 39688 0 0
T4 850311 850212 0 0
T5 65148 65060 0 0
T6 68693 68624 0 0
T7 151781 151707 0 0
T8 93638 93545 0 0
T12 15807 15716 0 0
T31 1860 1788 0 0

DataIntgOptions_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 565 565 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T12 1 1 0 0
T31 1 1 0 0

ReqOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 430386976 430313743 0 0
T1 6412 6343 0 0
T2 252784 252775 0 0
T3 39777 39688 0 0
T4 850311 850212 0 0
T5 65148 65060 0 0
T6 68693 68624 0 0
T7 151781 151707 0 0
T8 93638 93545 0 0
T12 15807 15716 0 0
T31 1860 1788 0 0

SramDwHasByteGranularity_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 565 565 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T12 1 1 0 0
T31 1 1 0 0

SramDwIsMultipleOfTlulWidth_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 565 565 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T12 1 1 0 0
T31 1 1 0 0

TlOutKnownIfFifoKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 430386976 430313743 0 0
T1 6412 6343 0 0
T2 252784 252775 0 0
T3 39777 39688 0 0
T4 850311 850212 0 0
T5 65148 65060 0 0
T6 68693 68624 0 0
T7 151781 151707 0 0
T8 93638 93545 0 0
T12 15807 15716 0 0
T31 1860 1788 0 0

TlOutValidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 430386976 430313743 0 0
T1 6412 6343 0 0
T2 252784 252775 0 0
T3 39777 39688 0 0
T4 850311 850212 0 0
T5 65148 65060 0 0
T6 68693 68624 0 0
T7 151781 151707 0 0
T8 93638 93545 0 0
T12 15807 15716 0 0
T31 1860 1788 0 0

WdataOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 430386976 430313743 0 0
T1 6412 6343 0 0
T2 252784 252775 0 0
T3 39777 39688 0 0
T4 850311 850212 0 0
T5 65148 65060 0 0
T6 68693 68624 0 0
T7 151781 151707 0 0
T8 93638 93545 0 0
T12 15807 15716 0 0
T31 1860 1788 0 0

WeOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 430386976 430313743 0 0
T1 6412 6343 0 0
T2 252784 252775 0 0
T3 39777 39688 0 0
T4 850311 850212 0 0
T5 65148 65060 0 0
T6 68693 68624 0 0
T7 151781 151707 0 0
T8 93638 93545 0 0
T12 15807 15716 0 0
T31 1860 1788 0 0

WmaskOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 430386976 430313743 0 0
T1 6412 6343 0 0
T2 252784 252775 0 0
T3 39777 39688 0 0
T4 850311 850212 0 0
T5 65148 65060 0 0
T6 68693 68624 0 0
T7 151781 151707 0 0
T8 93638 93545 0 0
T12 15807 15716 0 0
T31 1860 1788 0 0

adapterNoReadOrWrite
NameAttemptsReal SuccessesFailuresIncomplete
Total 565 565 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T12 1 1 0 0
T31 1 1 0 0

rvalidHighReqFifoEmpty
NameAttemptsReal SuccessesFailuresIncomplete
Total 430386976 0 0 0

rvalidHighWhenRspFifoFull
NameAttemptsReal SuccessesFailuresIncomplete
Total 430386976 0 0 0

Line Coverage for Instance : tb.dut.u_tlul_adapter
Line No.TotalCoveredPercent
TOTAL696898.55
CONT_ASSIGN10700
CONT_ASSIGN11400
ALWAYS12933100.00
CONT_ASSIGN13811100.00
CONT_ASSIGN14411100.00
CONT_ASSIGN15111100.00
CONT_ASSIGN16211100.00
CONT_ASSIGN17611100.00
CONT_ASSIGN18811100.00
CONT_ASSIGN27411100.00
CONT_ASSIGN27511100.00
CONT_ASSIGN27611100.00
ALWAYS28177100.00
ALWAYS30166100.00
CONT_ASSIGN31511100.00
CONT_ASSIGN31911100.00
CONT_ASSIGN33811100.00
CONT_ASSIGN34311100.00
CONT_ASSIGN34911100.00
CONT_ASSIGN36111100.00
ALWAYS36433100.00
CONT_ASSIGN37111100.00
CONT_ASSIGN39211100.00
CONT_ASSIGN39311100.00
CONT_ASSIGN39411100.00
CONT_ASSIGN39511100.00
ALWAYS42566100.00
ALWAYS43755100.00
CONT_ASSIGN45211100.00
CONT_ASSIGN45311100.00
CONT_ASSIGN45411100.00
CONT_ASSIGN45811100.00
CONT_ASSIGN45911100.00
CONT_ASSIGN46111100.00
CONT_ASSIGN46211100.00
CONT_ASSIGN46911100.00
CONT_ASSIGN47211100.00
CONT_ASSIGN47611100.00
CONT_ASSIGN477100.00
CONT_ASSIGN47911100.00
CONT_ASSIGN48111100.00
CONT_ASSIGN49000
ALWAYS52133100.00
CONT_ASSIGN52711100.00
CONT_ASSIGN53011100.00
CONT_ASSIGN53511100.00
CONT_ASSIGN54000
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
107 unreachable
114 unreachable
129 1 1
130 1 1
131 1 1
132 unreachable
MISSING_ELSE
138 1 1
144 1 1
151 1 1
162 1 1
176 1 1
188 1 1
274 1 1
275 1 1
276 1 1
281 1 1
283 1 1
284 1 1
286 1 1
287 1 1
288 excluded
Exclude Annotation: VC_COV_UNR
291 1 1
294 1 1
301 1 1
303 1 1
304 1 1
305 1 1
307 1 1
310 1 1
315 1 1
319 1 1
338 1 1
343 1 1
349 1 1
361 1 1
364 1 1
365 1 1
367 1 1
371 1 1
392 1 1
393 1 1
394 1 1
395 1 1
425 1 1
426 1 1
428 1 1
429 1 1
430 1 1
431 1 1
MISSING_ELSE
437 1 1
438 1 1
440 1 1
441 1 1
442 1 1
MISSING_ELSE
452 1 1
453 1 1
454 1 1
458 1 1
459 1 1
461 1 1
462 1 1
469 1 1
472 1 1
476 1 1
477 0 1
479 1 1
481 1 1
490 unreachable
521 1 1
522 1 1
523 1 1
527 1 1
530 1 1
535 1 1
540 unreachable


Cond Coverage for Instance : tb.dut.u_tlul_adapter
TotalCoveredPercent
Conditions908695.56
Logical908695.56
Non-Logical00
Event00

 LINE       114
 EXPRESSION (readback_error | readback_error_q)
             -------1------   --------2-------
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10Unreachable

 LINE       131
 EXPRESSION (intg_error || rsp_fifo_error || sramreqfifo_error || reqfifo_error)
             -----1----    -------2------    --------3--------    ------4------
-1--2--3--4-StatusTests
0000CoveredT1,T2,T3
0001Unreachable
0010Unreachable
0100Unreachable
1000Unreachable

 LINE       138
 EXPRESSION (intg_error | rsp_fifo_error | sramreqfifo_error | reqfifo_error | intg_error_q)
             -----1----   -------2------   --------3--------   ------4------   ------5-----
-1--2--3--4--5-StatusTests
00000CoveredT1,T2,T3
00001Not Covered
00010Unreachable
00100Unreachable
01000Unreachable
10000Unreachable

 LINE       144
 EXPRESSION 
 Number  Term
      1  ((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData)) ? (((ByteAccess == 1'b0) ? ((tl_i.a_mask != '1) || (tl_i.a_size != 2'h2)) : 1'b0)) : 1'b0)
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       144
 SUB-EXPRESSION ((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData))
                 ---------------1--------------    ----------------2----------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3

 LINE       144
 SUB-EXPRESSION (tl_i.a_opcode == PutFullData)
                ---------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       144
 SUB-EXPRESSION (tl_i.a_opcode == PutPartialData)
                ----------------1----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       162
 EXPRESSION (tl_i.a_opcode == Get)
            -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       176
 EXPRESSION (wr_attr_error | wr_vld_error | rd_vld_error | instr_error | tlul_error | intg_error)
             ------1------   ------2-----   ------3-----   -----4-----   -----5----   -----6----
-1--2--3--4--5--6-StatusTestsExclude Annotation
000000CoveredT1,T2,T3
000001Unreachable
000010CoveredT1,T2,T3
000100Excluded VC_COV_UNR
001000CoveredT24,T27,T28
010000Unreachable
100000Excluded VC_COV_UNR

 LINE       274
 EXPRESSION (tl_i_int.a_valid & tl_o_int.a_ready)
             --------1-------   --------2-------
-1--2-StatusTests
01CoveredT24,T27,T28
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       275
 EXPRESSION (tl_o_int.d_valid & tl_i_int.d_ready)
             --------1-------   --------2-------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT6,T4,T19
11CoveredT1,T2,T3

 LINE       276
 EXPRESSION (req_o & gnt_i)
             --1--   --2--
-1--2-StatusTestsExclude Annotation
01Excluded VC_COV_UNR
10CoveredT5,T8,T19
11CoveredT1,T2,T3

 LINE       287
 EXPRESSION (reqfifo_rdata.op == OpRead)
            --------------1-------------
-1-StatusTestsExclude Annotation
0CoveredT1,T2,T3
1Excluded VC_COV_UNR

 LINE       304
 EXPRESSION (reqfifo_rdata.op == OpRead)
            --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT24,T27,T28

 LINE       305
 EXPRESSION (rspfifo_rdata.error | reqfifo_rdata.error)
             ---------1---------   ---------2---------
-1--2-StatusTestsExclude Annotation
00Excluded VC_COV_UNR
01CoveredT24,T27,T28
10Excluded VC_COV_UNR

 LINE       315
 EXPRESSION (d_valid & reqfifo_rvalid & rspfifo_rvalid & (reqfifo_rdata.op == OpRead))
             ---1---   -------2------   -------3------   --------------4-------------
-1--2--3--4-StatusTestsExclude Annotation
0111Excluded VC_COV_UNR
1011Excluded VC_COV_UNR
1101CoveredT24,T27,T28
1110Excluded VC_COV_UNR
1111Excluded VC_COV_UNR

 LINE       315
 SUB-EXPRESSION (reqfifo_rdata.op == OpRead)
                --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT24,T27,T28

 LINE       343
 EXPRESSION ((vld_rd_rsp & ((~d_error))) ? rspfifo_rdata.data : error_blanking_data)
             -------------1-------------
-1-StatusTestsExclude Annotation
0CoveredT1,T2,T3
1Excluded VC_COV_UNR

 LINE       343
 SUB-EXPRESSION (vld_rd_rsp & ((~d_error)))
                 -----1----   ------2-----
-1--2-StatusTestsExclude Annotation
01CoveredT1,T2,T3
10Excluded VC_COV_UNR
11Excluded VC_COV_UNR

 LINE       349
 EXPRESSION ((vld_rd_rsp && reqfifo_rdata.error) ? error_blanking_integ : (vld_rd_rsp ? rspfifo_rdata.data_intg : prim_secded_pkg::SecdedInv3932ZeroEcc))
             -----------------1-----------------
-1-StatusTestsExclude Annotation
0CoveredT1,T2,T3
1Excluded VC_COV_UNR

 LINE       349
 SUB-EXPRESSION (vld_rd_rsp && reqfifo_rdata.error)
                 -----1----    ---------2---------
-1--2-StatusTestsExclude Annotation
01CoveredT24,T27,T28
10Excluded VC_COV_UNR
11Excluded VC_COV_UNR

 LINE       349
 SUB-EXPRESSION (vld_rd_rsp ? rspfifo_rdata.data_intg : prim_secded_pkg::SecdedInv3932ZeroEcc)
                 -----1----
-1-StatusTestsExclude Annotation
0CoveredT1,T2,T3
1Excluded VC_COV_UNR

 LINE       361
 EXPRESSION (error_internal & tl_i_int.a_valid & ((~tl_o_int.a_ready)))
             -------1------   --------2-------   ----------3----------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T2,T3
110CoveredT24,T27,T28
111CoveredT24,T27,T28

 LINE       371
 EXPRESSION ((d_valid && (reqfifo_rdata.op != OpRead)) ? AccessAck : AccessAckData)
             --------------------1--------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       371
 SUB-EXPRESSION (d_valid && (reqfifo_rdata.op != OpRead))
                 ---1---    --------------2-------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT24,T27,T28
11CoveredT1,T2,T3

 LINE       371
 SUB-EXPRESSION (reqfifo_rdata.op != OpRead)
                --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       371
 EXPRESSION (d_valid ? reqfifo_rdata.size : '0)
             ---1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       371
 EXPRESSION (d_valid ? reqfifo_rdata.source : '0)
             ---1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       371
 EXPRESSION (d_valid && d_error)
             ---1---    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT24,T27,T28

 LINE       371
 EXPRESSION ((gnt_i | missed_err_gnt_q) & reqfifo_wready & sramreqfifo_wready & sramreqaddrfifo_wready)
             -------------1------------   -------2------   ---------3--------   -----------4----------
-1--2--3--4-StatusTests
0111CoveredT1,T2,T3
1011Not Covered
1101Not Covered
1110Unreachable
1111CoveredT1,T2,T3

 LINE       371
 SUB-EXPRESSION (gnt_i | missed_err_gnt_q)
                 --1--   --------2-------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT24,T27,T28
10CoveredT1,T2,T3

 LINE       392
 EXPRESSION (tl_i_int.a_valid & reqfifo_wready & ((~error_internal)))
             --------1-------   -------2------   ---------3---------
-1--2--3-StatusTestsExclude Annotation
011Excluded VC_COV_UNR
101CoveredT1,T2,T3
110CoveredT24,T27,T28
111CoveredT1,T2,T3

 LINE       394
 EXPRESSION (tl_i_int.a_valid & (tl_i_int.a_opcode inside {PutFullData, PutPartialData}))
             --------1-------   ----------------------------2---------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT24,T27,T28
11CoveredT1,T2,T3

 LINE       395
 EXPRESSION (tl_i_int.a_valid ? tl_i_int.a_address[DataBitWidth+:SramAw] : '0)
             --------1-------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       431
 EXPRESSION ((tl_i_int.a_mask[i] && we_o) ? tl_i_int.a_data[(8 * i)+:8] : '0)
             --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       431
 SUB-EXPRESSION (tl_i_int.a_mask[i] && we_o)
                 ---------1--------    --2-
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT24,T27,T28
11CoveredT1,T2,T3

 LINE       454
 EXPRESSION (((|wmask_intg)) & ((|wdata_intg)))
             -------1-------   -------2-------
-1--2-StatusTestsExclude Annotation
01Excluded vcs_gen_start:i=0:vcs_gen_end:VC_COV_UNR
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       462
 EXPRESSION ((tl_i_int.a_opcode != Get) ? OpWrite : OpRead)
             -------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       462
 SUB-EXPRESSION (tl_i_int.a_opcode != Get)
                -------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       476
 EXPRESSION (sram_ack & ((~we_o)))
             ----1---   ----2----
-1--2-StatusTestsExclude Annotation
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11Excluded VC_COV_UNR

 LINE       479
 EXPRESSION (rvalid_i & reqfifo_rvalid)
             ----1---   -------2------
-1--2-StatusTestsExclude Annotation
01CoveredT1,T2,T3
10Excluded VC_COV_UNR
11Excluded VC_COV_UNR

 LINE       535
 EXPRESSION (((reqfifo_rdata.op == OpRead) & ((~reqfifo_rdata.error))) ? reqfifo_rready : 1'b0)
             ----------------------------1----------------------------
-1-StatusTestsExclude Annotation
0CoveredT1,T2,T3
1Excluded VC_COV_UNR

 LINE       535
 SUB-EXPRESSION ((reqfifo_rdata.op == OpRead) & ((~reqfifo_rdata.error)))
                 --------------1-------------   ------------2-----------
-1--2-StatusTestsExclude Annotation
01CoveredT1,T2,T3
10CoveredT24,T27,T28
11Excluded VC_COV_UNR

 LINE       535
 SUB-EXPRESSION (reqfifo_rdata.op == OpRead)
                --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT24,T27,T28

Branch Coverage for Instance : tb.dut.u_tlul_adapter
Line No.TotalCoveredPercent
Branches 21 21 100.00
TERNARY 144 2 2 100.00
TERNARY 343 1 1 100.00
TERNARY 349 1 1 100.00
TERNARY 395 2 2 100.00
TERNARY 535 1 1 100.00
IF 129 2 2 100.00
IF 283 3 3 100.00
IF 303 3 3 100.00
IF 364 2 2 100.00
IF 428 2 2 100.00
IF 440 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 144 (((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData))) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 343 ((vld_rd_rsp & (~d_error))) ?

Branches:
-1-StatusTestsExclude Annotation
1 Excluded VC_COV_UNR
0 Covered T1,T2,T3


LineNo. Expression -1-: 349 ((vld_rd_rsp && reqfifo_rdata.error)) ? -2-: 349 (vld_rd_rsp) ?

Branches:
-1--2-StatusTestsExclude Annotation
1 - Excluded VC_COV_UNR
0 1 Excluded VC_COV_UNR
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 395 (tl_i_int.a_valid) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 535 (((reqfifo_rdata.op == OpRead) & (~reqfifo_rdata.error))) ?

Branches:
-1-StatusTestsExclude Annotation
1 Excluded VC_COV_UNR
0 Covered T1,T2,T3


LineNo. Expression -1-: 129 if ((!rst_ni)) -2-: 131 if ((((intg_error || rsp_fifo_error) || sramreqfifo_error) || reqfifo_error))

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Unreachable
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 283 if (reqfifo_rvalid) -2-: 284 if (reqfifo_rdata.error) -3-: 287 if ((reqfifo_rdata.op == OpRead))

Branches:
-1--2--3-StatusTestsExclude Annotation
1 1 - Covered T24,T27,T28
1 0 1 Excluded VC_COV_UNR
1 0 0 Covered T1,T2,T3
0 - - Covered T1,T2,T3


LineNo. Expression -1-: 303 if (reqfifo_rvalid) -2-: 304 if ((reqfifo_rdata.op == OpRead))

Branches:
-1--2-StatusTests
1 1 Covered T24,T27,T28
1 0 Covered T1,T2,T3
0 - Covered T1,T2,T3


LineNo. Expression -1-: 364 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 428 if (tl_i_int.a_valid)

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 440 if (tl_i_int.a_valid)

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_tlul_adapter
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 13 13 100.00 11 84.62
Cover properties 0 0 0
Cover sequences 0 0 0
Total 13 13 100.00 11 84.62




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AddrOutKnown_A 430386976 430313743 0 0
DataIntgOptions_A 565 565 0 0
ReqOutKnown_A 430386976 430313743 0 0
SramDwHasByteGranularity_A 565 565 0 0
SramDwIsMultipleOfTlulWidth_A 565 565 0 0
TlOutKnownIfFifoKnown_A 430386976 430313743 0 0
TlOutValidKnown_A 430386976 430313743 0 0
WdataOutKnown_A 430386976 430313743 0 0
WeOutKnown_A 430386976 430313743 0 0
WmaskOutKnown_A 430386976 430313743 0 0
adapterNoReadOrWrite 565 565 0 0
rvalidHighReqFifoEmpty 430386976 0 0 0
rvalidHighWhenRspFifoFull 430386976 0 0 0


AddrOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 430386976 430313743 0 0
T1 6412 6343 0 0
T2 252784 252775 0 0
T3 39777 39688 0 0
T4 850311 850212 0 0
T5 65148 65060 0 0
T6 68693 68624 0 0
T7 151781 151707 0 0
T8 93638 93545 0 0
T12 15807 15716 0 0
T31 1860 1788 0 0

DataIntgOptions_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 565 565 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T12 1 1 0 0
T31 1 1 0 0

ReqOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 430386976 430313743 0 0
T1 6412 6343 0 0
T2 252784 252775 0 0
T3 39777 39688 0 0
T4 850311 850212 0 0
T5 65148 65060 0 0
T6 68693 68624 0 0
T7 151781 151707 0 0
T8 93638 93545 0 0
T12 15807 15716 0 0
T31 1860 1788 0 0

SramDwHasByteGranularity_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 565 565 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T12 1 1 0 0
T31 1 1 0 0

SramDwIsMultipleOfTlulWidth_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 565 565 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T12 1 1 0 0
T31 1 1 0 0

TlOutKnownIfFifoKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 430386976 430313743 0 0
T1 6412 6343 0 0
T2 252784 252775 0 0
T3 39777 39688 0 0
T4 850311 850212 0 0
T5 65148 65060 0 0
T6 68693 68624 0 0
T7 151781 151707 0 0
T8 93638 93545 0 0
T12 15807 15716 0 0
T31 1860 1788 0 0

TlOutValidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 430386976 430313743 0 0
T1 6412 6343 0 0
T2 252784 252775 0 0
T3 39777 39688 0 0
T4 850311 850212 0 0
T5 65148 65060 0 0
T6 68693 68624 0 0
T7 151781 151707 0 0
T8 93638 93545 0 0
T12 15807 15716 0 0
T31 1860 1788 0 0

WdataOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 430386976 430313743 0 0
T1 6412 6343 0 0
T2 252784 252775 0 0
T3 39777 39688 0 0
T4 850311 850212 0 0
T5 65148 65060 0 0
T6 68693 68624 0 0
T7 151781 151707 0 0
T8 93638 93545 0 0
T12 15807 15716 0 0
T31 1860 1788 0 0

WeOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 430386976 430313743 0 0
T1 6412 6343 0 0
T2 252784 252775 0 0
T3 39777 39688 0 0
T4 850311 850212 0 0
T5 65148 65060 0 0
T6 68693 68624 0 0
T7 151781 151707 0 0
T8 93638 93545 0 0
T12 15807 15716 0 0
T31 1860 1788 0 0

WmaskOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 430386976 430313743 0 0
T1 6412 6343 0 0
T2 252784 252775 0 0
T3 39777 39688 0 0
T4 850311 850212 0 0
T5 65148 65060 0 0
T6 68693 68624 0 0
T7 151781 151707 0 0
T8 93638 93545 0 0
T12 15807 15716 0 0
T31 1860 1788 0 0

adapterNoReadOrWrite
NameAttemptsReal SuccessesFailuresIncomplete
Total 565 565 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T12 1 1 0 0
T31 1 1 0 0

rvalidHighReqFifoEmpty
NameAttemptsReal SuccessesFailuresIncomplete
Total 430386976 0 0 0

rvalidHighWhenRspFifoFull
NameAttemptsReal SuccessesFailuresIncomplete
Total 430386976 0 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%