Module Definition
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Module : hmac_csr_assert_fpv
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_hmac_csr_assert_0/hmac_csr_assert_fpv.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.hmac_csr_assert 100.00 100.00



Module Instance : tb.dut.hmac_csr_assert

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
84.84 95.88 84.97 100.00 40.00 88.17 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Since this is the module's only instance, the coverage report is the same as for the module.
Assert Coverage for Module : hmac_csr_assert_fpv
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
TlulOOBAddrErr_A 517591417 1766508 0 0
intr_enable_rd_A 517591417 3236 0 0


TlulOOBAddrErr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 517591417 1766508 0 0
T11 472338 197237 0 0
T12 357032 16509 0 0
T13 0 14174 0 0
T14 0 110710 0 0
T15 0 209396 0 0
T16 0 114825 0 0
T17 0 34584 0 0
T43 0 144955 0 0
T45 0 176543 0 0
T46 0 51628 0 0
T47 32116 0 0 0
T48 7022 0 0 0
T49 294492 0 0 0
T50 5020 0 0 0
T51 258131 0 0 0
T52 2201 0 0 0
T53 5211 0 0 0
T54 381844 0 0 0

intr_enable_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 517591417 3236 0 0
T13 0 27 0 0
T27 188874 14 0 0
T33 141094 0 0 0
T40 0 31 0 0
T55 0 17 0 0
T56 0 27 0 0
T57 0 27 0 0
T58 0 48 0 0
T59 0 34 0 0
T60 0 51 0 0
T61 0 51 0 0
T62 766852 0 0 0
T63 120704 0 0 0
T64 770103 0 0 0
T65 3334 0 0 0
T66 1485 0 0 0
T67 435736 0 0 0
T68 8885 0 0 0
T69 339737 0 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%