Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

34892373

1

T1

8140

T2

39982

T3

9

full_word

34626575

1

T1

6959

T2

34157

T3

4

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	69518518	1			T1	15099		T2	74139		T3	13
auto[TlIntgErrCmd]	139	1			T34	10		T35	3		T36	7
auto[TlIntgErrData]	147	1			T34	9		T35	4		T36	8
auto[TlIntgErrBoth]	144	1			T34	11		T35	3		T36	5

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27786176

1

T1

6287

T2

30094

T3

1

auto[1]

41732772

1

T1

8812

T2

44045

T3

12

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	14442513	1			T1	3215		T2	15120		T18	1
auto[TlIntgErrNone]	partial	auto[1]	20449461	1			T1	4925		T2	24862		T3	9
auto[TlIntgErrNone]	full_word	auto[0]	13343467	1			T1	3072		T2	14974		T3	1
auto[TlIntgErrNone]	full_word	auto[1]	21283077	1			T1	3887		T2	19183		T3	3
auto[TlIntgErrCmd]	partial	auto[0]	53	1			T34	5		T35	2		T36	1
auto[TlIntgErrCmd]	partial	auto[1]	79	1			T34	5		T35	1		T36	6
auto[TlIntgErrCmd]	full_word	auto[0]	1	1			T110	1		-	-		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	6	1			T111	1		T112	1		T38	1
auto[TlIntgErrData]	partial	auto[0]	79	1			T34	8		T35	2		T36	5
auto[TlIntgErrData]	partial	auto[1]	55	1			T34	1		T35	2		T36	2
auto[TlIntgErrData]	full_word	auto[0]	10	1			T36	1		T113	1		T109	2
auto[TlIntgErrData]	full_word	auto[1]	3	1			T109	1		T114	1		T38	1
auto[TlIntgErrBoth]	partial	auto[0]	51	1			T34	3		T35	3		T36	3
auto[TlIntgErrBoth]	partial	auto[1]	82	1			T34	8		T36	2		T107	4
auto[TlIntgErrBoth]	full_word	auto[0]	2	1			T112	1		T110	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	9	1			T108	1		T113	1		T111	3