Unified Coverage Report :: Module :: hmac_csr_assert_fpv

Module : hmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_hmac_csr_assert_0/hmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.hmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.hmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
84.84	95.88	84.97	100.00	40.00	88.17	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : hmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	403738712	1308452	0	0
intr_enable_rd_A	403738712	3382	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403738712	1308452	0	0
T8	0	436667	0	0
T9	0	86816	0	0
T19	361567	153587	0	0
T34	0	12	0	0
T35	0	3	0	0
T41	0	5	0	0
T43	0	10	0	0
T44	0	26	0	0
T45	0	975	0	0
T46	0	536	0	0
T47	953751	0	0	0
T48	388564	0	0	0
T49	40337	0	0	0
T50	63898	0	0	0
T51	73064	0	0	0
T52	104887	0	0	0
T53	11029	0	0	0
T54	119776	0	0	0
T55	14596	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403738712	3382	0	0
T5	957709	19	0	0
T6	32391	0	0	0
T10	13373	0	0	0
T11	773986	101	0	0
T13	367573	0	0	0
T16	1409	0	0	0
T17	1110	0	0	0
T20	0	43	0	0
T25	384403	0	0	0
T26	41302	0	0	0
T37	4213	0	0	0
T56	0	32	0	0
T57	0	23	0	0
T58	0	41	0	0
T59	0	15	0	0
T60	0	9	0	0
T61	0	15	0	0
T62	0	41	0	0