Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

37640387

1

T1

25042

T2

31601

T3

57913

full_word

37143795

1

T1

20925

T2

31694

T3

73700

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	74783742	1			T1	45967		T2	63295		T3	131613
auto[TlIntgErrCmd]	157	1			T38	11		T39	14		T40	9
auto[TlIntgErrData]	135	1			T38	11		T39	4		T40	8
auto[TlIntgErrBoth]	148	1			T38	8		T39	12		T40	3

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

29772409

1

T1

18792

T2

28197

T3

52533

auto[1]

45011773

1

T1

27175

T2

35098

T3

79080

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	15553420	1			T1	9599		T2	14276		T3	35055
auto[TlIntgErrNone]	partial	auto[1]	22086558	1			T1	15443		T2	17325		T3	22858
auto[TlIntgErrNone]	full_word	auto[0]	14218781	1			T1	9193		T2	13921		T3	17478
auto[TlIntgErrNone]	full_word	auto[1]	22924983	1			T1	11732		T2	17773		T3	56222
auto[TlIntgErrCmd]	partial	auto[0]	65	1			T38	4		T39	7		T40	3
auto[TlIntgErrCmd]	partial	auto[1]	81	1			T38	7		T39	7		T40	6
auto[TlIntgErrCmd]	full_word	auto[0]	8	1			T101	1		T105	1		T106	2
auto[TlIntgErrCmd]	full_word	auto[1]	3	1			T100	1		T107	1		T108	1
auto[TlIntgErrData]	partial	auto[0]	64	1			T38	8		T39	1		T40	3
auto[TlIntgErrData]	partial	auto[1]	59	1			T38	1		T39	3		T40	4
auto[TlIntgErrData]	full_word	auto[0]	8	1			T38	1		T40	1		T103	1
auto[TlIntgErrData]	full_word	auto[1]	4	1			T38	1		T100	1		T105	1
auto[TlIntgErrBoth]	partial	auto[0]	59	1			T38	4		T39	5		T109	1
auto[TlIntgErrBoth]	partial	auto[1]	81	1			T38	4		T39	7		T40	3
auto[TlIntgErrBoth]	full_word	auto[0]	4	1			T100	1		T101	1		T107	1
auto[TlIntgErrBoth]	full_word	auto[1]	4	1			T106	1		T103	2		T110	1