Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	128277158	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

134953092

1

T1

2442

T2

70734

T3

49933

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	106645483	1			T1	1994		T2	68189		T3	44613
values[0x0]	73774361	1			T1	1090		T2	37583		T3	29306
values[0x1]	82810406	1			T1	1218		T2	43737		T3	36196

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	96217997	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

167012253

1

T1

2915

T2

89675

T3

66201

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	769423	1			T1	22		T2	582		T3	448
valid_sources[0x01]	821212	1			T1	24		T2	574		T3	393
valid_sources[0x02]	1144026	1			T1	18		T2	576		T3	427
valid_sources[0x03]	767106	1			T1	10		T2	561		T3	426
valid_sources[0x04]	773005	1			T1	10		T2	604		T3	460
valid_sources[0x05]	771081	1			T1	10		T2	585		T3	441
valid_sources[0x06]	1159594	1			T1	19		T2	601		T3	396
valid_sources[0x07]	769646	1			T1	13		T2	555		T3	473
valid_sources[0x08]	766884	1			T1	18		T2	591		T3	427
valid_sources[0x09]	767648	1			T1	14		T2	573		T3	454
valid_sources[0x0a]	771621	1			T1	18		T2	596		T3	395
valid_sources[0x0b]	807500	1			T1	25		T2	607		T3	421
valid_sources[0x0c]	766202	1			T1	16		T2	556		T3	422
valid_sources[0x0d]	774795	1			T1	4		T2	574		T3	455
valid_sources[0x0e]	2071042	1			T1	12		T2	571		T3	383
valid_sources[0x0f]	769580	1			T1	14		T2	587		T3	424
valid_sources[0x10]	799076	1			T1	23		T2	586		T3	392
valid_sources[0x11]	889528	1			T1	16		T2	593		T3	451
valid_sources[0x12]	788745	1			T1	12		T2	537		T3	426
valid_sources[0x13]	1148299	1			T1	18		T2	628		T3	385
valid_sources[0x14]	774373	1			T1	17		T2	570		T3	389
valid_sources[0x15]	2395971	1			T1	8		T2	603		T3	426
valid_sources[0x16]	769372	1			T1	13		T2	607		T3	427
valid_sources[0x17]	6328089	1			T1	12		T2	594		T3	429
valid_sources[0x18]	768201	1			T1	21		T2	587		T3	439
valid_sources[0x19]	774438	1			T1	17		T2	621		T3	451
valid_sources[0x1a]	770757	1			T1	22		T2	632		T3	438
valid_sources[0x1b]	765116	1			T1	20		T2	551		T3	414
valid_sources[0x1c]	774088	1			T1	18		T2	571		T3	452
valid_sources[0x1d]	769232	1			T1	14		T2	574		T3	415
valid_sources[0x1e]	767211	1			T1	9		T2	567		T3	407
valid_sources[0x1f]	808737	1			T1	12		T2	600		T3	424
valid_sources[0x20]	764080	1			T1	18		T2	607		T3	423
valid_sources[0x21]	774517	1			T1	19		T2	642		T3	404
valid_sources[0x22]	766787	1			T1	10		T2	600		T3	484
valid_sources[0x23]	764129	1			T1	8		T2	605		T3	448
valid_sources[0x24]	766930	1			T1	24		T2	581		T3	396
valid_sources[0x25]	788725	1			T1	11		T2	592		T3	431
valid_sources[0x26]	765350	1			T1	20		T2	570		T3	470
valid_sources[0x27]	763084	1			T1	21		T2	596		T3	418
valid_sources[0x28]	768641	1			T1	21		T2	575		T3	464
valid_sources[0x29]	787288	1			T1	17		T2	595		T3	395
valid_sources[0x2a]	769767	1			T1	20		T2	603		T3	472
valid_sources[0x2b]	769978	1			T1	10		T2	562		T3	455
valid_sources[0x2c]	824415	1			T1	17		T2	610		T3	387
valid_sources[0x2d]	768842	1			T1	7		T2	595		T3	413
valid_sources[0x2e]	860709	1			T1	18		T2	585		T3	429
valid_sources[0x2f]	844096	1			T1	16		T2	613		T3	466
valid_sources[0x30]	767333	1			T1	29		T2	593		T3	451
valid_sources[0x31]	772209	1			T1	18		T2	566		T3	400
valid_sources[0x32]	774709	1			T1	12		T2	562		T3	402
valid_sources[0x33]	796922	1			T1	15		T2	566		T3	434
valid_sources[0x34]	821565	1			T1	19		T2	600		T3	446
valid_sources[0x35]	801870	1			T1	8		T2	592		T3	438
valid_sources[0x36]	792177	1			T1	17		T2	596		T3	427
valid_sources[0x37]	2348508	1			T1	13		T2	630		T3	440
valid_sources[0x38]	766864	1			T1	20		T2	576		T3	426
valid_sources[0x39]	767047	1			T1	13		T2	593		T3	385
valid_sources[0x3a]	788877	1			T1	16		T2	567		T3	429
valid_sources[0x3b]	2484596	1			T1	10		T2	600		T3	406
valid_sources[0x3c]	766723	1			T1	18		T2	572		T3	389
valid_sources[0x3d]	778020	1			T1	20		T2	593		T3	457
valid_sources[0x3e]	2079600	1			T1	22		T2	577		T3	463
valid_sources[0x3f]	2387877	1			T1	29		T2	524		T3	441
valid_sources[0x40]	823089	1			T1	27		T2	570		T3	407
valid_sources[0x41]	1182573	1			T1	12		T2	579		T3	442
valid_sources[0x42]	764298	1			T1	23		T2	599		T3	449
valid_sources[0x43]	843800	1			T1	6		T2	587		T3	440
valid_sources[0x44]	832162	1			T1	10		T2	588		T3	434
valid_sources[0x45]	767951	1			T1	17		T2	550		T3	406
valid_sources[0x46]	768732	1			T1	14		T2	546		T3	423
valid_sources[0x47]	765000	1			T1	21		T2	596		T3	396
valid_sources[0x48]	763202	1			T1	15		T2	565		T3	416
valid_sources[0x49]	864107	1			T1	15		T2	587		T3	435
valid_sources[0x4a]	780263	1			T1	20		T2	589		T3	450
valid_sources[0x4b]	2566844	1			T1	21		T2	613		T3	458
valid_sources[0x4c]	767844	1			T1	17		T2	596		T3	438
valid_sources[0x4d]	767056	1			T1	20		T2	542		T3	448
valid_sources[0x4e]	3756704	1			T1	19		T2	601		T3	502
valid_sources[0x4f]	823089	1			T1	19		T2	597		T3	421
valid_sources[0x50]	839222	1			T1	14		T2	567		T3	425
valid_sources[0x51]	761685	1			T1	13		T2	560		T3	443
valid_sources[0x52]	769383	1			T1	11		T2	579		T3	434
valid_sources[0x53]	807657	1			T1	12		T2	581		T3	436
valid_sources[0x54]	769665	1			T1	24		T2	604		T3	448
valid_sources[0x55]	2252011	1			T1	22		T2	553		T3	416
valid_sources[0x56]	829843	1			T1	16		T2	577		T3	433
valid_sources[0x57]	768846	1			T1	15		T2	634		T3	422
valid_sources[0x58]	798113	1			T1	20		T2	589		T3	401
valid_sources[0x59]	1152783	1			T1	9		T2	613		T3	412
valid_sources[0x5a]	769061	1			T1	23		T2	629		T3	428
valid_sources[0x5b]	824333	1			T1	11		T2	587		T3	518
valid_sources[0x5c]	1169426	1			T1	10		T2	612		T3	416
valid_sources[0x5d]	776359	1			T1	21		T2	559		T3	446
valid_sources[0x5e]	811742	1			T1	17		T2	574		T3	403
valid_sources[0x5f]	772582	1			T1	16		T2	572		T3	458
valid_sources[0x60]	802484	1			T1	19		T2	633		T3	426
valid_sources[0x61]	2546189	1			T1	19		T2	559		T3	411
valid_sources[0x62]	854397	1			T1	9		T2	585		T3	427
valid_sources[0x63]	765548	1			T1	18		T2	590		T3	454
valid_sources[0x64]	771632	1			T1	13		T2	580		T3	434
valid_sources[0x65]	853786	1			T1	16		T2	575		T3	436
valid_sources[0x66]	770698	1			T1	19		T2	574		T3	379
valid_sources[0x67]	769782	1			T1	19		T2	572		T3	420
valid_sources[0x68]	2176737	1			T1	27		T2	600		T3	482
valid_sources[0x69]	986394	1			T1	5		T2	600		T3	400
valid_sources[0x6a]	861695	1			T1	15		T2	574		T3	444
valid_sources[0x6b]	768672	1			T1	16		T2	600		T3	416
valid_sources[0x6c]	770238	1			T1	21		T2	577		T3	410
valid_sources[0x6d]	768456	1			T1	13		T2	609		T3	422
valid_sources[0x6e]	767301	1			T1	22		T2	580		T3	489
valid_sources[0x6f]	817327	1			T1	16		T2	587		T3	436
valid_sources[0x70]	2425190	1			T1	9		T2	590		T3	438
valid_sources[0x71]	779801	1			T1	14		T2	597		T3	454
valid_sources[0x72]	768492	1			T1	19		T2	596		T3	409
valid_sources[0x73]	771393	1			T1	14		T2	585		T3	467
valid_sources[0x74]	766490	1			T1	14		T2	586		T3	471
valid_sources[0x75]	789423	1			T1	17		T2	528		T3	410
valid_sources[0x76]	1235167	1			T1	22		T2	561		T3	417
valid_sources[0x77]	766705	1			T1	11		T2	599		T3	467
valid_sources[0x78]	770908	1			T1	15		T2	580		T3	415
valid_sources[0x79]	764184	1			T1	19		T2	591		T3	443
valid_sources[0x7a]	763890	1			T1	25		T2	590		T3	413
valid_sources[0x7b]	812849	1			T1	13		T2	590		T3	406
valid_sources[0x7c]	807014	1			T1	13		T2	576		T3	419
valid_sources[0x7d]	2384703	1			T1	17		T2	576		T3	418
valid_sources[0x7e]	767671	1			T1	9		T2	543		T3	443
valid_sources[0x7f]	2786742	1			T1	21		T2	587		T3	437
valid_sources[0x80]	775306	1			T1	19		T2	557		T3	451

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

53012530

1

T1

958

T2

34248

T3

21850

values[0x0]

all_enables

biggest_size

43477106

1

T1

768

T2

19656

T3

15008

values[0x1]

all_enables

biggest_size

38463456

1

T1

716

T2

16830

T3

13075