Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

128408393

1

T1

1860

T2

78775

T3

60182

full_word

134961608

1

T1

2442

T2

70734

T3

49933

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	263369611	1			T1	4302		T2	149509		T3	110115
auto[TlIntgErrCmd]	130	1			T60	12		T63	11		T64	5
auto[TlIntgErrData]	132	1			T60	4		T63	5		T64	5
auto[TlIntgErrBoth]	128	1			T60	14		T63	4		T151	6

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

106691172

1

T1

1994

T2

68189

T3

44613

auto[1]

156678829

1

T1

2308

T2

81320

T3

65502

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	53675019	1			T1	1036		T2	33941		T3	22763
auto[TlIntgErrNone]	partial	auto[1]	74733032	1			T1	824		T2	44834		T3	37419
auto[TlIntgErrNone]	full_word	auto[0]	53015984	1			T1	958		T2	34248		T3	21850
auto[TlIntgErrNone]	full_word	auto[1]	81945576	1			T1	1484		T2	36486		T3	28083
auto[TlIntgErrCmd]	partial	auto[0]	53	1			T60	7		T63	4		T64	1
auto[TlIntgErrCmd]	partial	auto[1]	61	1			T60	4		T63	4		T64	4
auto[TlIntgErrCmd]	full_word	auto[0]	7	1			T60	1		T63	1		T154	1
auto[TlIntgErrCmd]	full_word	auto[1]	9	1			T63	2		T73	1		T153	1
auto[TlIntgErrData]	partial	auto[0]	53	1			T60	1		T64	2		T151	1
auto[TlIntgErrData]	partial	auto[1]	63	1			T60	2		T63	3		T64	3
auto[TlIntgErrData]	full_word	auto[0]	6	1			T60	1		T63	1		T155	2
auto[TlIntgErrData]	full_word	auto[1]	10	1			T63	1		T151	3		T156	1
auto[TlIntgErrBoth]	partial	auto[0]	48	1			T60	7		T63	2		T151	2
auto[TlIntgErrBoth]	partial	auto[1]	64	1			T60	6		T63	1		T151	2
auto[TlIntgErrBoth]	full_word	auto[0]	2	1			T63	1		T156	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	14	1			T60	1		T151	2		T73	2