Unified Coverage Report :: Module :: hmac_csr_assert_fpv

Module : hmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_hmac_csr_assert_0/hmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.hmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.hmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.42	100.00	93.75	100.00	100.00	96.77	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : hmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1537189593	74167	0	0
intr_enable_rd_A	1537189593	2949	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1537189593	74167	0	0
T14	157896	59774	0	0
T47	0	10	0	0
T48	0	13	0	0
T60	0	5	0	0
T61	0	510	0	0
T62	0	739	0	0
T65	0	25	0	0
T68	0	12	0	0
T74	0	5	0	0
T75	0	7	0	0
T76	19696	0	0	0
T77	1209	0	0	0
T78	1442	0	0	0
T79	141711	0	0	0
T80	262493	0	0	0
T81	1119	0	0	0
T82	105203	0	0	0
T83	55855	0	0	0
T84	175263	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1537189593	2949	0	0
T85	168004	6	0	0
T86	0	26	0	0
T87	0	26	0	0
T88	0	9	0	0
T89	0	22	0	0
T90	0	7	0	0
T91	0	34	0	0
T92	0	34	0	0
T93	0	17	0	0
T94	0	398	0	0
T95	103377	0	0	0
T96	644922	0	0	0
T97	428676	0	0	0
T98	57531	0	0	0
T99	70658	0	0	0
T100	92059	0	0	0
T101	323149	0	0	0
T102	1246	0	0	0
T103	137643	0	0	0