Unified Coverage Report :: Module :: hmac_csr_assert_fpv

Module : hmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_hmac_csr_assert_0/hmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.hmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.hmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.44	100.00	93.85	100.00	100.00	96.77	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : hmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	448354292	2282790	0	0
intr_enable_rd_A	448354292	3377	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	448354292	2282790	0	0
T7	582626	97835	0	0
T8	0	273368	0	0
T9	0	233426	0	0
T14	0	84702	0	0
T15	0	81686	0	0
T20	79917	0	0	0
T22	0	202523	0	0
T23	0	399492	0	0
T30	0	131875	0	0
T49	259562	0	0	0
T50	45783	0	0	0
T56	7873	0	0	0
T61	1119	0	0	0
T62	382888	0	0	0
T73	0	114294	0	0
T74	0	214609	0	0
T75	182690	0	0	0
T76	426154	0	0	0
T77	115741	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	448354292	3377	0	0
T7	582626	160	0	0
T14	0	71	0	0
T20	79917	0	0	0
T49	259562	0	0	0
T50	45783	0	0	0
T56	7873	0	0	0
T61	1119	0	0	0
T62	382888	0	0	0
T75	182690	0	0	0
T76	426154	0	0	0
T77	115741	0	0	0
T78	0	32	0	0
T79	0	81	0	0
T80	0	4	0	0
T81	0	68	0	0
T82	0	28	0	0
T83	0	53	0	0
T84	0	62	0	0
T85	0	21	0	0