Unified Coverage Report :: Module :: hmac

Module : hmac

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.93	100.00	90.81	100.00	100.00	96.77	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_hmac_0.1/rtl/hmac.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut	98.44	100.00	93.85	100.00	100.00	96.77	100.00

---

Module Instance : tb.dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.44	100.00	93.85	100.00	100.00	96.77	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.87	95.95	94.29	100.00	87.18	92.33	99.49

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_alert_tx[0].u_prim_alert_sender	100.00			100.00
hmac_csr_assert	100.00						100.00
intr_hw_fifo_empty	100.00	100.00	100.00			100.00	100.00
intr_hw_hmac_done	100.00	100.00	100.00			100.00	100.00
intr_hw_hmac_err	100.00	100.00	100.00			100.00	100.00
tlul_assert_device	100.00	100.00				100.00	100.00
u_hmac	96.68	99.41	93.90		100.00	93.41
u_msg_fifo	100.00	100.00	100.00			100.00	100.00
u_packer	100.00	100.00	100.00			100.00	100.00
u_prim_sha2_512	87.82	94.62	89.47		80.00	87.18
u_reg	98.23	94.86	97.60	100.00		98.72	100.00
u_tlul_adapter	88.64	94.12	87.32			80.25	92.86

Line Coverage for Module : hmac

	Line No.	Total	Covered	Percent
TOTAL		198	198	100.00
CONT_ASSIGN	135	1	1	100.00
CONT_ASSIGN	136	1	1	100.00
CONT_ASSIGN	137	1	1	100.00
CONT_ASSIGN	138	1	1	100.00
ALWAYS	150	15	15	100.00
ALWAYS	192	3	3	100.00
CONT_ASSIGN	199	1	1	100.00
CONT_ASSIGN	200	1	1	100.00
ALWAYS	204	7	7	100.00
ALWAYS	219	3	3	100.00
ALWAYS	231	19	19	100.00
CONT_ASSIGN	277	1	1	100.00
CONT_ASSIGN	282	1	1	100.00
CONT_ASSIGN	283	1	1	100.00
CONT_ASSIGN	285	1	1	100.00
ALWAYS	287	5	5	100.00
CONT_ASSIGN	301	1	1	100.00
ALWAYS	304	3	3	100.00
CONT_ASSIGN	308	1	1	100.00
ALWAYS	310	7	7	100.00
CONT_ASSIGN	325	1	1	100.00
CONT_ASSIGN	326	1	1	100.00
CONT_ASSIGN	327	1	1	100.00
CONT_ASSIGN	329	1	1	100.00
CONT_ASSIGN	330	1	1	100.00
CONT_ASSIGN	331	1	1	100.00
CONT_ASSIGN	332	1	1	100.00
CONT_ASSIGN	333	1	1	100.00
CONT_ASSIGN	334	1	1	100.00
CONT_ASSIGN	335	1	1	100.00
CONT_ASSIGN	337	1	1	100.00
CONT_ASSIGN	338	1	1	100.00
CONT_ASSIGN	339	1	1	100.00
CONT_ASSIGN	340	1	1	100.00
CONT_ASSIGN	343	1	1	100.00
CONT_ASSIGN	344	1	1	100.00
CONT_ASSIGN	349	1	1	100.00
CONT_ASSIGN	350	1	1	100.00
CONT_ASSIGN	351	1	1	100.00
CONT_ASSIGN	352	1	1	100.00
ALWAYS	355	6	6	100.00
ALWAYS	365	4	4	100.00
ALWAYS	404	6	6	100.00
CONT_ASSIGN	454	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	462	1	1	100.00
CONT_ASSIGN	470	1	1	100.00
CONT_ASSIGN	472	1	1	100.00
ALWAYS	475	7	7	100.00
CONT_ASSIGN	518	1	1	100.00
CONT_ASSIGN	521	1	1	100.00
CONT_ASSIGN	527	1	1	100.00
CONT_ASSIGN	532	1	1	100.00
CONT_ASSIGN	533	1	1	100.00
CONT_ASSIGN	535	1	1	100.00
CONT_ASSIGN	536	1	1	100.00
CONT_ASSIGN	537	1	1	100.00
ALWAYS	542	9	9	100.00
CONT_ASSIGN	617	1	1	100.00
ALWAYS	622	3	3	100.00
ALWAYS	630	3	3	100.00
ALWAYS	635	10	10	100.00
CONT_ASSIGN	652	1	1	100.00
CONT_ASSIGN	653	1	1	100.00
CONT_ASSIGN	660	1	1	100.00
CONT_ASSIGN	661	1	1	100.00
CONT_ASSIGN	771	1	1	100.00
CONT_ASSIGN	800	1	1	100.00
CONT_ASSIGN	801	1	1	100.00
CONT_ASSIGN	802	1	1	100.00
CONT_ASSIGN	807	1	1	100.00
CONT_ASSIGN	812	1	1	100.00
ALWAYS	815	6	6	100.00
CONT_ASSIGN	831	1	1	100.00
ALWAYS	837	7	7	100.00
CONT_ASSIGN	880	1	1	100.00
CONT_ASSIGN	884	1	1	100.00
ALWAYS	886	3	3	100.00
CONT_ASSIGN	892	1	1	100.00
ALWAYS	914	6	6	100.00
ALWAYS	921	6	6	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_hmac_0.1/rtl/hmac.sv' or '../src/lowrisc_ip_hmac_0.1/rtl/hmac.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
135	1	1
136	1	1
137	1	1
138	1	1
150	1	1
151	1	1
153	1	1
155	1	1
157	1	1
158	1	1
160	1	1
			MISSING_ELSE
165	1	1
166	1	1
167	1	1
			MISSING_ELSE
172	1	1
176	1	1
			MISSING_ELSE
181	1	1
182	1	1
183	1	1
			==> MISSING_ELSE
192	1	1
193	1	1
195	1	1
199	1	1
200	1	1
204	1	1
205	1	1
206	1	1
207	1	1
209	1	1
210	1	1
212	1	1
			MISSING_ELSE
			MISSING_ELSE
219	2	2
220	1	1
231	1	1
232	1	1
234	1	1
236	1	1
240	1	1
242	1	1
243	1	1
244	1	1
246	1	1
249	1	1
252	1	1
			MISSING_ELSE
256	1	1
257	1	1
261	1	1
262	1	1
266	1	1
267	1	1
270	1	1
271	1	1
277	1	1
282	1	1
283	1	1
285	1	1
287	1	1
289	1	1
290	1	1
291	1	1
292	1	1
301	1	1
304	2	2
305	1	1
308	1	1
310	1	1
312	1	1
313	1	1
314	1	1
315	1	1
316	1	1
317	1	1
325	1	1
326	1	1
327	1	1
329	1	1
330	1	1
331	1	1
332	1	1
333	1	1
334	1	1
335	1	1
337	1	1
338	1	1
339	1	1
340	1	1
343	1	1
344	1	1
349	1	1
350	1	1
351	1	1
352	1	1
355	1	1
356	1	1
357	1	1
358	1	1
359	1	1
360	1	1
			MISSING_ELSE
365	1	1
366	1	1
397	1	1
398	1	1
			MISSING_ELSE
404	1	1
405	1	1
406	1	1
407	1	1
408	1	1
409	1	1
			MISSING_ELSE
454	1	1
455	1	1
462	1	1
470	1	1
472	1	1
475	1	1
476	1	1
477	1	1
478	1	1
480	1	1
481	1	1
482	1	1
518	1	1
521	1	1
527	1	1
532	1	1
533	1	1
535	1	1
536	1	1
537	1	1
542	1	1
543	1	1
545	1	1
546	1	1
547	1	1
549	1	1
550	1	1
552	1	1
553	1	1
			==> MISSING_ELSE
			MISSING_ELSE
617	1	1
622	1	1
623	1	1
624	1	1
630	2	2
631	1	1
635	1	1
636	1	1
637	1	1
638	1	1
			MISSING_ELSE
640	1	1
641	1	1
			MISSING_ELSE
			MISSING_ELSE
645	1	1
646	1	1
647	1	1
648	1	1
			MISSING_ELSE
652	1	1
653	1	1
660	1	1
661	1	1
771	1	1
800	1	1
801	1	1
802	1	1
807	1	1
812	1	1
815	1	1
816	1	1
817	1	1
818	1	1
819	1	1
			MISSING_ELSE
823	1	1
831	1	1
837	1	1
839	1	1
842	1	1
846	1	1
850	1	1
854	1	1
858	1	1
880	1	1
884	1	1
886	1	1
887	1	1
889	1	1
892	1	1
914	2	2
915	2	2
916	2	2
			MISSING_ELSE
921	2	2
922	2	2
923	2	2
			MISSING_ELSE

---

Cond Coverage for Module : hmac

	Total	Covered	Percent
Conditions	185	168	90.81
Logical	185	168	90.81
Non-Logical	0	0
Event	0	0

 LINE       240
 EXPRESSION (digest_size == SHA2_256)
            ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       244
 EXPRESSION ((digest_size == SHA2_384) || (digest_size == SHA2_512))
             ------------1------------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       244
 SUB-EXPRESSION (digest_size == SHA2_384)
                ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       244
 SUB-EXPRESSION (digest_size == SHA2_512)
                ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       246
 EXPRESSION (reg2hw.digest[(2 * i)].qe ? prim_sha2_pkg::conv_endian32(reg2hw.digest[(2 * i)].q, digest_swap) : digest[i][63:32])
             ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       249
 EXPRESSION (reg2hw.digest[((2 * i) + 1)].qe ? prim_sha2_pkg::conv_endian32(reg2hw.digest[((2 * i) + 1)].q, digest_swap) : digest[i][31:0])
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       252
 EXPRESSION (reg2hw.digest[(2 * i)].qe | reg2hw.digest[((2 * i) + 1)].qe)
             ------------1------------   ---------------2---------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T3,T4

 LINE       256
 EXPRESSION (digest_size_started_q == SHA2_256)
            -----------------1-----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T5

 LINE       262
 EXPRESSION ((digest_size_started_q == SHA2_384) || (digest_size_started_q == SHA2_512))
             -----------------1-----------------    -----------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T5
1	0	Covered	T2,T3,T6

 LINE       262
 SUB-EXPRESSION (digest_size_started_q == SHA2_384)
                -----------------1-----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T6

 LINE       262
 SUB-EXPRESSION (digest_size_started_q == SHA2_512)
                -----------------1-----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T5

 LINE       301
 EXPRESSION (hash_start_or_continue ? digest_size : digest_size_started_q)
             -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T5

 LINE       337
 EXPRESSION (reg2hw.cmd.hash_start.qe & reg2hw.cmd.hash_start.q)
             ------------1-----------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T5
1	1	Covered	T1,T2,T3

 LINE       338
 EXPRESSION (reg2hw.cmd.hash_stop.qe & reg2hw.cmd.hash_stop.q)
             -----------1-----------   -----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T4

 LINE       339
 EXPRESSION (reg2hw.cmd.hash_continue.qe & reg2hw.cmd.hash_continue.q)
             -------------1-------------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T4

 LINE       340
 EXPRESSION (reg2hw.cmd.hash_process.qe & reg2hw.cmd.hash_process.q)
             -------------1------------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T5

 LINE       349
 EXPRESSION (reg_hash_start & sha_en & ((~cfg_block)) & ((~invalid_config)))
             -------1------   ---2--   -------3------   ---------4---------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Covered	T1,T2,T3
1	0	1	1	Covered	T3,T27,T53
1	1	0	1	Covered	T3,T27,T7
1	1	1	0	Covered	T1,T2,T3
1	1	1	1	Covered	T2,T3,T5

 LINE       350
 EXPRESSION (reg_hash_continue & sha_en & ((~cfg_block)) & ((~invalid_config)))
             --------1--------   ---2--   -------3------   ---------4---------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Covered	T1,T2,T3
1	0	1	1	Not Covered
1	1	0	1	Not Covered
1	1	1	0	Not Covered
1	1	1	1	Covered	T2,T3,T4

 LINE       351
 EXPRESSION (reg_hash_process & sha_en & cfg_block & ((~invalid_config)))
             --------1-------   ---2--   ----3----   ---------4---------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Covered	T2,T3,T5
1	0	1	1	Not Covered
1	1	0	1	Not Covered
1	1	1	0	Not Covered
1	1	1	1	Covered	T2,T3,T5

 LINE       352
 EXPRESSION (hash_start | hash_continue)
             -----1----   ------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T3,T5

 LINE       359
 EXPRESSION (reg_hash_done || reg_hash_stop)
             ------1------    ------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T3,T5

 LINE       397
 EXPRESSION (((!cfg_block)) && reg2hw.cfg.hmac_en.qe)
             -------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T3,T27,T53
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       454
 EXPRESSION (fifo_empty_q & ((~fifo_empty)))
             ------1-----   -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T5

 LINE       455
 EXPRESSION (((~fifo_full_q)) & fifo_full)
             --------1-------   ----2----

-1-	-2-	Status	Tests
0	1	Covered	T3,T25,T11
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       462
 EXPRESSION 
 Number  Term
      1  (reg_hash_start || reg_hash_continue || reg_hash_process || reg_hash_stop) ? 1'b0 : (fifo_empty_negedge ? 1'b0 : (fifo_full_posedge ? 1'b1 : fifo_full_seen_q)))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       462
 SUB-EXPRESSION (reg_hash_start || reg_hash_continue || reg_hash_process || reg_hash_stop)
                 -------1------    --------2--------    --------3-------    ------4------

-1-	-2-	-3-	-4-	Status	Tests
0	0	0	0	Covered	T1,T2,T3
0	0	0	1	Covered	T2,T3,T4
0	0	1	0	Covered	T2,T3,T5
0	1	0	0	Covered	T2,T3,T4
1	0	0	0	Covered	T1,T2,T3

 LINE       462
 SUB-EXPRESSION (fifo_empty_negedge ? 1'b0 : (fifo_full_posedge ? 1'b1 : fifo_full_seen_q))
                 ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T5

 LINE       462
 SUB-EXPRESSION (fifo_full_posedge ? 1'b1 : fifo_full_seen_q)
                 --------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       470
 EXPRESSION (((~msg_allowed)) || ((~fifo_full_seen_q)))
             --------1-------    ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T3,T25,T11
0	1	Covered	T2,T3,T5
1	0	Covered	T1,T2,T3

 LINE       472
 EXPRESSION (fifo_empty_gate ? 1'b0 : fifo_empty)
             -------1-------

-1-	Status	Tests
0	Covered	T3,T25,T11
1	Covered	T1,T2,T3

 LINE       518
 EXPRESSION (msg_fifo_req & ((~msg_fifo_we)))
             ------1-----   --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       521
 EXPRESSION (msg_fifo_req & ((~hmac_fifo_wsel)) & packer_ready)
             ------1-----   ---------2---------   ------3-----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Unreachable	T11,T12,T13
1	1	1	Covered	T1,T2,T3

 LINE       537
 EXPRESSION ((hmac_fifo_wsel && fifo_wready) ? hmac_fifo_wvalid : reg_fifo_wvalid)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T5

 LINE       537
 SUB-EXPRESSION (hmac_fifo_wsel && fifo_wready)
                 -------1------    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T5

 LINE       547
 EXPRESSION (digest_size == SHA2_256)
            ------------1------------

-1-	Status	Tests
0	Covered	T2,T3,T5
1	Covered	T2,T3,T5

 LINE       550
 EXPRESSION ((digest_size == SHA2_384) || (digest_size == SHA2_512))
             ------------1------------    ------------2------------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Covered	T2,T3,T5
1	0	Covered	T2,T3,T6

 LINE       550
 SUB-EXPRESSION (digest_size == SHA2_384)
                ------------1------------

-1-	Status	Tests
0	Covered	T2,T3,T5
1	Covered	T2,T3,T6

 LINE       550
 SUB-EXPRESSION (digest_size == SHA2_512)
                ------------1------------

-1-	Status	Tests
0	Covered	T2,T3,T6
1	Covered	T2,T3,T5

 LINE       564
 EXPRESSION (fifo_wvalid & sha_en)
             -----1-----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T5

 LINE       617
 EXPRESSION (msg_fifo_req & msg_fifo_we & ((~hmac_fifo_wsel)) & msg_allowed)
             ------1-----   -----2-----   ---------3---------   -----4-----

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Covered	T2,T3,T5
1	0	1	1	Not Covered
1	1	0	1	Not Covered
1	1	1	0	Covered	T1,T2,T3
1	1	1	1	Covered	T2,T3,T5

 LINE       647
 EXPRESSION (msg_write && sha_en && packer_ready)
             ----1----    ---2--    ------3-----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Unreachable	T11,T12,T13
1	1	1	Covered	T2,T3,T5

 LINE       667
 EXPRESSION (msg_write & sha_en)
             ----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T5

 LINE       667
 EXPRESSION (fifo_wready & ((~hmac_fifo_wsel)))
             -----1-----   ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T5
1	1	Covered	T1,T2,T3

 LINE       771
 SUB-EXPRESSION (reg2hw.alert_test.q & reg2hw.alert_test.qe)
                 ---------1---------   ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T17,T54,T55
1	0	Covered	T1,T2,T3
1	1	Covered	T17,T54,T55

 LINE       800
 EXPRESSION ((reg_hash_start | reg_hash_continue) & ((~sha_en)))
             ------------------1-----------------   -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T27,T53

 LINE       800
 SUB-EXPRESSION (reg_hash_start | reg_hash_continue)
                 -------1------   --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3

 LINE       801
 EXPRESSION ((reg_hash_start | reg_hash_continue) & cfg_block)
             ------------------1-----------------   ----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T27,T7

 LINE       801
 SUB-EXPRESSION (reg_hash_start | reg_hash_continue)
                 -------1------   --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3

 LINE       802
 EXPRESSION (msg_fifo_req & ((~msg_allowed)))
             ------1-----   --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T5
1	1	Covered	T1,T2,T3

 LINE       807
 EXPRESSION ((digest_size == SHA2_None) | ((key_length == Key_None) && hmac_en) | ((key_length == Key_1024) && (digest_size == SHA2_256) && hmac_en))
             -------------1------------   ------------------2------------------   ---------------------------------3--------------------------------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T3,T4,T24
0	1	0	Covered	T1,T2,T3
1	0	0	Covered	T1,T2,T3

 LINE       807
 SUB-EXPRESSION (digest_size == SHA2_None)
                -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       807
 SUB-EXPRESSION ((key_length == Key_None) && hmac_en)
                 ------------1-----------    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       807
 SUB-EXPRESSION (key_length == Key_None)
                ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       807
 SUB-EXPRESSION ((key_length == Key_1024) && (digest_size == SHA2_256) && hmac_en)
                 ------------1-----------    ------------2------------    ---3---

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T3,T6
1	1	0	Covered	T3,T6,T24
1	1	1	Covered	T3,T4,T24

 LINE       807
 SUB-EXPRESSION (key_length == Key_1024)
                ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       807
 SUB-EXPRESSION (digest_size == SHA2_256)
                ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       812
 EXPRESSION ((reg_hash_start || reg_hash_continue) & invalid_config)
             ------------------1------------------   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T5
1	1	Covered	T1,T2,T3

 LINE       812
 SUB-EXPRESSION (reg_hash_start || reg_hash_continue)
                 -------1------    --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3

 LINE       831
 EXPRESSION 
 Number  Term
      1  ((~reg2hw.intr_state.hmac_err.q)) & 
      2  (hash_start_sha_disabled | update_seckey_inprocess | hash_start_active | msg_push_not_allowed | invalid_config_atstart))

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       831
 SUB-EXPRESSION (hash_start_sha_disabled | update_seckey_inprocess | hash_start_active | msg_push_not_allowed | invalid_config_atstart)
                 -----------1-----------   -----------2-----------   --------3--------   ----------4---------   -----------5----------

-1-	-2-	-3-	-4-	-5-	Status	Tests
0	0	0	0	0	Covered	T1,T2,T3
0	0	0	0	1	Covered	T1,T2,T3
0	0	0	1	0	Covered	T1,T2,T3
0	0	1	0	0	Covered	T3,T27,T7
0	1	0	0	0	Covered	T3,T27,T53
1	0	0	0	0	Covered	T3,T27,T53

 LINE       880
 EXPRESSION (((!reg_fifo_wvalid)) && ((!fifo_rvalid)) && hmac_core_idle && sha_core_idle)
             ----------1---------    --------2-------    -------3------    ------4------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Not Covered
1	0	1	1	Not Covered
1	1	0	1	Covered	T2,T3,T5
1	1	1	0	Covered	T2,T3,T6
1	1	1	1	Covered	T1,T2,T3

 LINE       915
 EXPRESSION (hash_process || reg_hash_stop)
             ------1-----    ------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T3,T5

 LINE       923
 EXPRESSION (hash_process || reg_hash_stop)
             ------1-----    ------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T3,T5

---

Toggle Coverage for Module : hmac

	Total	Covered	Percent
Totals	30	30	100.00
Total Bits	346	346	100.00
Total Bits 0->1	173	173	100.00
Total Bits 1->0	173	173	100.00

Ports	30	30	100.00
Port Bits	346	346	100.00
Port Bits 0->1	173	173	100.00
Port Bits 1->0	173	173	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T3,T25,T7	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T3,T10,T6	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T2,T10,T17	Yes	T2,T10,T17	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_error	Yes	Yes	T7,T8,T9	Yes	T7,T8,T9	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T17,T54,T56	Yes	T17,T54,T56	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T17,T54,T56	Yes	T17,T54,T56	OUTPUT
intr_hmac_done_o	Yes	Yes	T2,T3,T5	Yes	T2,T3,T5	OUTPUT
intr_fifo_empty_o	Yes	Yes	T3,T25,T7	Yes	T3,T25,T7	OUTPUT
intr_hmac_err_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
idle_o[3:0]	Yes	Yes	T1,T2,T3	Yes	T2,T3,T5	OUTPUT

*Tests covering at least one bit in the range

---

FSM Coverage for Module : hmac

Summary for FSM :: done_state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	5	5	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: done_state_q

---

states	Line No.	Covered	Tests
DoneAwaitCmd	167	Covered	T1,T2,T3
DoneAwaitHashComplete	176	Covered	T2,T3,T4
DoneAwaitHashDone	157	Covered	T2,T3,T5
DoneAwaitMessageComplete	160	Covered	T2,T3,T4

transitions	Line No.	Covered	Tests
DoneAwaitCmd->DoneAwaitHashDone	157	Covered	T2,T3,T5
DoneAwaitCmd->DoneAwaitMessageComplete	160	Covered	T2,T3,T4
DoneAwaitHashComplete->DoneAwaitCmd	183	Covered	T2,T3,T4
DoneAwaitHashDone->DoneAwaitCmd	167	Covered	T2,T3,T5
DoneAwaitMessageComplete->DoneAwaitHashComplete	176	Covered	T2,T3,T4

---

Branch Coverage for Module : hmac

	Line No.	Total	Covered	Percent
Branches		93	90	96.77
TERNARY	301	2	2	100.00
TERNARY	462	4	4	100.00
TERNARY	472	2	2	100.00
TERNARY	537	2	2	100.00
CASE	153	10	8	80.00
IF	192	2	2	100.00
IF	205	3	3	100.00
IF	219	2	2	100.00
IF	240	6	6	100.00
IF	256	3	3	100.00
CASE	289	4	4	100.00
IF	304	2	2	100.00
CASE	312	6	6	100.00
IF	355	4	4	100.00
IF	365	3	3	100.00
IF	404	4	4	100.00
IF	475	2	2	100.00
IF	545	4	3	75.00
IF	630	2	2	100.00
IF	636	5	5	100.00
IF	645	3	3	100.00
IF	816	2	2	100.00
CASE	839	6	6	100.00
IF	886	2	2	100.00
IF	914	4	4	100.00
IF	921	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_hmac_0.1/rtl/hmac.sv' or '../src/lowrisc_ip_hmac_0.1/rtl/hmac.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	301	(hash_start_or_continue) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	462	((((reg_hash_start || reg_hash_continue) || reg_hash_process) || reg_hash_stop)) ? 
-2-:	462	(fifo_empty_negedge) ? 
-3-:	462	(fifo_full_posedge) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T5
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	472	(fifo_empty_gate) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T25,T11

	LineNo.	Expression
-1-:	537	((hmac_fifo_wsel && fifo_wready)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	153	case (done_state_q)
-2-:	155	if (sha_hash_process)
-3-:	158	if (reg_hash_stop)
-4-:	165	if (reg_hash_done)
-5-:	172	if (digest_on_blk)
-6-:	181	if ((!hash_running))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	Status	Tests
DoneAwaitCmd	1	-	-	-	-	Covered	T2,T3,T5
DoneAwaitCmd	0	1	-	-	-	Covered	T2,T3,T4
DoneAwaitCmd	0	0	-	-	-	Covered	T1,T2,T3
DoneAwaitHashDone	-	-	1	-	-	Covered	T2,T3,T5
DoneAwaitHashDone	-	-	0	-	-	Covered	T2,T3,T5
DoneAwaitMessageComplete	-	-	-	1	-	Covered	T2,T3,T4
DoneAwaitMessageComplete	-	-	-	0	-	Covered	T2,T3,T4
DoneAwaitHashComplete	-	-	-	-	1	Covered	T2,T3,T4
DoneAwaitHashComplete	-	-	-	-	0	Not Covered
default	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	192	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	205	if (wipe_secret)
-2-:	207	if ((!cfg_block))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T3,T24,T25
0	1	Covered	T1,T2,T3
0	0	Covered	T2,T3,T5

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	240	if ((digest_size == SHA2_256))
-2-:	244	if (((digest_size == SHA2_384) || (digest_size == SHA2_512)))
-3-:	246	(reg2hw.digest[(2 * i)].qe) ? 
-4-:	249	(reg2hw.digest[((2 * i) + 1)].qe) ? 

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	1	-	Covered	T2,T3,T4
0	1	0	-	Covered	T1,T2,T3
0	1	-	1	Covered	T2,T3,T4
0	1	-	0	Covered	T1,T2,T3
0	0	-	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	256	if ((digest_size_started_q == SHA2_256))
-2-:	262	if (((digest_size_started_q == SHA2_384) || (digest_size_started_q == SHA2_512)))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T3,T5
0	1	Covered	T2,T3,T5
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	289	case (digest_size_supplied)

Branches:

-1-	Status	Tests
SHA2_256	Covered	T1,T2,T3
SHA2_384	Covered	T1,T2,T3
SHA2_512	Covered	T1,T2,T3
default	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	304	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	312	case (key_length_supplied)

Branches:

-1-	Status	Tests
Key_128	Covered	T1,T2,T3
Key_256	Covered	T1,T2,T3
Key_384	Covered	T2,T3,T6
Key_512	Covered	T2,T3,T5
Key_1024	Covered	T1,T2,T3
default	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	355	if ((!rst_ni))
-2-:	357	if (hash_start_or_continue)
-3-:	359	if ((reg_hash_done || reg_hash_stop))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T5
0	0	1	Covered	T2,T3,T5
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	365	if ((!rst_ni))
-2-:	397	if (((!cfg_block) && reg2hw.cfg.hmac_en.qe))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	404	if ((!rst_ni))
-2-:	406	if (hash_start_or_continue)
-3-:	408	if (packer_flush_done)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T5
0	0	1	Covered	T2,T3,T5
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	475	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	545	if (hmac_fifo_wsel)
-2-:	547	if ((digest_size == SHA2_256))
-3-:	550	if (((digest_size == SHA2_384) || (digest_size == SHA2_512)))

Branches:

-1-	-2-	-3-	Status	Tests
1	1	-	Covered	T2,T3,T5
1	0	1	Covered	T2,T3,T5
1	0	0	Not Covered
0	-	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	630	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	636	if ((!cfg_block))
-2-:	637	if (reg2hw.msg_length_lower.qe)
-3-:	640	if (reg2hw.msg_length_upper.qe)

Branches:

-1-	-2-	-3-	Status	Tests
1	1	-	Covered	T2,T3,T4
1	0	-	Covered	T1,T2,T3
1	-	1	Covered	T2,T3,T4
1	-	0	Covered	T1,T2,T3
0	-	-	Covered	T2,T3,T5

	LineNo.	Expression
-1-:	645	if (hash_start)
-2-:	647	if (((msg_write && sha_en) && packer_ready))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T3,T5
0	1	Covered	T2,T3,T5
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	816	if (cfg_block)

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	839	case (1'b1)

Branches:

-1-	Status	Tests
invalid_config_atstart	Covered	T1,T2,T3
hash_start_sha_disabled	Covered	T3,T27,T53
hash_start_active	Covered	T3,T27,T7
msg_push_not_allowed	Covered	T1,T2,T3
update_seckey_inprocess	Covered	T3,T27,T53
default	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	886	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	914	if ((!rst_ni))
-2-:	915	if ((hash_process || reg_hash_stop))
-3-:	916	if (reg_hash_done)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T5
0	0	1	Covered	T2,T3,T5
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	921	if ((!rst_ni))
-2-:	922	if (hash_start_or_continue)
-3-:	923	if ((hash_process || reg_hash_stop))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T5
0	0	1	Covered	T2,T3,T5
0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Module : hmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertKnownO_A	424004747	423939465	0	0
FpvSecCmRegWeOnehotCheck_A	424004747	120	0	0
IntrFifoEmptyOKnown	424004747	423939465	0	0
IntrHmacDoneOKnown	424004747	423939465	0	0
TlOAReadyKnown	424004747	423939465	0	0
TlODValidKnown	424004747	423939465	0	0
ValidHashProcessAssert	424004747	18243	0	0
ValidHmacEnConditionAssert	424004747	11497	0	0
ValidWriteAssert	424004747	18761750	0	0
gen_assert_wmask_bytealign[0].unnamed$$_0	424004747	18761750	0	0
gen_assert_wmask_bytealign[1].unnamed$$_0	424004747	18761750	0	0
gen_assert_wmask_bytealign[2].unnamed$$_0	424004747	18761750	0	0
gen_assert_wmask_bytealign[3].unnamed$$_0	424004747	18761750	0	0

AlertKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424004747	423939465	0	0
T1	17277	17224	0	0
T2	142674	142602	0	0
T3	156346	156281	0	0
T4	487912	487861	0	0
T5	62103	62004	0	0
T6	34024	33958	0	0
T10	285293	285218	0	0
T16	113324	113240	0	0
T17	790	722	0	0
T18	95829	95744	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424004747	120	0	0
T52	168726	0	0	0
T55	1442	0	0	0
T56	7873	30	0	0
T57	0	30	0	0
T58	0	30	0	0
T59	0	20	0	0
T60	0	10	0	0
T61	1119	0	0	0
T62	382888	0	0	0
T63	24865	0	0	0
T64	688098	0	0	0
T65	325796	0	0	0
T66	93999	0	0	0
T67	1357	0	0	0

IntrFifoEmptyOKnown

Name	Attempts	Real Successes	Failures	Incomplete
Total	424004747	423939465	0	0
T1	17277	17224	0	0
T2	142674	142602	0	0
T3	156346	156281	0	0
T4	487912	487861	0	0
T5	62103	62004	0	0
T6	34024	33958	0	0
T10	285293	285218	0	0
T16	113324	113240	0	0
T17	790	722	0	0
T18	95829	95744	0	0

IntrHmacDoneOKnown

Name	Attempts	Real Successes	Failures	Incomplete
Total	424004747	423939465	0	0
T1	17277	17224	0	0
T2	142674	142602	0	0
T3	156346	156281	0	0
T4	487912	487861	0	0
T5	62103	62004	0	0
T6	34024	33958	0	0
T10	285293	285218	0	0
T16	113324	113240	0	0
T17	790	722	0	0
T18	95829	95744	0	0

TlOAReadyKnown

Name	Attempts	Real Successes	Failures	Incomplete
Total	424004747	423939465	0	0
T1	17277	17224	0	0
T2	142674	142602	0	0
T3	156346	156281	0	0
T4	487912	487861	0	0
T5	62103	62004	0	0
T6	34024	33958	0	0
T10	285293	285218	0	0
T16	113324	113240	0	0
T17	790	722	0	0
T18	95829	95744	0	0

TlODValidKnown

Name	Attempts	Real Successes	Failures	Incomplete
Total	424004747	423939465	0	0
T1	17277	17224	0	0
T2	142674	142602	0	0
T3	156346	156281	0	0
T4	487912	487861	0	0
T5	62103	62004	0	0
T6	34024	33958	0	0
T10	285293	285218	0	0
T16	113324	113240	0	0
T17	790	722	0	0
T18	95829	95744	0	0

ValidHashProcessAssert

Name	Attempts	Real Successes	Failures	Incomplete
Total	424004747	18243	0	0
T2	142674	16	0	0
T3	156346	147	0	0
T4	487912	26	0	0
T5	62103	2	0	0
T6	34024	8	0	0
T10	285293	0	0	0
T16	113324	13	0	0
T17	790	0	0	0
T18	95829	8	0	0
T24	974988	26	0	0
T27	0	7	0	0
T28	0	16	0	0

ValidHmacEnConditionAssert

Name	Attempts	Real Successes	Failures	Incomplete
Total	424004747	11497	0	0
T1	17277	4	0	0
T2	142674	15	0	0
T3	156346	173	0	0
T4	487912	18	0	0
T5	62103	1	0	0
T6	34024	12	0	0
T10	285293	10	0	0
T16	113324	14	0	0
T17	790	0	0	0
T18	95829	1	0	0
T24	0	21	0	0

ValidWriteAssert

Name	Attempts	Real Successes	Failures	Incomplete
Total	424004747	18761750	0	0
T1	17277	1696	0	0
T2	142674	16791	0	0
T3	156346	208896	0	0
T4	487912	24591	0	0
T5	62103	7426	0	0
T6	34024	704	0	0
T10	285293	9012	0	0
T16	113324	20969	0	0
T17	790	0	0	0
T18	95829	11366	0	0
T24	0	22025	0	0

gen_assert_wmask_bytealign[0].unnamed$$_0

Name	Attempts	Real Successes	Failures	Incomplete
Total	424004747	18761750	0	0
T1	17277	1696	0	0
T2	142674	16791	0	0
T3	156346	208896	0	0
T4	487912	24591	0	0
T5	62103	7426	0	0
T6	34024	704	0	0
T10	285293	9012	0	0
T16	113324	20969	0	0
T17	790	0	0	0
T18	95829	11366	0	0
T24	0	22025	0	0

gen_assert_wmask_bytealign[1].unnamed$$_0

Name	Attempts	Real Successes	Failures	Incomplete
Total	424004747	18761750	0	0
T1	17277	1696	0	0
T2	142674	16791	0	0
T3	156346	208896	0	0
T4	487912	24591	0	0
T5	62103	7426	0	0
T6	34024	704	0	0
T10	285293	9012	0	0
T16	113324	20969	0	0
T17	790	0	0	0
T18	95829	11366	0	0
T24	0	22025	0	0

gen_assert_wmask_bytealign[2].unnamed$$_0

Name	Attempts	Real Successes	Failures	Incomplete
Total	424004747	18761750	0	0
T1	17277	1696	0	0
T2	142674	16791	0	0
T3	156346	208896	0	0
T4	487912	24591	0	0
T5	62103	7426	0	0
T6	34024	704	0	0
T10	285293	9012	0	0
T16	113324	20969	0	0
T17	790	0	0	0
T18	95829	11366	0	0
T24	0	22025	0	0

gen_assert_wmask_bytealign[3].unnamed$$_0

Name	Attempts	Real Successes	Failures	Incomplete
Total	424004747	18761750	0	0
T1	17277	1696	0	0
T2	142674	16791	0	0
T3	156346	208896	0	0
T4	487912	24591	0	0
T5	62103	7426	0	0
T6	34024	704	0	0
T10	285293	9012	0	0
T16	113324	20969	0	0
T17	790	0	0	0
T18	95829	11366	0	0
T24	0	22025	0	0

Line Coverage for Instance : tb.dut

	Line No.	Total	Covered	Percent
TOTAL		198	198	100.00
CONT_ASSIGN	135	1	1	100.00
CONT_ASSIGN	136	1	1	100.00
CONT_ASSIGN	137	1	1	100.00
CONT_ASSIGN	138	1	1	100.00
ALWAYS	150	15	15	100.00
ALWAYS	192	3	3	100.00
CONT_ASSIGN	199	1	1	100.00
CONT_ASSIGN	200	1	1	100.00
ALWAYS	204	7	7	100.00
ALWAYS	219	3	3	100.00
ALWAYS	231	19	19	100.00
CONT_ASSIGN	277	1	1	100.00
CONT_ASSIGN	282	1	1	100.00
CONT_ASSIGN	283	1	1	100.00
CONT_ASSIGN	285	1	1	100.00
ALWAYS	287	5	5	100.00
CONT_ASSIGN	301	1	1	100.00
ALWAYS	304	3	3	100.00
CONT_ASSIGN	308	1	1	100.00
ALWAYS	310	7	7	100.00
CONT_ASSIGN	325	1	1	100.00
CONT_ASSIGN	326	1	1	100.00
CONT_ASSIGN	327	1	1	100.00
CONT_ASSIGN	329	1	1	100.00
CONT_ASSIGN	330	1	1	100.00
CONT_ASSIGN	331	1	1	100.00
CONT_ASSIGN	332	1	1	100.00
CONT_ASSIGN	333	1	1	100.00
CONT_ASSIGN	334	1	1	100.00
CONT_ASSIGN	335	1	1	100.00
CONT_ASSIGN	337	1	1	100.00
CONT_ASSIGN	338	1	1	100.00
CONT_ASSIGN	339	1	1	100.00
CONT_ASSIGN	340	1	1	100.00
CONT_ASSIGN	343	1	1	100.00
CONT_ASSIGN	344	1	1	100.00
CONT_ASSIGN	349	1	1	100.00
CONT_ASSIGN	350	1	1	100.00
CONT_ASSIGN	351	1	1	100.00
CONT_ASSIGN	352	1	1	100.00
ALWAYS	355	6	6	100.00
ALWAYS	365	4	4	100.00
ALWAYS	404	6	6	100.00
CONT_ASSIGN	454	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	462	1	1	100.00
CONT_ASSIGN	470	1	1	100.00
CONT_ASSIGN	472	1	1	100.00
ALWAYS	475	7	7	100.00
CONT_ASSIGN	518	1	1	100.00
CONT_ASSIGN	521	1	1	100.00
CONT_ASSIGN	527	1	1	100.00
CONT_ASSIGN	532	1	1	100.00
CONT_ASSIGN	533	1	1	100.00
CONT_ASSIGN	535	1	1	100.00
CONT_ASSIGN	536	1	1	100.00
CONT_ASSIGN	537	1	1	100.00
ALWAYS	542	9	9	100.00
CONT_ASSIGN	617	1	1	100.00
ALWAYS	622	3	3	100.00
ALWAYS	630	3	3	100.00
ALWAYS	635	10	10	100.00
CONT_ASSIGN	652	1	1	100.00
CONT_ASSIGN	653	1	1	100.00
CONT_ASSIGN	660	1	1	100.00
CONT_ASSIGN	661	1	1	100.00
CONT_ASSIGN	771	1	1	100.00
CONT_ASSIGN	800	1	1	100.00
CONT_ASSIGN	801	1	1	100.00
CONT_ASSIGN	802	1	1	100.00
CONT_ASSIGN	807	1	1	100.00
CONT_ASSIGN	812	1	1	100.00
ALWAYS	815	6	6	100.00
CONT_ASSIGN	831	1	1	100.00
ALWAYS	837	7	7	100.00
CONT_ASSIGN	880	1	1	100.00
CONT_ASSIGN	884	1	1	100.00
ALWAYS	886	3	3	100.00
CONT_ASSIGN	892	1	1	100.00
ALWAYS	914	6	6	100.00
ALWAYS	921	6	6	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_hmac_0.1/rtl/hmac.sv' or '../src/lowrisc_ip_hmac_0.1/rtl/hmac.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
135	1	1
136	1	1
137	1	1
138	1	1
150	1	1
151	1	1
153	1	1
155	1	1
157	1	1
158	1	1
160	1	1
			MISSING_ELSE
165	1	1
166	1	1
167	1	1
			MISSING_ELSE
172	1	1
176	1	1
			MISSING_ELSE
181	1	1
182	1	1
183	1	1
			==> MISSING_ELSE
192	1	1
193	1	1
195	1	1
199	1	1
200	1	1
204	1	1
205	1	1
206	1	1
207	1	1
209	1	1
210	1	1
212	1	1
			MISSING_ELSE
			MISSING_ELSE
219	2	2
220	1	1
231	1	1
232	1	1
234	1	1
236	1	1
240	1	1
242	1	1
243	1	1
244	1	1
246	1	1
249	1	1
252	1	1
			MISSING_ELSE
256	1	1
257	1	1
261	1	1
262	1	1
266	1	1
267	1	1
270	1	1
271	1	1
277	1	1
282	1	1
283	1	1
285	1	1
287	1	1
289	1	1
290	1	1
291	1	1
292	1	1
301	1	1
304	2	2
305	1	1
308	1	1
310	1	1
312	1	1
313	1	1
314	1	1
315	1	1
316	1	1
317	1	1
325	1	1
326	1	1
327	1	1
329	1	1
330	1	1
331	1	1
332	1	1
333	1	1
334	1	1
335	1	1
337	1	1
338	1	1
339	1	1
340	1	1
343	1	1
344	1	1
349	1	1
350	1	1
351	1	1
352	1	1
355	1	1
356	1	1
357	1	1
358	1	1
359	1	1
360	1	1
			MISSING_ELSE
365	1	1
366	1	1
397	1	1
398	1	1
			MISSING_ELSE
404	1	1
405	1	1
406	1	1
407	1	1
408	1	1
409	1	1
			MISSING_ELSE
454	1	1
455	1	1
462	1	1
470	1	1
472	1	1
475	1	1
476	1	1
477	1	1
478	1	1
480	1	1
481	1	1
482	1	1
518	1	1
521	1	1
527	1	1
532	1	1
533	1	1
535	1	1
536	1	1
537	1	1
542	1	1
543	1	1
545	1	1
546	1	1
547	1	1
549	1	1
550	1	1
552	1	1
553	1	1
			==> MISSING_ELSE
			MISSING_ELSE
617	1	1
622	1	1
623	1	1
624	1	1
630	2	2
631	1	1
635	1	1
636	1	1
637	1	1
638	1	1
			MISSING_ELSE
640	1	1
641	1	1
			MISSING_ELSE
			MISSING_ELSE
645	1	1
646	1	1
647	1	1
648	1	1
			MISSING_ELSE
652	1	1
653	1	1
660	1	1
661	1	1
771	1	1
800	1	1
801	1	1
802	1	1
807	1	1
812	1	1
815	1	1
816	1	1
817	1	1
818	1	1
819	1	1
			MISSING_ELSE
823	1	1
831	1	1
837	1	1
839	1	1
842	1	1
846	1	1
850	1	1
854	1	1
858	1	1
880	1	1
884	1	1
886	1	1
887	1	1
889	1	1
892	1	1
914	2	2
915	2	2
916	2	2
			MISSING_ELSE
921	2	2
922	2	2
923	2	2
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut

	Total	Covered	Percent
Conditions	179	168	93.85
Logical	179	168	93.85
Non-Logical	0	0
Event	0	0

 LINE       240
 EXPRESSION (digest_size == SHA2_256)
            ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       244
 EXPRESSION ((digest_size == SHA2_384) || (digest_size == SHA2_512))
             ------------1------------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       244
 SUB-EXPRESSION (digest_size == SHA2_384)
                ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       244
 SUB-EXPRESSION (digest_size == SHA2_512)
                ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       246
 EXPRESSION (reg2hw.digest[(2 * i)].qe ? prim_sha2_pkg::conv_endian32(reg2hw.digest[(2 * i)].q, digest_swap) : digest[i][63:32])
             ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       249
 EXPRESSION (reg2hw.digest[((2 * i) + 1)].qe ? prim_sha2_pkg::conv_endian32(reg2hw.digest[((2 * i) + 1)].q, digest_swap) : digest[i][31:0])
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       252
 EXPRESSION (reg2hw.digest[(2 * i)].qe | reg2hw.digest[((2 * i) + 1)].qe)
             ------------1------------   ---------------2---------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T3,T4

 LINE       256
 EXPRESSION (digest_size_started_q == SHA2_256)
            -----------------1-----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T5

 LINE       262
 EXPRESSION ((digest_size_started_q == SHA2_384) || (digest_size_started_q == SHA2_512))
             -----------------1-----------------    -----------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T5
1	0	Covered	T2,T3,T6

 LINE       262
 SUB-EXPRESSION (digest_size_started_q == SHA2_384)
                -----------------1-----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T6

 LINE       262
 SUB-EXPRESSION (digest_size_started_q == SHA2_512)
                -----------------1-----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T5

 LINE       301
 EXPRESSION (hash_start_or_continue ? digest_size : digest_size_started_q)
             -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T5

 LINE       337
 EXPRESSION (reg2hw.cmd.hash_start.qe & reg2hw.cmd.hash_start.q)
             ------------1-----------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T5
1	1	Covered	T1,T2,T3

 LINE       338
 EXPRESSION (reg2hw.cmd.hash_stop.qe & reg2hw.cmd.hash_stop.q)
             -----------1-----------   -----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T4

 LINE       339
 EXPRESSION (reg2hw.cmd.hash_continue.qe & reg2hw.cmd.hash_continue.q)
             -------------1-------------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T4

 LINE       340
 EXPRESSION (reg2hw.cmd.hash_process.qe & reg2hw.cmd.hash_process.q)
             -------------1------------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T5

 LINE       349
 EXPRESSION (reg_hash_start & sha_en & ((~cfg_block)) & ((~invalid_config)))
             -------1------   ---2--   -------3------   ---------4---------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Covered	T1,T2,T3
1	0	1	1	Covered	T3,T27,T53
1	1	0	1	Covered	T3,T27,T7
1	1	1	0	Covered	T1,T2,T3
1	1	1	1	Covered	T2,T3,T5

 LINE       350
 EXPRESSION (reg_hash_continue & sha_en & ((~cfg_block)) & ((~invalid_config)))
             --------1--------   ---2--   -------3------   ---------4---------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Covered	T1,T2,T3
1	0	1	1	Not Covered
1	1	0	1	Not Covered
1	1	1	0	Not Covered
1	1	1	1	Covered	T2,T3,T4

 LINE       351
 EXPRESSION (reg_hash_process & sha_en & cfg_block & ((~invalid_config)))
             --------1-------   ---2--   ----3----   ---------4---------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Covered	T2,T3,T5
1	0	1	1	Not Covered
1	1	0	1	Not Covered
1	1	1	0	Not Covered
1	1	1	1	Covered	T2,T3,T5

 LINE       352
 EXPRESSION (hash_start | hash_continue)
             -----1----   ------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T3,T5

 LINE       359
 EXPRESSION (reg_hash_done || reg_hash_stop)
             ------1------    ------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T3,T5

 LINE       397
 EXPRESSION (((!cfg_block)) && reg2hw.cfg.hmac_en.qe)
             -------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T3,T27,T53
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       454
 EXPRESSION (fifo_empty_q & ((~fifo_empty)))
             ------1-----   -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T5

 LINE       455
 EXPRESSION (((~fifo_full_q)) & fifo_full)
             --------1-------   ----2----

-1-	-2-	Status	Tests
0	1	Covered	T3,T25,T11
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       462
 EXPRESSION 
 Number  Term
      1  (reg_hash_start || reg_hash_continue || reg_hash_process || reg_hash_stop) ? 1'b0 : (fifo_empty_negedge ? 1'b0 : (fifo_full_posedge ? 1'b1 : fifo_full_seen_q)))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       462
 SUB-EXPRESSION (reg_hash_start || reg_hash_continue || reg_hash_process || reg_hash_stop)
                 -------1------    --------2--------    --------3-------    ------4------

-1-	-2-	-3-	-4-	Status	Tests
0	0	0	0	Covered	T1,T2,T3
0	0	0	1	Covered	T2,T3,T4
0	0	1	0	Covered	T2,T3,T5
0	1	0	0	Covered	T2,T3,T4
1	0	0	0	Covered	T1,T2,T3

 LINE       462
 SUB-EXPRESSION (fifo_empty_negedge ? 1'b0 : (fifo_full_posedge ? 1'b1 : fifo_full_seen_q))
                 ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T5

 LINE       462
 SUB-EXPRESSION (fifo_full_posedge ? 1'b1 : fifo_full_seen_q)
                 --------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       470
 EXPRESSION (((~msg_allowed)) || ((~fifo_full_seen_q)))
             --------1-------    ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T3,T25,T11
0	1	Covered	T2,T3,T5
1	0	Covered	T1,T2,T3

 LINE       472
 EXPRESSION (fifo_empty_gate ? 1'b0 : fifo_empty)
             -------1-------

-1-	Status	Tests
0	Covered	T3,T25,T11
1	Covered	T1,T2,T3

 LINE       518
 EXPRESSION (msg_fifo_req & ((~msg_fifo_we)))
             ------1-----   --------2-------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Excluded		VC_COV_UNR

 LINE       521
 EXPRESSION (msg_fifo_req & ((~hmac_fifo_wsel)) & packer_ready)
             ------1-----   ---------2---------   ------3-----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Unreachable	T11,T12,T13
1	1	1	Covered	T1,T2,T3

 LINE       537
 EXPRESSION ((hmac_fifo_wsel && fifo_wready) ? hmac_fifo_wvalid : reg_fifo_wvalid)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T5

 LINE       537
 SUB-EXPRESSION (hmac_fifo_wsel && fifo_wready)
                 -------1------    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T5

 LINE       547
 EXPRESSION (digest_size == SHA2_256)
            ------------1------------

-1-	Status	Tests
0	Covered	T2,T3,T5
1	Covered	T2,T3,T5

 LINE       550
 EXPRESSION ((digest_size == SHA2_384) || (digest_size == SHA2_512))
             ------------1------------    ------------2------------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Covered	T2,T3,T5
1	0	Covered	T2,T3,T6

 LINE       550
 SUB-EXPRESSION (digest_size == SHA2_384)
                ------------1------------

-1-	Status	Tests
0	Covered	T2,T3,T5
1	Covered	T2,T3,T6

 LINE       550
 SUB-EXPRESSION (digest_size == SHA2_512)
                ------------1------------

-1-	Status	Tests
0	Covered	T2,T3,T6
1	Covered	T2,T3,T5

 LINE       564
 EXPRESSION (fifo_wvalid & sha_en)
             -----1-----   ---2--

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T2,T3
1	0	Excluded		VC_COV_UNR
1	1	Covered	T2,T3,T5

 LINE       617
 EXPRESSION (msg_fifo_req & msg_fifo_we & ((~hmac_fifo_wsel)) & msg_allowed)
             ------1-----   -----2-----   ---------3---------   -----4-----

-1-	-2-	-3-	-4-	Status	Tests	Exclude Annotation
0	1	1	1	Covered	T2,T3,T5
1	0	1	1	Excluded		VC_COV_UNR
1	1	0	1	Excluded		VC_COV_UNR
1	1	1	0	Covered	T1,T2,T3
1	1	1	1	Covered	T2,T3,T5

 LINE       647
 EXPRESSION (msg_write && sha_en && packer_ready)
             ----1----    ---2--    ------3-----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Unreachable	T11,T12,T13
1	1	1	Covered	T2,T3,T5

 LINE       667
 EXPRESSION (msg_write & sha_en)
             ----1----   ---2--

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T2,T3
1	0	Excluded		VC_COV_UNR
1	1	Covered	T2,T3,T5

 LINE       667
 EXPRESSION (fifo_wready & ((~hmac_fifo_wsel)))
             -----1-----   ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T5
1	1	Covered	T1,T2,T3

 LINE       771
 SUB-EXPRESSION (reg2hw.alert_test.q & reg2hw.alert_test.qe)
                 ---------1---------   ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T17,T54,T55
1	0	Covered	T1,T2,T3
1	1	Covered	T17,T54,T55

 LINE       800
 EXPRESSION ((reg_hash_start | reg_hash_continue) & ((~sha_en)))
             ------------------1-----------------   -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T27,T53

 LINE       800
 SUB-EXPRESSION (reg_hash_start | reg_hash_continue)
                 -------1------   --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3

 LINE       801
 EXPRESSION ((reg_hash_start | reg_hash_continue) & cfg_block)
             ------------------1-----------------   ----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T27,T7

 LINE       801
 SUB-EXPRESSION (reg_hash_start | reg_hash_continue)
                 -------1------   --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3

 LINE       802
 EXPRESSION (msg_fifo_req & ((~msg_allowed)))
             ------1-----   --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T5
1	1	Covered	T1,T2,T3

 LINE       807
 EXPRESSION ((digest_size == SHA2_None) | ((key_length == Key_None) && hmac_en) | ((key_length == Key_1024) && (digest_size == SHA2_256) && hmac_en))
             -------------1------------   ------------------2------------------   ---------------------------------3--------------------------------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T3,T4,T24
0	1	0	Covered	T1,T2,T3
1	0	0	Covered	T1,T2,T3

 LINE       807
 SUB-EXPRESSION (digest_size == SHA2_None)
                -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       807
 SUB-EXPRESSION ((key_length == Key_None) && hmac_en)
                 ------------1-----------    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       807
 SUB-EXPRESSION (key_length == Key_None)
                ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       807
 SUB-EXPRESSION ((key_length == Key_1024) && (digest_size == SHA2_256) && hmac_en)
                 ------------1-----------    ------------2------------    ---3---

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T3,T6
1	1	0	Covered	T3,T6,T24
1	1	1	Covered	T3,T4,T24

 LINE       807
 SUB-EXPRESSION (key_length == Key_1024)
                ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       807
 SUB-EXPRESSION (digest_size == SHA2_256)
                ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       812
 EXPRESSION ((reg_hash_start || reg_hash_continue) & invalid_config)
             ------------------1------------------   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T5
1	1	Covered	T1,T2,T3

 LINE       812
 SUB-EXPRESSION (reg_hash_start || reg_hash_continue)
                 -------1------    --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3

 LINE       831
 EXPRESSION 
 Number  Term
      1  ((~reg2hw.intr_state.hmac_err.q)) & 
      2  (hash_start_sha_disabled | update_seckey_inprocess | hash_start_active | msg_push_not_allowed | invalid_config_atstart))

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       831
 SUB-EXPRESSION (hash_start_sha_disabled | update_seckey_inprocess | hash_start_active | msg_push_not_allowed | invalid_config_atstart)
                 -----------1-----------   -----------2-----------   --------3--------   ----------4---------   -----------5----------

-1-	-2-	-3-	-4-	-5-	Status	Tests
0	0	0	0	0	Covered	T1,T2,T3
0	0	0	0	1	Covered	T1,T2,T3
0	0	0	1	0	Covered	T1,T2,T3
0	0	1	0	0	Covered	T3,T27,T7
0	1	0	0	0	Covered	T3,T27,T53
1	0	0	0	0	Covered	T3,T27,T53

 LINE       880
 EXPRESSION (((!reg_fifo_wvalid)) && ((!fifo_rvalid)) && hmac_core_idle && sha_core_idle)
             ----------1---------    --------2-------    -------3------    ------4------

-1-	-2-	-3-	-4-	Status	Tests	Exclude Annotation
0	1	1	1	Excluded		VC_COV_UNR
1	0	1	1	Not Covered
1	1	0	1	Covered	T2,T3,T5
1	1	1	0	Covered	T2,T3,T6
1	1	1	1	Covered	T1,T2,T3

 LINE       915
 EXPRESSION (hash_process || reg_hash_stop)
             ------1-----    ------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T3,T5

 LINE       923
 EXPRESSION (hash_process || reg_hash_stop)
             ------1-----    ------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T3,T5

---

Toggle Coverage for Instance : tb.dut

	Total	Covered	Percent
Totals	30	30	100.00
Total Bits	346	346	100.00
Total Bits 0->1	173	173	100.00
Total Bits 1->0	173	173	100.00

Ports	30	30	100.00
Port Bits	346	346	100.00
Port Bits 0->1	173	173	100.00
Port Bits 1->0	173	173	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T3,T25,T7	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T3,T10,T6	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T2,T10,T17	Yes	T2,T10,T17	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_error	Yes	Yes	T7,T8,T9	Yes	T7,T8,T9	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T17,T54,T56	Yes	T17,T54,T56	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T17,T54,T56	Yes	T17,T54,T56	OUTPUT
intr_hmac_done_o	Yes	Yes	T2,T3,T5	Yes	T2,T3,T5	OUTPUT
intr_fifo_empty_o	Yes	Yes	T3,T25,T7	Yes	T3,T25,T7	OUTPUT
intr_hmac_err_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
idle_o[3:0]	Yes	Yes	T1,T2,T3	Yes	T2,T3,T5	OUTPUT

*Tests covering at least one bit in the range

---

FSM Coverage for Instance : tb.dut

Summary for FSM :: done_state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	5	5	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: done_state_q

---

states	Line No.	Covered	Tests
DoneAwaitCmd	167	Covered	T1,T2,T3
DoneAwaitHashComplete	176	Covered	T2,T3,T4
DoneAwaitHashDone	157	Covered	T2,T3,T5
DoneAwaitMessageComplete	160	Covered	T2,T3,T4

transitions	Line No.	Covered	Tests
DoneAwaitCmd->DoneAwaitHashDone	157	Covered	T2,T3,T5
DoneAwaitCmd->DoneAwaitMessageComplete	160	Covered	T2,T3,T4
DoneAwaitHashComplete->DoneAwaitCmd	183	Covered	T2,T3,T4
DoneAwaitHashDone->DoneAwaitCmd	167	Covered	T2,T3,T5
DoneAwaitMessageComplete->DoneAwaitHashComplete	176	Covered	T2,T3,T4

---

Branch Coverage for Instance : tb.dut

	Line No.	Total	Covered	Percent
Branches		93	90	96.77
TERNARY	301	2	2	100.00
TERNARY	462	4	4	100.00
TERNARY	472	2	2	100.00
TERNARY	537	2	2	100.00
CASE	153	10	8	80.00
IF	192	2	2	100.00
IF	205	3	3	100.00
IF	219	2	2	100.00
IF	240	6	6	100.00
IF	256	3	3	100.00
CASE	289	4	4	100.00
IF	304	2	2	100.00
CASE	312	6	6	100.00
IF	355	4	4	100.00
IF	365	3	3	100.00
IF	404	4	4	100.00
IF	475	2	2	100.00
IF	545	4	3	75.00
IF	630	2	2	100.00
IF	636	5	5	100.00
IF	645	3	3	100.00
IF	816	2	2	100.00
CASE	839	6	6	100.00
IF	886	2	2	100.00
IF	914	4	4	100.00
IF	921	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_hmac_0.1/rtl/hmac.sv' or '../src/lowrisc_ip_hmac_0.1/rtl/hmac.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	301	(hash_start_or_continue) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	462	((((reg_hash_start || reg_hash_continue) || reg_hash_process) || reg_hash_stop)) ? 
-2-:	462	(fifo_empty_negedge) ? 
-3-:	462	(fifo_full_posedge) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T5
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	472	(fifo_empty_gate) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T25,T11

	LineNo.	Expression
-1-:	537	((hmac_fifo_wsel && fifo_wready)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	153	case (done_state_q)
-2-:	155	if (sha_hash_process)
-3-:	158	if (reg_hash_stop)
-4-:	165	if (reg_hash_done)
-5-:	172	if (digest_on_blk)
-6-:	181	if ((!hash_running))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	Status	Tests
DoneAwaitCmd	1	-	-	-	-	Covered	T2,T3,T5
DoneAwaitCmd	0	1	-	-	-	Covered	T2,T3,T4
DoneAwaitCmd	0	0	-	-	-	Covered	T1,T2,T3
DoneAwaitHashDone	-	-	1	-	-	Covered	T2,T3,T5
DoneAwaitHashDone	-	-	0	-	-	Covered	T2,T3,T5
DoneAwaitMessageComplete	-	-	-	1	-	Covered	T2,T3,T4
DoneAwaitMessageComplete	-	-	-	0	-	Covered	T2,T3,T4
DoneAwaitHashComplete	-	-	-	-	1	Covered	T2,T3,T4
DoneAwaitHashComplete	-	-	-	-	0	Not Covered
default	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	192	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	205	if (wipe_secret)
-2-:	207	if ((!cfg_block))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T3,T24,T25
0	1	Covered	T1,T2,T3
0	0	Covered	T2,T3,T5

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	240	if ((digest_size == SHA2_256))
-2-:	244	if (((digest_size == SHA2_384) || (digest_size == SHA2_512)))
-3-:	246	(reg2hw.digest[(2 * i)].qe) ? 
-4-:	249	(reg2hw.digest[((2 * i) + 1)].qe) ? 

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	1	-	Covered	T2,T3,T4
0	1	0	-	Covered	T1,T2,T3
0	1	-	1	Covered	T2,T3,T4
0	1	-	0	Covered	T1,T2,T3
0	0	-	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	256	if ((digest_size_started_q == SHA2_256))
-2-:	262	if (((digest_size_started_q == SHA2_384) || (digest_size_started_q == SHA2_512)))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T3,T5
0	1	Covered	T2,T3,T5
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	289	case (digest_size_supplied)

Branches:

-1-	Status	Tests
SHA2_256	Covered	T1,T2,T3
SHA2_384	Covered	T1,T2,T3
SHA2_512	Covered	T1,T2,T3
default	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	304	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	312	case (key_length_supplied)

Branches:

-1-	Status	Tests
Key_128	Covered	T1,T2,T3
Key_256	Covered	T1,T2,T3
Key_384	Covered	T2,T3,T6
Key_512	Covered	T2,T3,T5
Key_1024	Covered	T1,T2,T3
default	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	355	if ((!rst_ni))
-2-:	357	if (hash_start_or_continue)
-3-:	359	if ((reg_hash_done || reg_hash_stop))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T5
0	0	1	Covered	T2,T3,T5
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	365	if ((!rst_ni))
-2-:	397	if (((!cfg_block) && reg2hw.cfg.hmac_en.qe))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	404	if ((!rst_ni))
-2-:	406	if (hash_start_or_continue)
-3-:	408	if (packer_flush_done)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T5
0	0	1	Covered	T2,T3,T5
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	475	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	545	if (hmac_fifo_wsel)
-2-:	547	if ((digest_size == SHA2_256))
-3-:	550	if (((digest_size == SHA2_384) || (digest_size == SHA2_512)))

Branches:

-1-	-2-	-3-	Status	Tests
1	1	-	Covered	T2,T3,T5
1	0	1	Covered	T2,T3,T5
1	0	0	Not Covered
0	-	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	630	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	636	if ((!cfg_block))
-2-:	637	if (reg2hw.msg_length_lower.qe)
-3-:	640	if (reg2hw.msg_length_upper.qe)

Branches:

-1-	-2-	-3-	Status	Tests
1	1	-	Covered	T2,T3,T4
1	0	-	Covered	T1,T2,T3
1	-	1	Covered	T2,T3,T4
1	-	0	Covered	T1,T2,T3
0	-	-	Covered	T2,T3,T5

	LineNo.	Expression
-1-:	645	if (hash_start)
-2-:	647	if (((msg_write && sha_en) && packer_ready))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T3,T5
0	1	Covered	T2,T3,T5
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	816	if (cfg_block)

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	839	case (1'b1)

Branches:

-1-	Status	Tests
invalid_config_atstart	Covered	T1,T2,T3
hash_start_sha_disabled	Covered	T3,T27,T53
hash_start_active	Covered	T3,T27,T7
msg_push_not_allowed	Covered	T1,T2,T3
update_seckey_inprocess	Covered	T3,T27,T53
default	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	886	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	914	if ((!rst_ni))
-2-:	915	if ((hash_process || reg_hash_stop))
-3-:	916	if (reg_hash_done)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T5
0	0	1	Covered	T2,T3,T5
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	921	if ((!rst_ni))
-2-:	922	if (hash_start_or_continue)
-3-:	923	if ((hash_process || reg_hash_stop))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T5
0	0	1	Covered	T2,T3,T5
0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertKnownO_A	424004747	423939465	0	0
FpvSecCmRegWeOnehotCheck_A	424004747	120	0	0
IntrFifoEmptyOKnown	424004747	423939465	0	0
IntrHmacDoneOKnown	424004747	423939465	0	0
TlOAReadyKnown	424004747	423939465	0	0
TlODValidKnown	424004747	423939465	0	0
ValidHashProcessAssert	424004747	18243	0	0
ValidHmacEnConditionAssert	424004747	11497	0	0
ValidWriteAssert	424004747	18761750	0	0
gen_assert_wmask_bytealign[0].unnamed$$_0	424004747	18761750	0	0
gen_assert_wmask_bytealign[1].unnamed$$_0	424004747	18761750	0	0
gen_assert_wmask_bytealign[2].unnamed$$_0	424004747	18761750	0	0
gen_assert_wmask_bytealign[3].unnamed$$_0	424004747	18761750	0	0

AlertKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424004747	423939465	0	0
T1	17277	17224	0	0
T2	142674	142602	0	0
T3	156346	156281	0	0
T4	487912	487861	0	0
T5	62103	62004	0	0
T6	34024	33958	0	0
T10	285293	285218	0	0
T16	113324	113240	0	0
T17	790	722	0	0
T18	95829	95744	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424004747	120	0	0
T52	168726	0	0	0
T55	1442	0	0	0
T56	7873	30	0	0
T57	0	30	0	0
T58	0	30	0	0
T59	0	20	0	0
T60	0	10	0	0
T61	1119	0	0	0
T62	382888	0	0	0
T63	24865	0	0	0
T64	688098	0	0	0
T65	325796	0	0	0
T66	93999	0	0	0
T67	1357	0	0	0

IntrFifoEmptyOKnown

Name	Attempts	Real Successes	Failures	Incomplete
Total	424004747	423939465	0	0
T1	17277	17224	0	0
T2	142674	142602	0	0
T3	156346	156281	0	0
T4	487912	487861	0	0
T5	62103	62004	0	0
T6	34024	33958	0	0
T10	285293	285218	0	0
T16	113324	113240	0	0
T17	790	722	0	0
T18	95829	95744	0	0

IntrHmacDoneOKnown

Name	Attempts	Real Successes	Failures	Incomplete
Total	424004747	423939465	0	0
T1	17277	17224	0	0
T2	142674	142602	0	0
T3	156346	156281	0	0
T4	487912	487861	0	0
T5	62103	62004	0	0
T6	34024	33958	0	0
T10	285293	285218	0	0
T16	113324	113240	0	0
T17	790	722	0	0
T18	95829	95744	0	0

TlOAReadyKnown

Name	Attempts	Real Successes	Failures	Incomplete
Total	424004747	423939465	0	0
T1	17277	17224	0	0
T2	142674	142602	0	0
T3	156346	156281	0	0
T4	487912	487861	0	0
T5	62103	62004	0	0
T6	34024	33958	0	0
T10	285293	285218	0	0
T16	113324	113240	0	0
T17	790	722	0	0
T18	95829	95744	0	0

TlODValidKnown

Name	Attempts	Real Successes	Failures	Incomplete
Total	424004747	423939465	0	0
T1	17277	17224	0	0
T2	142674	142602	0	0
T3	156346	156281	0	0
T4	487912	487861	0	0
T5	62103	62004	0	0
T6	34024	33958	0	0
T10	285293	285218	0	0
T16	113324	113240	0	0
T17	790	722	0	0
T18	95829	95744	0	0

ValidHashProcessAssert

Name	Attempts	Real Successes	Failures	Incomplete
Total	424004747	18243	0	0
T2	142674	16	0	0
T3	156346	147	0	0
T4	487912	26	0	0
T5	62103	2	0	0
T6	34024	8	0	0
T10	285293	0	0	0
T16	113324	13	0	0
T17	790	0	0	0
T18	95829	8	0	0
T24	974988	26	0	0
T27	0	7	0	0
T28	0	16	0	0

ValidHmacEnConditionAssert

Name	Attempts	Real Successes	Failures	Incomplete
Total	424004747	11497	0	0
T1	17277	4	0	0
T2	142674	15	0	0
T3	156346	173	0	0
T4	487912	18	0	0
T5	62103	1	0	0
T6	34024	12	0	0
T10	285293	10	0	0
T16	113324	14	0	0
T17	790	0	0	0
T18	95829	1	0	0
T24	0	21	0	0

ValidWriteAssert

Name	Attempts	Real Successes	Failures	Incomplete
Total	424004747	18761750	0	0
T1	17277	1696	0	0
T2	142674	16791	0	0
T3	156346	208896	0	0
T4	487912	24591	0	0
T5	62103	7426	0	0
T6	34024	704	0	0
T10	285293	9012	0	0
T16	113324	20969	0	0
T17	790	0	0	0
T18	95829	11366	0	0
T24	0	22025	0	0

gen_assert_wmask_bytealign[0].unnamed$$_0

Name	Attempts	Real Successes	Failures	Incomplete
Total	424004747	18761750	0	0
T1	17277	1696	0	0
T2	142674	16791	0	0
T3	156346	208896	0	0
T4	487912	24591	0	0
T5	62103	7426	0	0
T6	34024	704	0	0
T10	285293	9012	0	0
T16	113324	20969	0	0
T17	790	0	0	0
T18	95829	11366	0	0
T24	0	22025	0	0

gen_assert_wmask_bytealign[1].unnamed$$_0

Name	Attempts	Real Successes	Failures	Incomplete
Total	424004747	18761750	0	0
T1	17277	1696	0	0
T2	142674	16791	0	0
T3	156346	208896	0	0
T4	487912	24591	0	0
T5	62103	7426	0	0
T6	34024	704	0	0
T10	285293	9012	0	0
T16	113324	20969	0	0
T17	790	0	0	0
T18	95829	11366	0	0
T24	0	22025	0	0

gen_assert_wmask_bytealign[2].unnamed$$_0

Name	Attempts	Real Successes	Failures	Incomplete
Total	424004747	18761750	0	0
T1	17277	1696	0	0
T2	142674	16791	0	0
T3	156346	208896	0	0
T4	487912	24591	0	0
T5	62103	7426	0	0
T6	34024	704	0	0
T10	285293	9012	0	0
T16	113324	20969	0	0
T17	790	0	0	0
T18	95829	11366	0	0
T24	0	22025	0	0

gen_assert_wmask_bytealign[3].unnamed$$_0

Name	Attempts	Real Successes	Failures	Incomplete
Total	424004747	18761750	0	0
T1	17277	1696	0	0
T2	142674	16791	0	0
T3	156346	208896	0	0
T4	487912	24591	0	0
T5	62103	7426	0	0
T6	34024	704	0	0
T10	285293	9012	0	0
T16	113324	20969	0	0
T17	790	0	0	0
T18	95829	11366	0	0
T24	0	22025	0	0