Module Definition
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Module Instance : tb.dut.u_tlul_adapter.u_rspfifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
89.64 92.86 80.00 85.71 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
78.74 87.18 66.67 61.11 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
94.96 98.57 96.67 100.00 84.62 u_tlul_adapter


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_normal_fifo.u_fifo_cnt 63.15 84.00 60.00 45.45



Module Instance : tb.dut.u_tlul_adapter.u_sramreqfifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
90.93 92.31 71.43 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
78.08 86.84 62.96 62.50 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
94.96 98.57 96.67 100.00 84.62 u_tlul_adapter


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_normal_fifo.u_fifo_cnt 63.15 84.00 60.00 45.45



Module Instance : tb.dut.u_msg_fifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.44 100.00 93.85 100.00 100.00 96.77 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_normal_fifo.u_fifo_cnt 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_tlul_adapter.u_reqfifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
91.36 95.00 87.10 83.33 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
94.96 98.57 96.67 100.00 84.62 u_tlul_adapter


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_normal_fifo.u_fifo_cnt 81.58 92.00 80.00 72.73



Module Instance : tb.dut.u_reg.u_socket.fifo_h.reqfifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 fifo_h


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_reg.u_socket.fifo_h.rspfifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 fifo_h


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 gen_dfifo[0].fifo_d


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 gen_dfifo[0].fifo_d


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 gen_dfifo[1].fifo_d


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 gen_dfifo[1].fifo_d


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Line Coverage for Module : prim_fifo_sync ( parameter Width=36,Pass=1,Depth=32,OutputZeroIfEmpty=1,Secure=0,DepthW=6,gen_normal_fifo.PtrW=5 )
Line Coverage for Module self-instances :
SCORELINE
100.00 100.00
tb.dut.u_msg_fifo

Line No.TotalCoveredPercent
TOTAL1414100.00
ALWAYS6944100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN10011100.00
CONT_ASSIGN10111100.00
CONT_ASSIGN12011100.00
ALWAYS12322100.00
CONT_ASSIGN13011100.00
CONT_ASSIGN13111100.00
CONT_ASSIGN13811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
69 1 1
70 1 1
71 1 1
72 1 1
MISSING_ELSE
81 1 1
82 1 1
100 1 1
101 1 1
120 1 1
123 1 1
124 1 1
MISSING_ELSE
130 1 1
131 1 1
138 1 1


Line Coverage for Module : prim_fifo_sync ( parameter Width=17,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 )
Line Coverage for Module self-instances :
SCORELINE
100.00 100.00
tb.dut.u_tlul_adapter.u_reqfifo

Line No.TotalCoveredPercent
TOTAL1515100.00
ALWAYS6944100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN10011100.00
CONT_ASSIGN10111100.00
CONT_ASSIGN10811100.00
ALWAYS11122100.00
CONT_ASSIGN11611100.00
CONT_ASSIGN13311100.00
CONT_ASSIGN13411100.00
CONT_ASSIGN13811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
69 1 1
70 1 1
71 1 1
72 1 1
MISSING_ELSE
81 1 1
82 1 1
100 1 1
101 1 1
108 1 1
111 1 1
112 1 1
MISSING_ELSE
116 1 1
133 1 1
134 1 1
138 1 1


Line Coverage for Module : prim_fifo_sync ( parameter Width=5,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 )
Line Coverage for Module self-instances :
SCORELINE
90.93 92.31
tb.dut.u_tlul_adapter.u_sramreqfifo

Line No.TotalCoveredPercent
TOTAL151280.00
ALWAYS6944100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN10011100.00
CONT_ASSIGN10111100.00
CONT_ASSIGN108100.00
ALWAYS1112150.00
CONT_ASSIGN11611100.00
CONT_ASSIGN133100.00
CONT_ASSIGN13411100.00
CONT_ASSIGN13811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
69 1 1
70 1 1
71 1 1
72 1 1
MISSING_ELSE
81 1 1
82 1 1
100 1 1
101 1 1
108 0 1
111 1 1
112 0 1
MISSING_ELSE
116 1 1
133 0 1
134 1 1
138 1 1


Line Coverage for Module : prim_fifo_sync ( parameter Width=40,Pass=1,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 )
Line Coverage for Module self-instances :
SCORELINE
89.64 92.86
tb.dut.u_tlul_adapter.u_rspfifo

Line No.TotalCoveredPercent
TOTAL151386.67
ALWAYS6944100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN10011100.00
CONT_ASSIGN10111100.00
CONT_ASSIGN108100.00
ALWAYS1112150.00
CONT_ASSIGN11611100.00
CONT_ASSIGN13011100.00
CONT_ASSIGN13111100.00
CONT_ASSIGN13811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
69 1 1
70 1 1
71 1 1
72 1 1
MISSING_ELSE
81 1 1
82 1 1
100 1 1
101 1 1
108 0 1
111 1 1
112 0 1
MISSING_ELSE
116 1 1
130 1 1
131 1 1
138 1 1


Line Coverage for Module : prim_fifo_sync ( parameter Width=108,Pass=1,Depth=0,OutputZeroIfEmpty=1,Secure=0,DepthW=1 + Width=65,Pass=1,Depth=0,OutputZeroIfEmpty=1,Secure=0,DepthW=1 )
Line Coverage for Module self-instances :
SCORELINE
100.00 100.00
tb.dut.u_reg.u_socket.fifo_h.reqfifo

SCORELINE
100.00 100.00
tb.dut.u_reg.u_socket.fifo_h.rspfifo

SCORELINE
100.00 100.00
tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

SCORELINE
100.00 100.00
tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

SCORELINE
100.00 100.00
tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

SCORELINE
100.00 100.00
tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Line No.TotalCoveredPercent
TOTAL44100.00
CONT_ASSIGN4411100.00
CONT_ASSIGN4511100.00
CONT_ASSIGN4811100.00
CONT_ASSIGN4911100.00
CONT_ASSIGN5300
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
44 1 1
45 1 1
48 1 1
49 1 1
53 unreachable


Cond Coverage for Module : prim_fifo_sync ( parameter Width=5,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 )
Cond Coverage for Module self-instances :
SCORECOND
90.93 71.43
tb.dut.u_tlul_adapter.u_sramreqfifo

TotalCoveredPercent
Conditions16531.25
Logical16531.25
Non-Logical00
Event00

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101Not Covered
110Not Covered
111Not Covered

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011Not Covered
101Not Covered
110Not Covered
111Not Covered

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (5'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------
-1-StatusTests
0Not Covered
1CoveredT1,T2,T3

Cond Coverage for Module : prim_fifo_sync ( parameter Width=36,Pass=1,Depth=32,OutputZeroIfEmpty=1,Secure=0,DepthW=6,gen_normal_fifo.PtrW=5 )
Cond Coverage for Module self-instances :
SCORECOND
100.00 100.00
tb.dut.u_msg_fifo

TotalCoveredPercent
Conditions242083.33
Logical242083.33
Non-Logical00
Event00

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------
-1--2-StatusTests
01CoveredT3,T25,T11
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT2,T3,T5

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT11,T26,T12
110Not Covered
111CoveredT2,T3,T5

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011Not Covered
101CoveredT2,T3,T5
110Not Covered
111CoveredT2,T3,T5

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T5

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---
-1--2-StatusTests
01CoveredT2,T3,T5
10CoveredT1,T2,T3
11CoveredT2,T3,T5

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------
-1--2-StatusTests
01CoveredT2,T3,T5
10CoveredT2,T3,T5
11CoveredT1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (36'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------
-1-StatusTests
0CoveredT2,T3,T5
1CoveredT1,T2,T3

Cond Coverage for Module : prim_fifo_sync ( parameter Width=40,Pass=1,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 )
Cond Coverage for Module self-instances :
SCORECOND
89.64 80.00
tb.dut.u_tlul_adapter.u_rspfifo

TotalCoveredPercent
Conditions24833.33
Logical24833.33
Non-Logical00
Event00

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101Not Covered
110Not Covered
111Not Covered

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011Not Covered
101Not Covered
110Not Covered
111Not Covered

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11Not Covered

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------
-1--2-StatusTests
01Not Covered
10Not Covered
11CoveredT1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (40'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------
-1-StatusTests
0Not Covered
1CoveredT1,T2,T3

Cond Coverage for Module : prim_fifo_sync ( parameter Width=17,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 )
Cond Coverage for Module self-instances :
SCORECOND
100.00 100.00
tb.dut.u_tlul_adapter.u_reqfifo

TotalCoveredPercent
Conditions161168.75
Logical161168.75
Non-Logical00
Event00

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T2,T3

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101Not Covered
110Not Covered
111CoveredT1,T2,T3

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011Not Covered
101CoveredT2,T10,T6
110Not Covered
111CoveredT1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (17'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Branch Coverage for Module : prim_fifo_sync ( parameter Width=36,Pass=1,Depth=32,OutputZeroIfEmpty=1,Secure=0,DepthW=6,gen_normal_fifo.PtrW=5 + Width=40,Pass=1,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 )
Branch Coverage for Module self-instances :
SCOREBRANCH
100.00 100.00
tb.dut.u_msg_fifo

SCOREBRANCH
89.64 85.71
tb.dut.u_tlul_adapter.u_rspfifo

Line No.TotalCoveredPercent
Branches 9 9 100.00
TERNARY 130 2 2 100.00
TERNARY 138 2 2 100.00
IF 69 3 3 100.00
IF 123 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 130 ((gen_normal_fifo.fifo_empty && wvalid_i)) ?

Branches:
-1-StatusTests
1 Covered T2,T3,T5
0 Covered T1,T2,T3


LineNo. Expression -1-: 138 (gen_normal_fifo.empty) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T2,T3,T5


LineNo. Expression -1-: 69 if ((!rst_ni)) -2-: 71 if (gen_normal_fifo.under_rst)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 123 if (gen_normal_fifo.fifo_incr_wptr)

Branches:
-1-StatusTests
1 Covered T2,T3,T5
0 Covered T1,T2,T3


Branch Coverage for Module : prim_fifo_sync ( parameter Width=17,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 + Width=5,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 )
Branch Coverage for Module self-instances :
SCOREBRANCH
100.00 100.00
tb.dut.u_tlul_adapter.u_reqfifo

SCOREBRANCH
90.93 100.00
tb.dut.u_tlul_adapter.u_sramreqfifo

Line No.TotalCoveredPercent
Branches 7 7 100.00
TERNARY 138 2 2 100.00
IF 69 3 3 100.00
IF 111 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 138 (gen_normal_fifo.empty) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 69 if ((!rst_ni)) -2-: 71 if (gen_normal_fifo.under_rst)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 111 if (gen_normal_fifo.fifo_incr_wptr)

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Module : prim_fifo_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 6 6 100.00 6 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 6 6 100.00 6 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 2147483647 524607948 0 0
DepthKnown_A 2147483647 2147483647 0 0
RvalidKnown_A 2147483647 2147483647 0 0
WreadyKnown_A 2147483647 2147483647 0 0
gen_normal_fifo.depthShallNotExceedParamDepth 1696018988 55674467 0 0
gen_passthru_fifo.paramCheckPass 3948 3948 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 524607948 0 0
T1 120939 32664 0 0
T2 1141392 314913 0 0
T3 1250768 3276929 0 0
T4 3903296 663470 0 0
T5 496824 128994 0 0
T6 272192 19991 0 0
T10 2282344 171036 0 0
T16 906592 278712 0 0
T17 6320 48 0 0
T18 766632 211276 0 0
T24 974988 241969 0 0
T27 0 19964 0 0
T28 0 1170 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 172770 172240 0 0
T2 1426740 1426020 0 0
T3 1563460 1562810 0 0
T4 4879120 4878610 0 0
T5 621030 620040 0 0
T6 340240 339580 0 0
T10 2852930 2852180 0 0
T16 1133240 1132400 0 0
T17 7900 7220 0 0
T18 958290 957440 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 172770 172240 0 0
T2 1426740 1426020 0 0
T3 1563460 1562810 0 0
T4 4879120 4878610 0 0
T5 621030 620040 0 0
T6 340240 339580 0 0
T10 2852930 2852180 0 0
T16 1133240 1132400 0 0
T17 7900 7220 0 0
T18 958290 957440 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 172770 172240 0 0
T2 1426740 1426020 0 0
T3 1563460 1562810 0 0
T4 4879120 4878610 0 0
T5 621030 620040 0 0
T6 340240 339580 0 0
T10 2852930 2852180 0 0
T16 1133240 1132400 0 0
T17 7900 7220 0 0
T18 958290 957440 0 0

gen_normal_fifo.depthShallNotExceedParamDepth
NameAttemptsReal SuccessesFailuresIncomplete
Total 1696018988 55674467 0 0
T1 17277 1696 0 0
T2 285348 39109 0 0
T3 312692 465394 0 0
T4 975824 156846 0 0
T5 124206 7838 0 0
T6 68048 2047 0 0
T10 570586 9012 0 0
T16 226648 59612 0 0
T17 1580 0 0 0
T18 191658 25176 0 0
T24 974988 120005 0 0
T27 0 19964 0 0
T28 0 1170 0 0

gen_passthru_fifo.paramCheckPass
NameAttemptsReal SuccessesFailuresIncomplete
Total 3948 3948 0 0
T1 6 6 0 0
T2 6 6 0 0
T3 6 6 0 0
T4 6 6 0 0
T5 6 6 0 0
T6 6 6 0 0
T10 6 6 0 0
T16 6 6 0 0
T17 6 6 0 0
T18 6 6 0 0

Line Coverage for Instance : tb.dut.u_tlul_adapter.u_rspfifo
Line No.TotalCoveredPercent
TOTAL141392.86
ALWAYS6944100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN10011100.00
CONT_ASSIGN10111100.00
CONT_ASSIGN108100.00
ALWAYS11111100.00
CONT_ASSIGN11611100.00
CONT_ASSIGN13011100.00
CONT_ASSIGN13111100.00
CONT_ASSIGN13811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
69 1 1
70 1 1
71 1 1
72 1 1
MISSING_ELSE
81 1 1
82 1 1
100 1 1
101 1 1
108 0 1
111 1 1
112 excluded
Exclude Annotation: VC_COV_UNR
MISSING_ELSE
116 1 1
130 1 1
131 1 1
138 1 1


Cond Coverage for Instance : tb.dut.u_tlul_adapter.u_rspfifo
TotalCoveredPercent
Conditions10880.00
Logical10880.00
Non-Logical00
Event00

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------
-1--2-StatusTestsExclude Annotation
01CoveredT1,T2,T3
10Excluded VC_COV_UNR
11Excluded VC_COV_UNR

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTestsExclude Annotation
011CoveredT1,T2,T3
101Excluded VC_COV_UNR
110Excluded VC_COV_UNR
111Excluded VC_COV_UNR

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTestsExclude Annotation
011Excluded VC_COV_UNR
101Excluded VC_COV_UNR
110Excluded VC_COV_UNR
111Excluded VC_COV_UNR

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------
-1-StatusTestsExclude Annotation
0CoveredT1,T2,T3
1Excluded VC_COV_UNR

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---
-1--2-StatusTestsExclude Annotation
01Excluded VC_COV_UNR
10CoveredT1,T2,T3
11Excluded VC_COV_UNR

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------
-1--2-StatusTestsExclude Annotation
01Excluded VC_COV_UNR
10Excluded VC_COV_UNR
11CoveredT1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (40'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------
-1-StatusTests
0Not Covered
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_tlul_adapter.u_rspfifo
Line No.TotalCoveredPercent
Branches 7 6 85.71
TERNARY 130 1 1 100.00
TERNARY 138 1 1 100.00
IF 69 3 3 100.00
IF 123 2 1 50.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 130 ((gen_normal_fifo.fifo_empty && wvalid_i)) ?

Branches:
-1-StatusTestsExclude Annotation
1 Excluded VC_COV_UNR
0 Covered T1,T2,T3


LineNo. Expression -1-: 138 (gen_normal_fifo.empty) ?

Branches:
-1-StatusTestsExclude Annotation
1 Covered T1,T2,T3
0 Excluded VC_COV_UNR


LineNo. Expression -1-: 69 if ((!rst_ni)) -2-: 71 if (gen_normal_fifo.under_rst)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 123 if (gen_normal_fifo.fifo_incr_wptr)

Branches:
-1-StatusTests
1 Not Covered
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_tlul_adapter.u_rspfifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncompleteExclusionExclude Annotation
DataKnown_A Excluded [UNSUPPORTED] excluded by fpv
DepthKnown_A 424004747 423939465 0 0
RvalidKnown_A 424004747 423939465 0 0
WreadyKnown_A 424004747 423939465 0 0
gen_normal_fifo.depthShallNotExceedParamDepth Excluded [UNSUPPORTED] excluded by fpv


DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 424004747 423939465 0 0
T1 17277 17224 0 0
T2 142674 142602 0 0
T3 156346 156281 0 0
T4 487912 487861 0 0
T5 62103 62004 0 0
T6 34024 33958 0 0
T10 285293 285218 0 0
T16 113324 113240 0 0
T17 790 722 0 0
T18 95829 95744 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 424004747 423939465 0 0
T1 17277 17224 0 0
T2 142674 142602 0 0
T3 156346 156281 0 0
T4 487912 487861 0 0
T5 62103 62004 0 0
T6 34024 33958 0 0
T10 285293 285218 0 0
T16 113324 113240 0 0
T17 790 722 0 0
T18 95829 95744 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 424004747 423939465 0 0
T1 17277 17224 0 0
T2 142674 142602 0 0
T3 156346 156281 0 0
T4 487912 487861 0 0
T5 62103 62004 0 0
T6 34024 33958 0 0
T10 285293 285218 0 0
T16 113324 113240 0 0
T17 790 722 0 0
T18 95829 95744 0 0

Line Coverage for Instance : tb.dut.u_tlul_adapter.u_sramreqfifo
Line No.TotalCoveredPercent
TOTAL131292.31
ALWAYS6944100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN10011100.00
CONT_ASSIGN10111100.00
CONT_ASSIGN10800
ALWAYS11111100.00
CONT_ASSIGN11611100.00
CONT_ASSIGN133100.00
CONT_ASSIGN13411100.00
CONT_ASSIGN13811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
69 1 1
70 1 1
71 1 1
72 1 1
MISSING_ELSE
81 1 1
82 1 1
100 1 1
101 1 1
108 excluded
Exclude Annotation: [UNR] Pass is always '1'
111 1 1
112 excluded
Exclude Annotation: VC_COV_UNR
MISSING_ELSE
116 1 1
133 0 1
134 1 1
138 1 1


Cond Coverage for Instance : tb.dut.u_tlul_adapter.u_sramreqfifo
TotalCoveredPercent
Conditions7571.43
Logical7571.43
Non-Logical00
Event00

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------
-1--2-StatusTestsExclude Annotation
01CoveredT1,T2,T3
10Excluded VC_COV_UNR
11Excluded VC_COV_UNR

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTestsExclude Annotation
011CoveredT1,T2,T3
101Excluded VC_COV_UNR
110Excluded VC_COV_UNR
111Excluded VC_COV_UNR

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTestsExclude Annotation
011Excluded VC_COV_UNR
101Excluded VC_COV_UNR
110Excluded VC_COV_UNR
111Excluded VC_COV_UNR

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (5'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------
-1-StatusTests
0Not Covered
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_tlul_adapter.u_sramreqfifo
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 138 1 1 100.00
IF 69 3 3 100.00
IF 111 1 1 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 138 (gen_normal_fifo.empty) ?

Branches:
-1-StatusTestsExclude Annotation
1 Covered T1,T2,T3
0 Excluded VC_COV_UNR


LineNo. Expression -1-: 69 if ((!rst_ni)) -2-: 71 if (gen_normal_fifo.under_rst)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 111 if (gen_normal_fifo.fifo_incr_wptr)

Branches:
-1-StatusTestsExclude Annotation
1 Excluded VC_COV_UNR
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_tlul_adapter.u_sramreqfifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncompleteExclusionExclude Annotation
DataKnown_A Excluded [UNSUPPORTED] excluded by fpv
DepthKnown_A 424004747 423939465 0 0
RvalidKnown_A 424004747 423939465 0 0
WreadyKnown_A 424004747 423939465 0 0
gen_normal_fifo.depthShallNotExceedParamDepth Excluded [UNSUPPORTED] excluded by fpv


DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 424004747 423939465 0 0
T1 17277 17224 0 0
T2 142674 142602 0 0
T3 156346 156281 0 0
T4 487912 487861 0 0
T5 62103 62004 0 0
T6 34024 33958 0 0
T10 285293 285218 0 0
T16 113324 113240 0 0
T17 790 722 0 0
T18 95829 95744 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 424004747 423939465 0 0
T1 17277 17224 0 0
T2 142674 142602 0 0
T3 156346 156281 0 0
T4 487912 487861 0 0
T5 62103 62004 0 0
T6 34024 33958 0 0
T10 285293 285218 0 0
T16 113324 113240 0 0
T17 790 722 0 0
T18 95829 95744 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 424004747 423939465 0 0
T1 17277 17224 0 0
T2 142674 142602 0 0
T3 156346 156281 0 0
T4 487912 487861 0 0
T5 62103 62004 0 0
T6 34024 33958 0 0
T10 285293 285218 0 0
T16 113324 113240 0 0
T17 790 722 0 0
T18 95829 95744 0 0

Line Coverage for Instance : tb.dut.u_msg_fifo
Line No.TotalCoveredPercent
TOTAL1414100.00
ALWAYS6944100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN10011100.00
CONT_ASSIGN10111100.00
CONT_ASSIGN12011100.00
ALWAYS12322100.00
CONT_ASSIGN13011100.00
CONT_ASSIGN13111100.00
CONT_ASSIGN13811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
69 1 1
70 1 1
71 1 1
72 1 1
MISSING_ELSE
81 1 1
82 1 1
100 1 1
101 1 1
120 1 1
123 1 1
124 1 1
MISSING_ELSE
130 1 1
131 1 1
138 1 1


Cond Coverage for Instance : tb.dut.u_msg_fifo
TotalCoveredPercent
Conditions2020100.00
Logical2020100.00
Non-Logical00
Event00

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------
-1--2-StatusTests
01CoveredT3,T25,T11
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------
-1--2-StatusTestsExclude Annotation
01CoveredT1,T2,T3
10Excluded VC_COV_UNR
11CoveredT2,T3,T5

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTestsExclude Annotation
011CoveredT1,T2,T3
101CoveredT11,T26,T12
110Excluded VC_COV_UNR
111CoveredT2,T3,T5

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTestsExclude Annotation
011Excluded VC_COV_UNR
101CoveredT2,T3,T5
110Excluded VC_COV_UNR
111CoveredT2,T3,T5

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T5

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---
-1--2-StatusTests
01CoveredT2,T3,T5
10CoveredT1,T2,T3
11CoveredT2,T3,T5

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------
-1--2-StatusTests
01CoveredT2,T3,T5
10CoveredT2,T3,T5
11CoveredT1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (36'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------
-1-StatusTests
0CoveredT2,T3,T5
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_msg_fifo
Line No.TotalCoveredPercent
Branches 9 9 100.00
TERNARY 130 2 2 100.00
TERNARY 138 2 2 100.00
IF 69 3 3 100.00
IF 123 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 130 ((gen_normal_fifo.fifo_empty && wvalid_i)) ?

Branches:
-1-StatusTests
1 Covered T2,T3,T5
0 Covered T1,T2,T3


LineNo. Expression -1-: 138 (gen_normal_fifo.empty) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T2,T3,T5


LineNo. Expression -1-: 69 if ((!rst_ni)) -2-: 71 if (gen_normal_fifo.under_rst)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 123 if (gen_normal_fifo.fifo_incr_wptr)

Branches:
-1-StatusTests
1 Covered T2,T3,T5
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_msg_fifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 424004747 22443005 0 0
DepthKnown_A 424004747 423939465 0 0
RvalidKnown_A 424004747 423939465 0 0
WreadyKnown_A 424004747 423939465 0 0
gen_normal_fifo.depthShallNotExceedParamDepth 424004747 22443005 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 424004747 22443005 0 0
T2 142674 22318 0 0
T3 156346 256498 0 0
T4 487912 45092 0 0
T5 62103 412 0 0
T6 34024 1343 0 0
T10 285293 0 0 0
T16 113324 38643 0 0
T17 790 0 0 0
T18 95829 13810 0 0
T24 974988 20066 0 0
T27 0 19964 0 0
T28 0 1170 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 424004747 423939465 0 0
T1 17277 17224 0 0
T2 142674 142602 0 0
T3 156346 156281 0 0
T4 487912 487861 0 0
T5 62103 62004 0 0
T6 34024 33958 0 0
T10 285293 285218 0 0
T16 113324 113240 0 0
T17 790 722 0 0
T18 95829 95744 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 424004747 423939465 0 0
T1 17277 17224 0 0
T2 142674 142602 0 0
T3 156346 156281 0 0
T4 487912 487861 0 0
T5 62103 62004 0 0
T6 34024 33958 0 0
T10 285293 285218 0 0
T16 113324 113240 0 0
T17 790 722 0 0
T18 95829 95744 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 424004747 423939465 0 0
T1 17277 17224 0 0
T2 142674 142602 0 0
T3 156346 156281 0 0
T4 487912 487861 0 0
T5 62103 62004 0 0
T6 34024 33958 0 0
T10 285293 285218 0 0
T16 113324 113240 0 0
T17 790 722 0 0
T18 95829 95744 0 0

gen_normal_fifo.depthShallNotExceedParamDepth
NameAttemptsReal SuccessesFailuresIncomplete
Total 424004747 22443005 0 0
T2 142674 22318 0 0
T3 156346 256498 0 0
T4 487912 45092 0 0
T5 62103 412 0 0
T6 34024 1343 0 0
T10 285293 0 0 0
T16 113324 38643 0 0
T17 790 0 0 0
T18 95829 13810 0 0
T24 974988 20066 0 0
T27 0 19964 0 0
T28 0 1170 0 0

Line Coverage for Instance : tb.dut.u_tlul_adapter.u_reqfifo
Line No.TotalCoveredPercent
TOTAL1515100.00
ALWAYS6944100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN10011100.00
CONT_ASSIGN10111100.00
CONT_ASSIGN10811100.00
ALWAYS11122100.00
CONT_ASSIGN11611100.00
CONT_ASSIGN13311100.00
CONT_ASSIGN13411100.00
CONT_ASSIGN13811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
69 1 1
70 1 1
71 1 1
72 1 1
MISSING_ELSE
81 1 1
82 1 1
100 1 1
101 1 1
108 1 1
111 1 1
112 1 1
MISSING_ELSE
116 1 1
133 1 1
134 1 1
138 1 1


Cond Coverage for Instance : tb.dut.u_tlul_adapter.u_reqfifo
TotalCoveredPercent
Conditions1111100.00
Logical1111100.00
Non-Logical00
Event00

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------
-1--2-StatusTestsExclude Annotation
01CoveredT1,T2,T3
10Excluded VC_COV_UNR
11CoveredT1,T2,T3

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTestsExclude Annotation
011CoveredT1,T2,T3
101Excluded VC_COV_UNR
110Excluded VC_COV_UNR
111CoveredT1,T2,T3

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTestsExclude Annotation
011Excluded VC_COV_UNR
101CoveredT2,T10,T6
110Excluded VC_COV_UNR
111CoveredT1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (17'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_tlul_adapter.u_reqfifo
Line No.TotalCoveredPercent
Branches 7 7 100.00
TERNARY 138 2 2 100.00
IF 69 3 3 100.00
IF 111 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 138 (gen_normal_fifo.empty) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 69 if ((!rst_ni)) -2-: 71 if (gen_normal_fifo.under_rst)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 111 if (gen_normal_fifo.fifo_incr_wptr)

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_tlul_adapter.u_reqfifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 424004747 33231462 0 0
DepthKnown_A 424004747 423939465 0 0
RvalidKnown_A 424004747 423939465 0 0
WreadyKnown_A 424004747 423939465 0 0
gen_normal_fifo.depthShallNotExceedParamDepth 424004747 33231462 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 424004747 33231462 0 0
T1 17277 1696 0 0
T2 142674 16791 0 0
T3 156346 208896 0 0
T4 487912 111754 0 0
T5 62103 7426 0 0
T6 34024 704 0 0
T10 285293 9012 0 0
T16 113324 20969 0 0
T17 790 0 0 0
T18 95829 11366 0 0
T24 0 99939 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 424004747 423939465 0 0
T1 17277 17224 0 0
T2 142674 142602 0 0
T3 156346 156281 0 0
T4 487912 487861 0 0
T5 62103 62004 0 0
T6 34024 33958 0 0
T10 285293 285218 0 0
T16 113324 113240 0 0
T17 790 722 0 0
T18 95829 95744 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 424004747 423939465 0 0
T1 17277 17224 0 0
T2 142674 142602 0 0
T3 156346 156281 0 0
T4 487912 487861 0 0
T5 62103 62004 0 0
T6 34024 33958 0 0
T10 285293 285218 0 0
T16 113324 113240 0 0
T17 790 722 0 0
T18 95829 95744 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 424004747 423939465 0 0
T1 17277 17224 0 0
T2 142674 142602 0 0
T3 156346 156281 0 0
T4 487912 487861 0 0
T5 62103 62004 0 0
T6 34024 33958 0 0
T10 285293 285218 0 0
T16 113324 113240 0 0
T17 790 722 0 0
T18 95829 95744 0 0

gen_normal_fifo.depthShallNotExceedParamDepth
NameAttemptsReal SuccessesFailuresIncomplete
Total 424004747 33231462 0 0
T1 17277 1696 0 0
T2 142674 16791 0 0
T3 156346 208896 0 0
T4 487912 111754 0 0
T5 62103 7426 0 0
T6 34024 704 0 0
T10 285293 9012 0 0
T16 113324 20969 0 0
T17 790 0 0 0
T18 95829 11366 0 0
T24 0 99939 0 0

Line Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.reqfifo
Line No.TotalCoveredPercent
TOTAL44100.00
CONT_ASSIGN4411100.00
CONT_ASSIGN4511100.00
CONT_ASSIGN4811100.00
CONT_ASSIGN4911100.00
CONT_ASSIGN5300
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
44 1 1
45 1 1
48 1 1
49 1 1
53 unreachable


Assert Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.reqfifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 448354292 96754843 0 0
DepthKnown_A 448354292 448250163 0 0
RvalidKnown_A 448354292 448250163 0 0
WreadyKnown_A 448354292 448250163 0 0
gen_passthru_fifo.paramCheckPass 658 658 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 448354292 96754843 0 0
T1 17277 7742 0 0
T2 142674 68951 0 0
T3 156346 702895 0 0
T4 487912 45873 0 0
T5 62103 30289 0 0
T6 34024 4486 0 0
T10 285293 40506 0 0
T16 113324 54775 0 0
T17 790 12 0 0
T18 95829 46525 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 448354292 448250163 0 0
T1 17277 17224 0 0
T2 142674 142602 0 0
T3 156346 156281 0 0
T4 487912 487861 0 0
T5 62103 62004 0 0
T6 34024 33958 0 0
T10 285293 285218 0 0
T16 113324 113240 0 0
T17 790 722 0 0
T18 95829 95744 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 448354292 448250163 0 0
T1 17277 17224 0 0
T2 142674 142602 0 0
T3 156346 156281 0 0
T4 487912 487861 0 0
T5 62103 62004 0 0
T6 34024 33958 0 0
T10 285293 285218 0 0
T16 113324 113240 0 0
T17 790 722 0 0
T18 95829 95744 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 448354292 448250163 0 0
T1 17277 17224 0 0
T2 142674 142602 0 0
T3 156346 156281 0 0
T4 487912 487861 0 0
T5 62103 62004 0 0
T6 34024 33958 0 0
T10 285293 285218 0 0
T16 113324 113240 0 0
T17 790 722 0 0
T18 95829 95744 0 0

gen_passthru_fifo.paramCheckPass
NameAttemptsReal SuccessesFailuresIncomplete
Total 658 658 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T10 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0

Line Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.rspfifo
Line No.TotalCoveredPercent
TOTAL44100.00
CONT_ASSIGN4411100.00
CONT_ASSIGN4511100.00
CONT_ASSIGN4811100.00
CONT_ASSIGN4911100.00
CONT_ASSIGN5300
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
44 1 1
45 1 1
48 1 1
49 1 1
53 unreachable


Assert Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.rspfifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 448354292 139738461 0 0
DepthKnown_A 448354292 448250163 0 0
RvalidKnown_A 448354292 448250163 0 0
WreadyKnown_A 448354292 448250163 0 0
gen_passthru_fifo.paramCheckPass 658 658 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 448354292 139738461 0 0
T1 17277 7742 0 0
T2 142674 68951 0 0
T3 156346 702873 0 0
T4 487912 207439 0 0
T5 62103 30289 0 0
T6 34024 4486 0 0
T10 285293 40506 0 0
T16 113324 54775 0 0
T17 790 12 0 0
T18 95829 46525 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 448354292 448250163 0 0
T1 17277 17224 0 0
T2 142674 142602 0 0
T3 156346 156281 0 0
T4 487912 487861 0 0
T5 62103 62004 0 0
T6 34024 33958 0 0
T10 285293 285218 0 0
T16 113324 113240 0 0
T17 790 722 0 0
T18 95829 95744 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 448354292 448250163 0 0
T1 17277 17224 0 0
T2 142674 142602 0 0
T3 156346 156281 0 0
T4 487912 487861 0 0
T5 62103 62004 0 0
T6 34024 33958 0 0
T10 285293 285218 0 0
T16 113324 113240 0 0
T17 790 722 0 0
T18 95829 95744 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 448354292 448250163 0 0
T1 17277 17224 0 0
T2 142674 142602 0 0
T3 156346 156281 0 0
T4 487912 487861 0 0
T5 62103 62004 0 0
T6 34024 33958 0 0
T10 285293 285218 0 0
T16 113324 113240 0 0
T17 790 722 0 0
T18 95829 95744 0 0

gen_passthru_fifo.paramCheckPass
NameAttemptsReal SuccessesFailuresIncomplete
Total 658 658 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T10 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo
Line No.TotalCoveredPercent
TOTAL44100.00
CONT_ASSIGN4411100.00
CONT_ASSIGN4511100.00
CONT_ASSIGN4811100.00
CONT_ASSIGN4911100.00
CONT_ASSIGN5300
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
44 1 1
45 1 1
48 1 1
49 1 1
53 unreachable


Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 448354292 24114789 0 0
DepthKnown_A 448354292 448250163 0 0
RvalidKnown_A 448354292 448250163 0 0
WreadyKnown_A 448354292 448250163 0 0
gen_passthru_fifo.paramCheckPass 658 658 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 448354292 24114789 0 0
T1 17277 1696 0 0
T2 142674 16791 0 0
T3 156346 208896 0 0
T4 487912 24591 0 0
T5 62103 7426 0 0
T6 34024 704 0 0
T10 285293 9012 0 0
T16 113324 20969 0 0
T17 790 0 0 0
T18 95829 11366 0 0
T24 0 22025 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 448354292 448250163 0 0
T1 17277 17224 0 0
T2 142674 142602 0 0
T3 156346 156281 0 0
T4 487912 487861 0 0
T5 62103 62004 0 0
T6 34024 33958 0 0
T10 285293 285218 0 0
T16 113324 113240 0 0
T17 790 722 0 0
T18 95829 95744 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 448354292 448250163 0 0
T1 17277 17224 0 0
T2 142674 142602 0 0
T3 156346 156281 0 0
T4 487912 487861 0 0
T5 62103 62004 0 0
T6 34024 33958 0 0
T10 285293 285218 0 0
T16 113324 113240 0 0
T17 790 722 0 0
T18 95829 95744 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 448354292 448250163 0 0
T1 17277 17224 0 0
T2 142674 142602 0 0
T3 156346 156281 0 0
T4 487912 487861 0 0
T5 62103 62004 0 0
T6 34024 33958 0 0
T10 285293 285218 0 0
T16 113324 113240 0 0
T17 790 722 0 0
T18 95829 95744 0 0

gen_passthru_fifo.paramCheckPass
NameAttemptsReal SuccessesFailuresIncomplete
Total 658 658 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T10 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo
Line No.TotalCoveredPercent
TOTAL44100.00
CONT_ASSIGN4411100.00
CONT_ASSIGN4511100.00
CONT_ASSIGN4811100.00
CONT_ASSIGN4911100.00
CONT_ASSIGN5300
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
44 1 1
45 1 1
48 1 1
49 1 1
53 unreachable


Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 448354292 35863457 0 0
DepthKnown_A 448354292 448250163 0 0
RvalidKnown_A 448354292 448250163 0 0
WreadyKnown_A 448354292 448250163 0 0
gen_passthru_fifo.paramCheckPass 658 658 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 448354292 35863457 0 0
T1 17277 1696 0 0
T2 142674 16791 0 0
T3 156346 208896 0 0
T4 487912 111754 0 0
T5 62103 7426 0 0
T6 34024 704 0 0
T10 285293 9012 0 0
T16 113324 20969 0 0
T17 790 0 0 0
T18 95829 11366 0 0
T24 0 99939 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 448354292 448250163 0 0
T1 17277 17224 0 0
T2 142674 142602 0 0
T3 156346 156281 0 0
T4 487912 487861 0 0
T5 62103 62004 0 0
T6 34024 33958 0 0
T10 285293 285218 0 0
T16 113324 113240 0 0
T17 790 722 0 0
T18 95829 95744 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 448354292 448250163 0 0
T1 17277 17224 0 0
T2 142674 142602 0 0
T3 156346 156281 0 0
T4 487912 487861 0 0
T5 62103 62004 0 0
T6 34024 33958 0 0
T10 285293 285218 0 0
T16 113324 113240 0 0
T17 790 722 0 0
T18 95829 95744 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 448354292 448250163 0 0
T1 17277 17224 0 0
T2 142674 142602 0 0
T3 156346 156281 0 0
T4 487912 487861 0 0
T5 62103 62004 0 0
T6 34024 33958 0 0
T10 285293 285218 0 0
T16 113324 113240 0 0
T17 790 722 0 0
T18 95829 95744 0 0

gen_passthru_fifo.paramCheckPass
NameAttemptsReal SuccessesFailuresIncomplete
Total 658 658 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T10 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo
Line No.TotalCoveredPercent
TOTAL44100.00
CONT_ASSIGN4411100.00
CONT_ASSIGN4511100.00
CONT_ASSIGN4811100.00
CONT_ASSIGN4911100.00
CONT_ASSIGN5300
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
44 1 1
45 1 1
48 1 1
49 1 1
53 unreachable


Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 448354292 68586927 0 0
DepthKnown_A 448354292 448250163 0 0
RvalidKnown_A 448354292 448250163 0 0
WreadyKnown_A 448354292 448250163 0 0
gen_passthru_fifo.paramCheckPass 658 658 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 448354292 68586927 0 0
T1 17277 6046 0 0
T2 142674 52160 0 0
T3 156346 493998 0 0
T4 487912 21282 0 0
T5 62103 22863 0 0
T6 34024 3782 0 0
T10 285293 31494 0 0
T16 113324 33806 0 0
T17 790 12 0 0
T18 95829 35159 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 448354292 448250163 0 0
T1 17277 17224 0 0
T2 142674 142602 0 0
T3 156346 156281 0 0
T4 487912 487861 0 0
T5 62103 62004 0 0
T6 34024 33958 0 0
T10 285293 285218 0 0
T16 113324 113240 0 0
T17 790 722 0 0
T18 95829 95744 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 448354292 448250163 0 0
T1 17277 17224 0 0
T2 142674 142602 0 0
T3 156346 156281 0 0
T4 487912 487861 0 0
T5 62103 62004 0 0
T6 34024 33958 0 0
T10 285293 285218 0 0
T16 113324 113240 0 0
T17 790 722 0 0
T18 95829 95744 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 448354292 448250163 0 0
T1 17277 17224 0 0
T2 142674 142602 0 0
T3 156346 156281 0 0
T4 487912 487861 0 0
T5 62103 62004 0 0
T6 34024 33958 0 0
T10 285293 285218 0 0
T16 113324 113240 0 0
T17 790 722 0 0
T18 95829 95744 0 0

gen_passthru_fifo.paramCheckPass
NameAttemptsReal SuccessesFailuresIncomplete
Total 658 658 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T10 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo
Line No.TotalCoveredPercent
TOTAL44100.00
CONT_ASSIGN4411100.00
CONT_ASSIGN4511100.00
CONT_ASSIGN4811100.00
CONT_ASSIGN4911100.00
CONT_ASSIGN5300
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
44 1 1
45 1 1
48 1 1
49 1 1
53 unreachable


Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 448354292 103875004 0 0
DepthKnown_A 448354292 448250163 0 0
RvalidKnown_A 448354292 448250163 0 0
WreadyKnown_A 448354292 448250163 0 0
gen_passthru_fifo.paramCheckPass 658 658 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 448354292 103875004 0 0
T1 17277 6046 0 0
T2 142674 52160 0 0
T3 156346 493977 0 0
T4 487912 95685 0 0
T5 62103 22863 0 0
T6 34024 3782 0 0
T10 285293 31494 0 0
T16 113324 33806 0 0
T17 790 12 0 0
T18 95829 35159 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 448354292 448250163 0 0
T1 17277 17224 0 0
T2 142674 142602 0 0
T3 156346 156281 0 0
T4 487912 487861 0 0
T5 62103 62004 0 0
T6 34024 33958 0 0
T10 285293 285218 0 0
T16 113324 113240 0 0
T17 790 722 0 0
T18 95829 95744 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 448354292 448250163 0 0
T1 17277 17224 0 0
T2 142674 142602 0 0
T3 156346 156281 0 0
T4 487912 487861 0 0
T5 62103 62004 0 0
T6 34024 33958 0 0
T10 285293 285218 0 0
T16 113324 113240 0 0
T17 790 722 0 0
T18 95829 95744 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 448354292 448250163 0 0
T1 17277 17224 0 0
T2 142674 142602 0 0
T3 156346 156281 0 0
T4 487912 487861 0 0
T5 62103 62004 0 0
T6 34024 33958 0 0
T10 285293 285218 0 0
T16 113324 113240 0 0
T17 790 722 0 0
T18 95829 95744 0 0

gen_passthru_fifo.paramCheckPass
NameAttemptsReal SuccessesFailuresIncomplete
Total 658 658 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T10 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%