Unified Coverage Report :: Module :: hmac_core

Module : hmac_core

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.68	99.41	93.90		100.00	93.41

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_hmac_0.1/rtl/hmac_core.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_hmac	96.68	99.41	93.90		100.00	93.41

---

Module Instance : tb.dut.u_hmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.68	99.41	93.90		100.00	93.41

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.68	99.41	93.90		100.00	93.41

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.44	100.00	93.85	100.00	100.00	96.77	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : hmac_core

	Line No.	Total	Covered	Percent
TOTAL		170	169	99.41
CONT_ASSIGN	120	1	1	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	123	1	1	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
CONT_ASSIGN	127	1	1	100.00
ALWAYS	132	25	25	100.00
CONT_ASSIGN	189	1	1	100.00
CONT_ASSIGN	191	1	1	100.00
CONT_ASSIGN	192	1	1	100.00
ALWAYS	208	16	15	93.75
CONT_ASSIGN	232	1	1	100.00
ALWAYS	235	5	5	100.00
CONT_ASSIGN	245	1	1	100.00
ALWAYS	253	10	10	100.00
ALWAYS	271	3	3	100.00
ALWAYS	277	6	6	100.00
ALWAYS	287	4	4	100.00
ALWAYS	295	6	6	100.00
CONT_ASSIGN	304	1	1	100.00
ALWAYS	307	3	3	100.00
ALWAYS	312	71	71	100.00
CONT_ASSIGN	458	1	1	100.00
ALWAYS	463	3	3	100.00
CONT_ASSIGN	471	1	1	100.00
CONT_ASSIGN	482	1	1	100.00
ALWAYS	485	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_hmac_0.1/rtl/hmac_core.sv' or '../src/lowrisc_ip_hmac_0.1/rtl/hmac_core.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
120	1	1
121	1	1
123	1	1
124	1	1
126	1	1
127	1	1
132	1	1
133	1	1
134	1	1
135	1	1
137	1	1
139	1	1
141	1	1
143	1	1
145	1	1
149	1	1
151	1	1
153	1	1
155	1	1
159	1	1
161	1	1
163	1	1
165	1	1
169	1	1
170	1	1
172	1	1
173	1	1
178	1	1
179	1	1
181	1	1
182	1	1
189	1	1
191	1	1
192	1	1
208	1	1
209	1	1
210	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
219	1	1
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
226	1	1
			==> MISSING_ELSE
229	0	1
232	1	1
235	1	1
237	1	1
238	1	1
239	1	1
240	1	1
245	1	1
253	1	1
254	1	1
255	1	1
256	1	1
259	1	1
260	1	1
261	1	1
262	1	1
265	1	1
266	1	1
			MISSING_ELSE
271	2	2
272	1	1
277	1	1
278	1	1
279	1	1
280	1	1
281	1	1
282	1	1
			MISSING_ELSE
287	1	1
288	1	1
289	1	1
290	1	1
			MISSING_ELSE
295	1	1
296	1	1
297	1	1
298	1	1
299	1	1
300	1	1
			==> MISSING_ELSE
304	1	1
307	2	2
308	1	1
312	1	1
313	1	1
314	1	1
315	1	1
316	1	1
317	1	1
318	1	1
319	1	1
320	1	1
321	1	1
322	1	1
323	1	1
324	1	1
325	1	1
327	1	1
332	1	1
333	1	1
334	1	1
335	1	1
337	1	1
338	1	1
339	1	1
340	1	1
342	1	1
343	1	1
345	1	1
350	1	1
352	1	1
353	1	1
355	1	1
357	1	1
359	1	1
364	1	1
365	1	1
367	1	1
369	1	1
371	1	1
372	1	1
373	1	1
378	1	1
380	1	1
382	1	1
383	1	1
388	1	1
390	1	1
391	1	1
392	1	1
394	1	1
395	1	1
397	1	1
401	1	1
406	1	1
407	1	1
408	1	1
409	1	1
411	1	1
415	1	1
417	1	1
418	1	1
419	1	1
420	1	1
422	1	1
428	1	1
429	1	1
431	1	1
432	1	1
434	1	1
436	1	1
438	1	1
444	1	1
446	1	1
458	1	1
463	1	1
464	1	1
466	1	1
471	1	1
482	1	1
485	1	1
486	1	1
488	1	1

---

Cond Coverage for Module : hmac_core

	Total	Covered	Percent
Conditions	213	200	93.90
Logical	213	200	93.90
Non-Logical	0	0
Event	0	0

 LINE       120
 EXPRESSION (hmac_en_i ? hash_start : reg_hash_start_i)
             ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       121
 EXPRESSION (hmac_en_i ? hash_continue : reg_hash_continue_i)
             ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       123
 EXPRESSION (hmac_en_i ? (reg_hash_process_i | hash_process) : reg_hash_process_i)
             ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       123
 SUB-EXPRESSION (reg_hash_process_i | hash_process)
                 ---------1--------   ------2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T5
1	0	Covered	T2,T3,T5

 LINE       124
 EXPRESSION (hmac_en_i ? hmac_hash_done : sha_hash_done_i)
             ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       189
 EXPRESSION (hmac_en_i ? ((st_q == StMsg) & sha_rready_i) : sha_rready_i)
             ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       189
 SUB-EXPRESSION ((st_q == StMsg) & sha_rready_i)
                 -------1-------   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T5
1	0	Covered	T2,T3,T5
1	1	Covered	T2,T3,T5

 LINE       189
 SUB-EXPRESSION (st_q == StMsg)
                -------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T5

 LINE       191
 EXPRESSION (((!hmac_en_i)) ? fifo_rvalid_i : hmac_sha_rvalid)
             -------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       192
 EXPRESSION 
 Number  Term
      1  ((!hmac_en_i)) ? fifo_rdata_i : (((sel_rdata == SelIPad) && (digest_size_i == SHA2_256)) ? ('{data:i_pad_256[((BlockSizeSHA256 - 1) - (32 * pad_index_256))-:32], mask:'1}) : (((sel_rdata == SelIPad) && ((digest_size_i == SHA2_384) || (digest_size_i == SHA2_512))) ? ('{data:i_pad_512[((BlockSizeSHA512 - 1) - (32 * pad_index_512))-:32], mask:'1}) : (((sel_rdata == SelOPad) && (digest_size_i == SHA2_256)) ? ('{data:o_pad_256[((BlockSizeSHA256 - 1) - (32 * pad_index_256))-:32], mask:'1}) : (((sel_rdata == SelOPad) && ((digest_size_i == SHA2_384) || (digest_size_i == SHA2_512))) ? ('{data:o_pad_512[((BlockSizeSHA512 - 1) - (32 * pad_index_512))-:32], mask:'1}) : ((sel_rdata == SelFifo) ? fifo_rdata_i : ('{(*adjust*)default:'0, (*adjust*)default:'0})))))))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       192
 SUB-EXPRESSION 
 Number  Term
      1  ((sel_rdata == SelIPad) && (digest_size_i == SHA2_256)) ? ('{data:i_pad_256[((BlockSizeSHA256 - 1) - (32 * pad_index_256))-:32], mask:'1}) : (((sel_rdata == SelIPad) && ((digest_size_i == SHA2_384) || (digest_size_i == SHA2_512))) ? ('{data:i_pad_512[((BlockSizeSHA512 - 1) - (32 * pad_index_512))-:32], mask:'1}) : (((sel_rdata == SelOPad) && (digest_size_i == SHA2_256)) ? ('{data:o_pad_256[((BlockSizeSHA256 - 1) - (32 * pad_index_256))-:32], mask:'1}) : (((sel_rdata == SelOPad) && ((digest_size_i == SHA2_384) || (digest_size_i == SHA2_512))) ? ('{data:o_pad_512[((BlockSizeSHA512 - 1) - (32 * pad_index_512))-:32], mask:'1}) : ((sel_rdata == SelFifo) ? fifo_rdata_i : ('{(*adjust*)default:'0, (*adjust*)default:'0}))))))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T5

 LINE       192
 SUB-EXPRESSION ((sel_rdata == SelIPad) && (digest_size_i == SHA2_256))
                 -----------1----------    -------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T5
1	1	Covered	T2,T3,T5

 LINE       192
 SUB-EXPRESSION (sel_rdata == SelIPad)
                -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T5

 LINE       192
 SUB-EXPRESSION (digest_size_i == SHA2_256)
                -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       192
 SUB-EXPRESSION 
 Number  Term
      1  ((sel_rdata == SelIPad) && ((digest_size_i == SHA2_384) || (digest_size_i == SHA2_512))) ? ('{data:i_pad_512[((BlockSizeSHA512 - 1) - (32 * pad_index_512))-:32], mask:'1}) : (((sel_rdata == SelOPad) && (digest_size_i == SHA2_256)) ? ('{data:o_pad_256[((BlockSizeSHA256 - 1) - (32 * pad_index_256))-:32], mask:'1}) : (((sel_rdata == SelOPad) && ((digest_size_i == SHA2_384) || (digest_size_i == SHA2_512))) ? ('{data:o_pad_512[((BlockSizeSHA512 - 1) - (32 * pad_index_512))-:32], mask:'1}) : ((sel_rdata == SelFifo) ? fifo_rdata_i : ('{(*adjust*)default:'0, (*adjust*)default:'0})))))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T5

 LINE       192
 SUB-EXPRESSION ((sel_rdata == SelIPad) && ((digest_size_i == SHA2_384) || (digest_size_i == SHA2_512)))
                 -----------1----------    ------------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T5

 LINE       192
 SUB-EXPRESSION (sel_rdata == SelIPad)
                -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T5

 LINE       192
 SUB-EXPRESSION ((digest_size_i == SHA2_384) || (digest_size_i == SHA2_512))
                 -------------1-------------    -------------2-------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T10

 LINE       192
 SUB-EXPRESSION (digest_size_i == SHA2_384)
                -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T10

 LINE       192
 SUB-EXPRESSION (digest_size_i == SHA2_512)
                -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       192
 SUB-EXPRESSION 
 Number  Term
      1  ((sel_rdata == SelOPad) && (digest_size_i == SHA2_256)) ? ('{data:o_pad_256[((BlockSizeSHA256 - 1) - (32 * pad_index_256))-:32], mask:'1}) : (((sel_rdata == SelOPad) && ((digest_size_i == SHA2_384) || (digest_size_i == SHA2_512))) ? ('{data:o_pad_512[((BlockSizeSHA512 - 1) - (32 * pad_index_512))-:32], mask:'1}) : ((sel_rdata == SelFifo) ? fifo_rdata_i : ('{(*adjust*)default:'0, (*adjust*)default:'0}))))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T5

 LINE       192
 SUB-EXPRESSION ((sel_rdata == SelOPad) && (digest_size_i == SHA2_256))
                 -----------1----------    -------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T5
1	1	Covered	T2,T3,T5

 LINE       192
 SUB-EXPRESSION (sel_rdata == SelOPad)
                -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T5

 LINE       192
 SUB-EXPRESSION (digest_size_i == SHA2_256)
                -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       192
 SUB-EXPRESSION 
 Number  Term
      1  ((sel_rdata == SelOPad) && ((digest_size_i == SHA2_384) || (digest_size_i == SHA2_512))) ? ('{data:o_pad_512[((BlockSizeSHA512 - 1) - (32 * pad_index_512))-:32], mask:'1}) : ((sel_rdata == SelFifo) ? fifo_rdata_i : ('{(*adjust*)default:'0, (*adjust*)default:'0})))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T5

 LINE       192
 SUB-EXPRESSION ((sel_rdata == SelOPad) && ((digest_size_i == SHA2_384) || (digest_size_i == SHA2_512)))
                 -----------1----------    ------------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T5

 LINE       192
 SUB-EXPRESSION (sel_rdata == SelOPad)
                -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T5

 LINE       192
 SUB-EXPRESSION ((digest_size_i == SHA2_384) || (digest_size_i == SHA2_512))
                 -------------1-------------    -------------2-------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T10

 LINE       192
 SUB-EXPRESSION (digest_size_i == SHA2_384)
                -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T10

 LINE       192
 SUB-EXPRESSION (digest_size_i == SHA2_512)
                -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       192
 SUB-EXPRESSION ((sel_rdata == SelFifo) ? fifo_rdata_i : ('{(*adjust*)default:'0, (*adjust*)default:'0}))
                 -----------1----------

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T2,T3

 LINE       192
 SUB-EXPRESSION (sel_rdata == SelFifo)
                -----------1----------

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T2,T3

 LINE       213
 EXPRESSION (sel_msglen == SelIPadMsg)
            -------------1------------

-1-	Status	Tests
0	Covered	T2,T3,T5
1	Covered	T1,T2,T3

 LINE       214
 EXPRESSION (digest_size_i == SHA2_256)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       216
 EXPRESSION ((digest_size_i == SHA2_384) || (digest_size_i == SHA2_512))
             -------------1-------------    -------------2-------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T10

 LINE       216
 SUB-EXPRESSION (digest_size_i == SHA2_384)
                -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T10

 LINE       216
 SUB-EXPRESSION (digest_size_i == SHA2_512)
                -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       219
 EXPRESSION (sel_msglen == SelOPadMsg)
            -------------1------------

-1-	Status	Tests
0	Not Covered
1	Covered	T2,T3,T5

 LINE       221
 EXPRESSION (digest_size_i == SHA2_256)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T5
1	Covered	T2,T3,T5

 LINE       223
 EXPRESSION (digest_size_i == SHA2_384)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T5
1	Covered	T2,T3,T6

 LINE       225
 EXPRESSION (digest_size_i == SHA2_512)
            -------------1-------------

-1-	Status	Tests
0	Not Covered
1	Covered	T2,T3,T5

 LINE       238
 EXPRESSION ((txcount[(BlockSizeBitsSHA256 - 1):0] == '0) && (txcount != '0))
             ----------------------1---------------------    -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T5

 LINE       238
 SUB-EXPRESSION (txcount[(BlockSizeBitsSHA256 - 1):0] == '0)
                ----------------------1---------------------

-1-	Status	Tests
0	Covered	T2,T3,T5
1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (txcount != '0)
                -------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T5

 LINE       239
 EXPRESSION ((txcount[(BlockSizeBitsSHA512 - 1):0] == '0) && (txcount != '0))
             ----------------------1---------------------    -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T6

 LINE       239
 SUB-EXPRESSION (txcount[(BlockSizeBitsSHA512 - 1):0] == '0)
                ----------------------1---------------------

-1-	Status	Tests
0	Covered	T2,T3,T6
1	Covered	T1,T2,T3

 LINE       239
 SUB-EXPRESSION (txcount != '0)
                -------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T6

 LINE       240
 EXPRESSION ((txcount[(BlockSizeBitsSHA512 - 1):0] == '0) && (txcount != '0))
             ----------------------1---------------------    -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T5

 LINE       240
 SUB-EXPRESSION (txcount[(BlockSizeBitsSHA512 - 1):0] == '0)
                ----------------------1---------------------

-1-	Status	Tests
0	Covered	T2,T3,T5
1	Covered	T1,T2,T3

 LINE       240
 SUB-EXPRESSION (txcount != '0)
                -------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T5

 LINE       245
 EXPRESSION (sha_rready_i && sha_rvalid_o)
             ------1-----    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T5
1	0	Not Covered
1	1	Covered	T2,T3,T5

 LINE       281
 EXPRESSION (hmac_hash_done || reg_hash_start_i || reg_hash_continue_i)
             -------1------    --------2-------    ---------3---------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T4
0	1	0	Covered	T2,T3,T5
1	0	0	Covered	T2,T3,T5

 LINE       299
 EXPRESSION (fifo_wsel_o && fifo_wvalid_o)
             -----1-----    ------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Covered	T2,T3,T5

 LINE       304
 EXPRESSION ((round_q == Inner) ? SelIPadMsg : SelOPadMsg)
             ---------1--------

-1-	Status	Tests
0	Covered	T2,T3,T5
1	Covered	T1,T2,T3

 LINE       304
 SUB-EXPRESSION (round_q == Inner)
                ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       334
 EXPRESSION (hmac_en_i && reg_hash_start_i)
             ----1----    --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T5

 LINE       339
 EXPRESSION (hmac_en_i && reg_hash_continue_i)
             ----1----    ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T18,T28,T19

 LINE       365
 EXPRESSION (round_q == Outer)
            ---------1--------

-1-	Status	Tests
0	Covered	T2,T3,T5
1	Covered	T2,T3,T5

 LINE       367
 EXPRESSION ((((round_q == Inner) && reg_hash_process_flag) || (round_q == Outer)) && (txcount >= sha_message_length_o))
             ----------------------------------1----------------------------------    ----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T6
1	0	Covered	T2,T3,T5
1	1	Covered	T2,T3,T5

 LINE       367
 SUB-EXPRESSION (((round_q == Inner) && reg_hash_process_flag) || (round_q == Outer))
                 ----------------------1----------------------    ---------2--------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T5
0	1	Covered	T2,T3,T5
1	0	Covered	T2,T3,T5

 LINE       367
 SUB-EXPRESSION ((round_q == Inner) && reg_hash_process_flag)
                 ---------1--------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T5
1	0	Covered	T2,T3,T5
1	1	Covered	T2,T3,T5

 LINE       367
 SUB-EXPRESSION (round_q == Inner)
                ---------1--------

-1-	Status	Tests
0	Covered	T2,T3,T5
1	Covered	T2,T3,T5

 LINE       367
 SUB-EXPRESSION (round_q == Outer)
                ---------1--------

-1-	Status	Tests
0	Covered	T2,T3,T5
1	Covered	T2,T3,T5

 LINE       372
 EXPRESSION (round_q == Outer)
            ---------1--------

-1-	Status	Tests
0	Covered	T2,T3,T5
1	Covered	T2,T3,T5

 LINE       373
 EXPRESSION (txcnt_eq_blksz && (txcount >= sha_message_length_o) && reg_hash_stop_q && (round_q == Inner))
             -------1------    ----------------2----------------    -------3-------    ---------4--------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Not Covered
1	0	1	1	Covered	T19,T21,T29
1	1	0	1	Covered	T2,T3,T6
1	1	1	0	Not Covered
1	1	1	1	Covered	T18,T28,T19

 LINE       373
 SUB-EXPRESSION (round_q == Inner)
                ---------1--------

-1-	Status	Tests
0	Covered	T2,T3,T5
1	Covered	T2,T3,T5

 LINE       391
 EXPRESSION (round_q == Outer)
            ---------1--------

-1-	Status	Tests
0	Covered	T2,T3,T5
1	Covered	T2,T3,T5

 LINE       411
 EXPRESSION 
 Number  Term
      1  fifo_wready_i && 
      2  (((fifo_wdata_sel_o == 4'd7) && (digest_size_i == SHA2_256)) || ((fifo_wdata_sel_o == 4'd15) && (digest_size_i == SHA2_512)) || ((fifo_wdata_sel_o == 4'd11) && (digest_size_i == SHA2_384))))

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T3,T5
1	1	Covered	T2,T3,T5

 LINE       411
 SUB-EXPRESSION 
 Number  Term
      1  ((fifo_wdata_sel_o == 4'd7) && (digest_size_i == SHA2_256)) || 
      2  ((fifo_wdata_sel_o == 4'd15) && (digest_size_i == SHA2_512)) || 
      3  ((fifo_wdata_sel_o == 4'd11) && (digest_size_i == SHA2_384)))

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T2,T3,T5
0	0	1	Covered	T2,T3,T6
0	1	0	Covered	T2,T3,T5
1	0	0	Covered	T2,T3,T5

 LINE       411
 SUB-EXPRESSION ((fifo_wdata_sel_o == 4'd7) && (digest_size_i == SHA2_256))
                 -------------1------------    -------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T5
1	0	Covered	T2,T3,T5
1	1	Covered	T2,T3,T5

 LINE       411
 SUB-EXPRESSION (fifo_wdata_sel_o == 4'd7)
                -------------1------------

-1-	Status	Tests
0	Covered	T2,T3,T5
1	Covered	T2,T3,T5

 LINE       411
 SUB-EXPRESSION (digest_size_i == SHA2_256)
                -------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T5
1	Covered	T2,T3,T5

 LINE       411
 SUB-EXPRESSION ((fifo_wdata_sel_o == 4'd15) && (digest_size_i == SHA2_512))
                 -------------1-------------    -------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T5
1	0	Not Covered
1	1	Covered	T2,T3,T5

 LINE       411
 SUB-EXPRESSION (fifo_wdata_sel_o == 4'd15)
                -------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T5
1	Covered	T2,T3,T5

 LINE       411
 SUB-EXPRESSION (digest_size_i == SHA2_512)
                -------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T5
1	Covered	T2,T3,T5

 LINE       411
 SUB-EXPRESSION ((fifo_wdata_sel_o == 4'd11) && (digest_size_i == SHA2_384))
                 -------------1-------------    -------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T6
1	0	Covered	T2,T3,T5
1	1	Covered	T2,T3,T6

 LINE       411
 SUB-EXPRESSION (fifo_wdata_sel_o == 4'd11)
                -------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T5
1	Covered	T2,T3,T5

 LINE       411
 SUB-EXPRESSION (digest_size_i == SHA2_384)
                -------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T5
1	Covered	T2,T3,T6

 LINE       458
 EXPRESSION ((reg_hash_stop_i == 1'b1) ? 1'b1 : (((sha_hash_done_i == 1'b1) && (reg_hash_stop_q == 1'b1)) ? 1'b0 : reg_hash_stop_q))
             ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       458
 SUB-EXPRESSION (reg_hash_stop_i == 1'b1)
                ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       458
 SUB-EXPRESSION (((sha_hash_done_i == 1'b1) && (reg_hash_stop_q == 1'b1)) ? 1'b0 : reg_hash_stop_q)
                 ----------------------------1---------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       458
 SUB-EXPRESSION ((sha_hash_done_i == 1'b1) && (reg_hash_stop_q == 1'b1))
                 ------------1------------    ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T3,T5
1	1	Covered	T2,T3,T4

 LINE       458
 SUB-EXPRESSION (sha_hash_done_i == 1'b1)
                ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T5

 LINE       458
 SUB-EXPRESSION (reg_hash_stop_q == 1'b1)
                ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       471
 EXPRESSION ((reg_hash_start_i || reg_hash_continue_i) ? 1'b0 : ((st_q == StIdle) ? 1'b1 : ((txcnt_eq_blksz && reg_hash_stop_d) ? 1'b1 : idle_q)))
             --------------------1--------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T5

 LINE       471
 SUB-EXPRESSION (reg_hash_start_i || reg_hash_continue_i)
                 --------1-------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T3,T5

 LINE       471
 SUB-EXPRESSION ((st_q == StIdle) ? 1'b1 : ((txcnt_eq_blksz && reg_hash_stop_d) ? 1'b1 : idle_q))
                 --------1-------

-1-	Status	Tests
0	Covered	T2,T3,T5
1	Covered	T1,T2,T3

 LINE       471
 SUB-EXPRESSION (st_q == StIdle)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       471
 SUB-EXPRESSION ((txcnt_eq_blksz && reg_hash_stop_d) ? 1'b1 : idle_q)
                 -----------------1-----------------

-1-	Status	Tests
0	Covered	T2,T3,T5
1	Covered	T18,T28,T19

 LINE       471
 SUB-EXPRESSION (txcnt_eq_blksz && reg_hash_stop_d)
                 -------1------    -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T19,T21,T44
1	0	Covered	T2,T3,T5
1	1	Covered	T18,T28,T19

---

FSM Coverage for Module : hmac_core

Summary for FSM :: st_q

	Total	Covered	Percent
States	7	7	100.00	(Not included in score)
Transitions	9	9	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: st_q

---

states	Line No.	Covered	Tests
StDone	392	Covered	T2,T3,T5
StIPad	335	Covered	T2,T3,T5
StIdle	345	Covered	T1,T2,T3
StMsg	340	Covered	T2,T3,T5
StOPad	415	Covered	T2,T3,T5
StPushToMsgFifo	397	Covered	T2,T3,T5
StWaitResp	369	Covered	T2,T3,T5

transitions	Line No.	Covered	Tests
StDone->StIdle	444	Covered	T2,T3,T5
StIPad->StMsg	353	Covered	T2,T3,T5
StIdle->StIPad	335	Covered	T2,T3,T5
StIdle->StMsg	340	Covered	T18,T28,T19
StMsg->StWaitResp	369	Covered	T2,T3,T5
StOPad->StMsg	432	Covered	T2,T3,T5
StPushToMsgFifo->StOPad	415	Covered	T2,T3,T5
StWaitResp->StDone	392	Covered	T2,T3,T5
StWaitResp->StPushToMsgFifo	397	Covered	T2,T3,T5

---

Branch Coverage for Module : hmac_core

	Line No.	Total	Covered	Percent
Branches		91	85	93.41
TERNARY	120	2	2	100.00
TERNARY	121	2	2	100.00
TERNARY	123	2	2	100.00
TERNARY	124	2	2	100.00
TERNARY	189	2	2	100.00
TERNARY	191	2	2	100.00
TERNARY	192	7	6	85.71
TERNARY	304	2	2	100.00
TERNARY	458	3	3	100.00
TERNARY	471	4	4	100.00
CASE	137	6	6	100.00
IF	209	9	7	77.78
CASE	237	4	4	100.00
IF	254	7	6	85.71
IF	271	2	2	100.00
IF	277	4	4	100.00
IF	287	3	3	100.00
IF	295	4	3	75.00
IF	307	2	2	100.00
CASE	327	18	17	94.44
IF	463	2	2	100.00
IF	485	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_hmac_0.1/rtl/hmac_core.sv' or '../src/lowrisc_ip_hmac_0.1/rtl/hmac_core.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	120	(hmac_en_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	121	(hmac_en_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	(hmac_en_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	124	(hmac_en_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	189	(hmac_en_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	191	((!hmac_en_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	192	((!hmac_en_i)) ? 
-2-:	192	(((sel_rdata == SelIPad) && (digest_size_i == SHA2_256))) ? 
-3-:	192	(((sel_rdata == SelIPad) && ((digest_size_i == SHA2_384) || (digest_size_i == SHA2_512)))) ? 
-4-:	192	(((sel_rdata == SelOPad) && (digest_size_i == SHA2_256))) ? 
-5-:	192	(((sel_rdata == SelOPad) && ((digest_size_i == SHA2_384) || (digest_size_i == SHA2_512)))) ? 
-6-:	192	((sel_rdata == SelFifo)) ? 

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	Status	Tests
1	-	-	-	-	-	Covered	T1,T2,T3
0	1	-	-	-	-	Covered	T2,T3,T5
0	0	1	-	-	-	Covered	T2,T3,T5
0	0	0	1	-	-	Covered	T2,T3,T5
0	0	0	0	1	-	Covered	T2,T3,T5
0	0	0	0	0	1	Covered	T1,T2,T3
0	0	0	0	0	0	Not Covered

	LineNo.	Expression
-1-:	304	((round_q == Inner)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T5

	LineNo.	Expression
-1-:	458	((reg_hash_stop_i == 1'b1)) ? 
-2-:	458	(((sha_hash_done_i == 1'b1) && (reg_hash_stop_q == 1'b1))) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T3,T4
0	1	Covered	T2,T3,T4
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	471	((reg_hash_start_i || reg_hash_continue_i)) ? 
-2-:	471	((st_q == StIdle)) ? 
-3-:	471	((txcnt_eq_blksz && reg_hash_stop_d)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T2,T3,T5
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T18,T28,T19
0	0	0	Covered	T2,T3,T5

	LineNo.	Expression
-1-:	137	case (key_length_i)

Branches:

-1-	Status	Tests
Key_128	Covered	T1,T2,T3
Key_256	Covered	T1,T2,T3
Key_384	Covered	T2,T3,T6
Key_512	Covered	T2,T3,T5
Key_1024	Covered	T1,T2,T3
default	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	209	if ((!hmac_en_i))
-2-:	213	if ((sel_msglen == SelIPadMsg))
-3-:	214	if ((digest_size_i == SHA2_256))
-4-:	216	if (((digest_size_i == SHA2_384) || (digest_size_i == SHA2_512)))
-5-:	219	if ((sel_msglen == SelOPadMsg))
-6-:	221	if ((digest_size_i == SHA2_256))
-7-:	223	if ((digest_size_i == SHA2_384))
-8-:	225	if ((digest_size_i == SHA2_512))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
1	-	-	-	-	-	-	-	Covered	T1,T2,T3
0	1	1	-	-	-	-	-	Covered	T1,T2,T3
0	1	0	1	-	-	-	-	Covered	T1,T2,T3
0	1	0	0	-	-	-	-	Covered	T1,T2,T3
0	0	-	-	1	1	-	-	Covered	T2,T3,T5
0	0	-	-	1	0	1	-	Covered	T2,T3,T6
0	0	-	-	1	0	0	1	Covered	T2,T3,T5
0	0	-	-	1	0	0	0	Not Covered
0	0	-	-	0	-	-	-	Not Covered

	LineNo.	Expression
-1-:	237	case (digest_size_i)

Branches:

-1-	Status	Tests
SHA2_256	Covered	T1,T2,T3
SHA2_384	Covered	T1,T2,T3
SHA2_512	Covered	T1,T2,T3
default	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	254	if (clr_txcount)
-2-:	256	if (load_txcount)
-3-:	259	case (digest_size_i)
-4-:	265	if (inc_txcount)

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T2,T3,T5
0	1	SHA2_256	-	Covered	T18,T28,T19
0	1	SHA2_384	-	Covered	T19,T49,T50
0	1	SHA2_512	-	Covered	T18,T51,T52
0	1	default	-	Not Covered
0	0	-	1	Covered	T2,T3,T5
0	0	-	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	271	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	277	if ((!rst_ni))
-2-:	279	if (reg_hash_process_i)
-3-:	281	if (((hmac_hash_done || reg_hash_start_i) || reg_hash_continue_i))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T5
0	0	1	Covered	T2,T3,T5
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	287	if ((!rst_ni))
-2-:	289	if (update_round)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T2,T3,T5

	LineNo.	Expression
-1-:	295	if ((!rst_ni))
-2-:	297	if (clr_fifo_wdata_sel)
-3-:	299	if ((fifo_wsel_o && fifo_wvalid_o))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T5
0	0	0	Not Covered

	LineNo.	Expression
-1-:	307	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	327	case (st_q)
-2-:	334	if ((hmac_en_i && reg_hash_start_i))
-3-:	339	if ((hmac_en_i && reg_hash_continue_i))
-4-:	352	if (txcnt_eq_blksz)
-5-:	367	if (((((round_q == Inner) && reg_hash_process_flag) || (round_q == Outer)) && (txcount >= sha_message_length_o)))
-6-:	373	if ((((txcnt_eq_blksz && (txcount >= sha_message_length_o)) && reg_hash_stop_q) && (round_q == Inner)))
-7-:	390	if (sha_hash_done_i)
-8-:	391	if ((round_q == Outer))
-9-:	394	if (reg_hash_stop_q)
-10-:	411	if ((fifo_wready_i && ((((fifo_wdata_sel_o == 4'd7) && (digest_size_i == SHA2_256)) || ((fifo_wdata_sel_o == 4'd15) && (digest_size_i == SHA2_512))) || ((fifo_wdata_sel_o == 4'd11) && (digest_size_i == SHA2_384)))))
-11-:	431	if (txcnt_eq_blksz)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	Status	Tests
StIdle	1	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T5
StIdle	0	1	-	-	-	-	-	-	-	-	Covered	T18,T28,T19
StIdle	0	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StIPad	-	-	1	-	-	-	-	-	-	-	Covered	T2,T3,T5
StIPad	-	-	0	-	-	-	-	-	-	-	Covered	T2,T3,T5
StMsg	-	-	-	1	-	-	-	-	-	-	Covered	T2,T3,T5
StMsg	-	-	-	0	1	-	-	-	-	-	Covered	T18,T28,T19
StMsg	-	-	-	0	0	-	-	-	-	-	Covered	T2,T3,T5
StWaitResp	-	-	-	-	-	1	1	-	-	-	Covered	T2,T3,T5
StWaitResp	-	-	-	-	-	1	0	1	-	-	Covered	T18,T28,T19
StWaitResp	-	-	-	-	-	1	0	0	-	-	Covered	T2,T3,T5
StWaitResp	-	-	-	-	-	0	-	-	-	-	Covered	T2,T3,T5
StPushToMsgFifo	-	-	-	-	-	-	-	-	1	-	Covered	T2,T3,T5
StPushToMsgFifo	-	-	-	-	-	-	-	-	0	-	Covered	T2,T3,T5
StOPad	-	-	-	-	-	-	-	-	-	1	Covered	T2,T3,T5
StOPad	-	-	-	-	-	-	-	-	-	0	Covered	T2,T3,T5
StDone	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T5
default	-	-	-	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	463	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	485	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3