SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
100.00 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
tl_intg_err_cgs_wrap[hmac_reg_block] | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 14 | 0 | 14 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_is_mem | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_num_cmd_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_num_data_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_tl_intg_err_type | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 61256487 | 1 | T1 | 15593 | T2 | 91483 | T3 | 180839 | ||||
auto[1] | 18577824 | 1 | T1 | 4957 | T2 | 21154 | T3 | 294417 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 79834025 | 1 | T1 | 20550 | T2 | 112637 | T3 | 210281 | ||||
values[1] | 34 | 1 | T74 | 3 | T76 | 6 | T124 | 3 | ||||
values[2] | 10 | 1 | T74 | 1 | T125 | 1 | T124 | 1 | ||||
values[3] | 139 | 1 | T74 | 11 | T75 | 8 | T76 | 8 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 79834016 | 1 | T1 | 20550 | T2 | 112637 | T3 | 210281 | ||||
values[1] | 28 | 1 | T74 | 3 | T75 | 2 | T126 | 1 | ||||
values[2] | 7 | 1 | T76 | 3 | T124 | 1 | T127 | 1 | ||||
values[3] | 149 | 1 | T74 | 12 | T75 | 7 | T76 | 10 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[TlIntgErrNone] | 79833881 | 1 | T1 | 20550 | T2 | 112637 | T3 | 210281 | ||||
auto[TlIntgErrCmd] | 135 | 1 | T74 | 4 | T75 | 7 | T76 | 10 | ||||
auto[TlIntgErrData] | 144 | 1 | T74 | 10 | T75 | 7 | T76 | 7 | ||||
auto[TlIntgErrBoth] | 151 | 1 | T74 | 16 | T75 | 6 | T76 | 13 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |