Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

41543386

1

T1

11451

T2

58709

T3

105827

full_word

38290925

1

T1

9099

T2

53928

T3

104453

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	79833881	1			T1	20550		T2	112637		T3	210281
auto[TlIntgErrCmd]	135	1			T74	4		T75	7		T76	10
auto[TlIntgErrData]	144	1			T74	10		T75	7		T76	7
auto[TlIntgErrBoth]	151	1			T74	16		T75	6		T76	13

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

37745125

1

T1

10309

T2

55400

T3

970949

auto[1]

42089186

1

T1

10241

T2

57237

T3

113186

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	19304675	1			T1	5315		T2	27678		T3	485986
auto[TlIntgErrNone]	partial	auto[1]	22238317	1			T1	6136		T2	31031		T3	572291
auto[TlIntgErrNone]	full_word	auto[0]	18440263	1			T1	4994		T2	27722		T3	484963
auto[TlIntgErrNone]	full_word	auto[1]	19850626	1			T1	4105		T2	26206		T3	559574
auto[TlIntgErrCmd]	partial	auto[0]	50	1			T74	1		T75	4		T76	9
auto[TlIntgErrCmd]	partial	auto[1]	74	1			T74	2		T75	3		T126	6
auto[TlIntgErrCmd]	full_word	auto[0]	6	1			T74	1		T125	1		T128	1
auto[TlIntgErrCmd]	full_word	auto[1]	5	1			T76	1		T129	1		T130	1
auto[TlIntgErrData]	partial	auto[0]	66	1			T74	4		T75	2		T76	5
auto[TlIntgErrData]	partial	auto[1]	62	1			T74	5		T75	5		T76	2
auto[TlIntgErrData]	full_word	auto[0]	7	1			T124	1		T128	1		T131	2
auto[TlIntgErrData]	full_word	auto[1]	9	1			T74	1		T125	3		T132	1
auto[TlIntgErrBoth]	partial	auto[0]	53	1			T74	3		T76	5		T126	2
auto[TlIntgErrBoth]	partial	auto[1]	89	1			T74	12		T75	4		T76	6
auto[TlIntgErrBoth]	full_word	auto[0]	5	1			T74	1		T75	1		T76	1
auto[TlIntgErrBoth]	full_word	auto[1]	4	1			T75	1		T76	1		T127	1