Unified Coverage Report :: Module :: hmac_csr_assert_fpv

Module : hmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_hmac_csr_assert_0/hmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.hmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.hmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.71	100.00	93.33	100.00	100.00	98.90	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : hmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	436704687	891163	0	0
intr_enable_rd_A	436704687	2520	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436704687	891163	0	0
T18	0	20134	0	0
T19	0	79823	0	0
T20	0	70849	0	0
T22	152235	19677	0	0
T23	681689	126480	0	0
T24	0	49478	0	0
T25	52596	0	0	0
T33	0	48799	0	0
T35	0	385613	0	0
T37	197024	0	0	0
T63	3605	0	0	0
T70	3132	0	0	0
T71	1038	0	0	0
T72	55164	0	0	0
T73	135020	0	0	0
T77	0	23626	0	0
T78	0	52764	0	0
T79	582239	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436704687	2520	0	0
T18	0	40	0	0
T22	0	190	0	0
T23	0	97	0	0
T34	457362	14	0	0
T57	349619	0	0	0
T59	1267	0	0	0
T80	0	23	0	0
T81	0	8	0	0
T82	0	49	0	0
T83	0	43	0	0
T84	0	54	0	0
T85	0	57	0	0
T86	124286	0	0	0
T87	111967	0	0	0
T88	413250	0	0	0
T89	21547	0	0	0
T90	263523	0	0	0
T91	824319	0	0	0
T92	208451	0	0	0