Module Definition
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Module : prim_sha2_pad
SCORELINECONDTOGGLEFSMBRANCHASSERT
86.65 96.12 91.61 73.33 85.53

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_sha2_0/rtl/prim_sha2_pad.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_prim_sha2_512.gen_multimode_logic.u_prim_sha2_multimode.u_pad 95.98 96.12 94.93 100.00 92.86



Module Instance : tb.dut.u_prim_sha2_512.gen_multimode_logic.u_prim_sha2_multimode.u_pad

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.98 96.12 94.93 100.00 92.86


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.98 96.12 94.93 100.00 92.86


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.12 100.00 97.87 100.00 98.59 gen_multimode_logic.u_prim_sha2_multimode


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Line Coverage for Module : prim_sha2_pad
Line No.TotalCoveredPercent
TOTAL12912496.12
CONT_ASSIGN4811100.00
CONT_ASSIGN5611100.00
CONT_ASSIGN6011100.00
CONT_ASSIGN6711100.00
CONT_ASSIGN7211100.00
CONT_ASSIGN7611100.00
ALWAYS8155100.00
ALWAYS101232295.65
ALWAYS19033100.00
ALWAYS196747094.59
ALWAYS3461010100.00
ALWAYS36433100.00
CONT_ASSIGN36811100.00
ALWAYS37333100.00
CONT_ASSIGN37811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_sha2_0/rtl/prim_sha2_pad.sv' or '../src/lowrisc_prim_sha2_0/rtl/prim_sha2_pad.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
48 1 1
56 1 1
60 1 1
67 1 1
72 1 1
76 1 1
81 1 1
82 1 1
83 1 1
85 1 1
86 1 1
101 1 1
103 1 1
112 1 1
113 1 1
114 1 1
115 1 1
116 1 1
117 1 1
120 1 1
121 1 1
122 1 1
123 1 1
124 1 1
125 1 1
126 1 1
127 1 1
128 1 1
129 1 1
133 0 1
137 1 1
141 1 1
148 1 1
159 1 1(1 unreachable)
MISSING_ELSE
190 2 2
191 1 1
196 1 1
197 1 1
198 1 1
199 1 1
200 1 1
202 1 1
204 1 1
205 1 1
206 1 1
207 1 1
208 1 1
210 1 1
215 1 1
216 1 1
218 1 1
219 1 1
220 1 1
221 1 1
222 1 1
223 1 1
224 1 1
225 1 1
226 1 1
227 1 1
229 1 1
230 1 1
231 1 1
232 1 1
234 1 1
235 1 1
236 1 1
237 1 1
240 1 1
241 1 1
242 1 1
243 1 1
244 1 1
MISSING_ELSE
249 1 1
250 1 1
251 1 1
257 1 1
258 1 1
259 1 1
263 1 1
264 1 1
265 1 1
267 1 1
268 1 1
297 1 1
298 1 1
300 1 1
301 1 1
302 2 2
303 1 1
305 1 1
310 1 1
311 1 1
313 1 1
314 1 1
315 1 1
317 0 1
318 0 1
323 1 1
324 1 1
326 1 1
327 1 1
328 1 1
330 0 1
331 0 1
340 2 2
341 2 2
MISSING_ELSE
346 1 1
348 1 1
350 1 1
351 1 1
353 1 1
354 1 1
355 1 1
356 1 1
357 1 1
358 1 1
==> MISSING_ELSE
MISSING_ELSE
364 2 2
365 1 1
368 1 1
373 2 2
374 1 1
378 1 1


Cond Coverage for Module : prim_sha2_pad
TotalCoveredPercent
Conditions14313191.61
Logical14313191.61
Non-Logical00
Event00

 LINE       48
 EXPRESSION (hash_start_i | hash_continue_i)
             ------1-----   -------2-------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT4,T5,T6
10CoveredT2,T3,T4

 LINE       60
 EXPRESSION 
 Number  Term
      1  ((digest_mode_flag_q == SHA2_256) || ((~MultimodeEn))) ? (tx_count[8:0] == 9'h1a0) : (((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512)) ? (tx_count[9:0] == 10'h340) : '0))
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T4

 LINE       60
 SUB-EXPRESSION ((digest_mode_flag_q == SHA2_256) || ((~MultimodeEn)))
                 ----------------1---------------    --------2-------
-1--2-StatusTests
0-CoveredT1,T2,T3
1-CoveredT2,T3,T4

 LINE       60
 SUB-EXPRESSION (digest_mode_flag_q == SHA2_256)
                ----------------1---------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T4

 LINE       60
 SUB-EXPRESSION (tx_count[8:0] == 9'h1a0)
                ------------1------------
-1-StatusTests
0CoveredT2,T3,T4
1CoveredT2,T3,T4

 LINE       60
 SUB-EXPRESSION (((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512)) ? (tx_count[9:0] == 10'h340) : '0)
                 -----------------------------------1----------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T4

 LINE       60
 SUB-EXPRESSION ((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512))
                 ----------------1---------------    ----------------2---------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT2,T3,T4
10CoveredT2,T3,T4

 LINE       60
 SUB-EXPRESSION (digest_mode_flag_q == SHA2_384)
                ----------------1---------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T4

 LINE       60
 SUB-EXPRESSION (digest_mode_flag_q == SHA2_512)
                ----------------1---------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T4

 LINE       60
 SUB-EXPRESSION (tx_count[9:0] == 10'h340)
                -------------1------------
-1-StatusTests
0CoveredT2,T3,T4
1CoveredT2,T3,T4

 LINE       67
 EXPRESSION (tx_count == message_length_i)
            ---------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       72
 EXPRESSION ((((~sha_en_i)) || hash_go || hash_done_i) ? 1'b0 : (hash_stop_i ? 1'b1 : hash_stop_flag_q))
             --------------------1--------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       72
 SUB-EXPRESSION (((~sha_en_i)) || hash_go || hash_done_i)
                 ------1------    ---2---    -----3-----
-1--2--3-StatusTests
000CoveredT1,T2,T3
001CoveredT2,T3,T4
010CoveredT2,T3,T4
100CoveredT1,T2,T3

 LINE       72
 SUB-EXPRESSION (hash_stop_i ? 1'b1 : hash_stop_flag_q)
                 -----1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT4,T5,T6

 LINE       76
 EXPRESSION ((((~sha_en_i)) || hash_go || hash_done_i) ? 1'b0 : (hash_process_i ? 1'b1 : hash_process_flag_q))
             --------------------1--------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       76
 SUB-EXPRESSION (((~sha_en_i)) || hash_go || hash_done_i)
                 ------1------    ---2---    -----3-----
-1--2--3-StatusTests
000CoveredT1,T2,T3
001CoveredT2,T3,T4
010CoveredT2,T3,T4
100CoveredT1,T2,T3

 LINE       76
 SUB-EXPRESSION (hash_process_i ? 1'b1 : hash_process_flag_q)
                 -------1------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T4

 LINE       112
 EXPRESSION ((digest_mode_flag_q == SHA2_256) || ((~MultimodeEn)))
             ----------------1---------------    --------2-------
-1--2-StatusTests
0-CoveredT2,T3,T4
1-CoveredT2,T3,T4

 LINE       112
 SUB-EXPRESSION (digest_mode_flag_q == SHA2_256)
                ----------------1---------------
-1-StatusTests
0CoveredT2,T3,T4
1CoveredT2,T3,T4

 LINE       120
 EXPRESSION ((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512))
             ----------------1---------------    ----------------2---------------
-1--2-StatusTests
00Not Covered
01CoveredT2,T3,T4
10CoveredT2,T3,T4

 LINE       120
 SUB-EXPRESSION (digest_mode_flag_q == SHA2_384)
                ----------------1---------------
-1-StatusTests
0CoveredT2,T3,T4
1CoveredT2,T3,T4

 LINE       120
 SUB-EXPRESSION (digest_mode_flag_q == SHA2_512)
                ----------------1---------------
-1-StatusTests
0CoveredT2,T3,T4
1CoveredT2,T3,T4

 LINE       141
 EXPRESSION 
 Number  Term
      1  ((digest_mode_flag_q == SHA2_256) || ((~MultimodeEn))) ? ({32'b0, message_length_i[63:32]}) : (((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512)) ? message_length_i[127:64] : '0))
-1-StatusTests
0CoveredT2,T3,T4
1CoveredT2,T3,T4

 LINE       141
 SUB-EXPRESSION ((digest_mode_flag_q == SHA2_256) || ((~MultimodeEn)))
                 ----------------1---------------    --------2-------
-1--2-StatusTests
0-CoveredT2,T3,T4
1-CoveredT2,T3,T4

 LINE       141
 SUB-EXPRESSION (digest_mode_flag_q == SHA2_256)
                ----------------1---------------
-1-StatusTests
0CoveredT2,T3,T4
1CoveredT2,T3,T4

 LINE       141
 SUB-EXPRESSION (((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512)) ? message_length_i[127:64] : '0)
                 -----------------------------------1----------------------------------
-1-StatusTests
0Not Covered
1CoveredT2,T3,T4

 LINE       141
 SUB-EXPRESSION ((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512))
                 ----------------1---------------    ----------------2---------------
-1--2-StatusTests
00Not Covered
01CoveredT2,T3,T4
10CoveredT2,T3,T4

 LINE       141
 SUB-EXPRESSION (digest_mode_flag_q == SHA2_384)
                ----------------1---------------
-1-StatusTests
0CoveredT2,T3,T4
1CoveredT2,T3,T4

 LINE       141
 SUB-EXPRESSION (digest_mode_flag_q == SHA2_512)
                ----------------1---------------
-1-StatusTests
0CoveredT2,T3,T4
1CoveredT2,T3,T4

 LINE       148
 EXPRESSION 
 Number  Term
      1  ((digest_mode_flag_q == SHA2_256) || ((~MultimodeEn))) ? ({32'b0, message_length_i[31:0]}) : (((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512)) ? message_length_i[63:0] : '0))
-1-StatusTests
0CoveredT2,T3,T4
1CoveredT2,T3,T4

 LINE       148
 SUB-EXPRESSION ((digest_mode_flag_q == SHA2_256) || ((~MultimodeEn)))
                 ----------------1---------------    --------2-------
-1--2-StatusTests
0-CoveredT2,T3,T4
1-CoveredT2,T3,T4

 LINE       148
 SUB-EXPRESSION (digest_mode_flag_q == SHA2_256)
                ----------------1---------------
-1-StatusTests
0CoveredT2,T3,T4
1CoveredT2,T3,T4

 LINE       148
 SUB-EXPRESSION (((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512)) ? message_length_i[63:0] : '0)
                 -----------------------------------1----------------------------------
-1-StatusTests
0Not Covered
1CoveredT2,T3,T4

 LINE       148
 SUB-EXPRESSION ((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512))
                 ----------------1---------------    ----------------2---------------
-1--2-StatusTests
00Not Covered
01CoveredT2,T3,T4
10CoveredT2,T3,T4

 LINE       148
 SUB-EXPRESSION (digest_mode_flag_q == SHA2_384)
                ----------------1---------------
-1-StatusTests
0CoveredT2,T3,T4
1CoveredT2,T3,T4

 LINE       148
 SUB-EXPRESSION (digest_mode_flag_q == SHA2_512)
                ----------------1---------------
-1-StatusTests
0CoveredT2,T3,T4
1CoveredT2,T3,T4

 LINE       206
 EXPRESSION (sha_en_i && hash_go)
             ----1---    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT2,T3,T4

 LINE       216
 EXPRESSION (fifo_partial && fifo_rvalid_i)
             ------1-----    ------2------
-1--2-StatusTests
01CoveredT2,T3,T4
10CoveredT2,T3,T4
11CoveredT2,T3,T4

 LINE       240
 EXPRESSION (txcnt_eq_msg_len && hash_stop_flag_q)
             --------1-------    --------2-------
-1--2-StatusTests
01CoveredT8,T17,T18
10CoveredT2,T3,T4
11CoveredT4,T5,T6

 LINE       251
 EXPRESSION 
 Number  Term
      1  ((digest_mode_flag_q == SHA2_256) || ((~MultimodeEn))) ? (shaf_rready_i && ((|message_length_i[4:3]))) : (((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512)) ? (shaf_rready_i && ((|message_length_i[5:3]))) : '0))
-1-StatusTests
0CoveredT2,T3,T4
1CoveredT2,T3,T4

 LINE       251
 SUB-EXPRESSION ((digest_mode_flag_q == SHA2_256) || ((~MultimodeEn)))
                 ----------------1---------------    --------2-------
-1--2-StatusTests
0-CoveredT2,T3,T4
1-CoveredT2,T3,T4

 LINE       251
 SUB-EXPRESSION (digest_mode_flag_q == SHA2_256)
                ----------------1---------------
-1-StatusTests
0CoveredT2,T3,T4
1CoveredT2,T3,T4

 LINE       251
 SUB-EXPRESSION (shaf_rready_i && ((|message_length_i[4:3])))
                 ------1------    -------------2------------
-1--2-StatusTests
01CoveredT2,T4,T6
10CoveredT2,T4,T5
11CoveredT2,T3,T4

 LINE       251
 SUB-EXPRESSION (((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512)) ? (shaf_rready_i && ((|message_length_i[5:3]))) : '0)
                 -----------------------------------1----------------------------------
-1-StatusTests
0Not Covered
1CoveredT2,T3,T4

 LINE       251
 SUB-EXPRESSION ((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512))
                 ----------------1---------------    ----------------2---------------
-1--2-StatusTests
00Not Covered
01CoveredT2,T3,T4
10CoveredT2,T3,T4

 LINE       251
 SUB-EXPRESSION (digest_mode_flag_q == SHA2_384)
                ----------------1---------------
-1-StatusTests
0CoveredT2,T3,T4
1CoveredT2,T3,T4

 LINE       251
 SUB-EXPRESSION (digest_mode_flag_q == SHA2_512)
                ----------------1---------------
-1-StatusTests
0CoveredT2,T3,T4
1CoveredT2,T3,T4

 LINE       251
 SUB-EXPRESSION (shaf_rready_i && ((|message_length_i[5:3])))
                 ------1------    -------------2------------
-1--2-StatusTests
01Not Covered
10CoveredT2,T3,T4
11CoveredT2,T3,T4

 LINE       257
 EXPRESSION (shaf_rready_i && txcnt_eq_1a0)
             ------1------    ------2-----
-1--2-StatusTests
01Not Covered
10CoveredT2,T3,T4
11CoveredT2,T5,T6

 LINE       263
 EXPRESSION (shaf_rready_i && ((!txcnt_eq_1a0)))
             ------1------    --------2--------
-1--2-StatusTests
01CoveredT2,T4,T5
10Not Covered
11CoveredT2,T3,T4

 LINE       355
 EXPRESSION ((digest_mode_flag_q == SHA2_256) || ((!MultimodeEn)))
             ----------------1---------------    --------2-------
-1--2-StatusTests
0-CoveredT2,T3,T4
1-CoveredT2,T3,T4

 LINE       355
 SUB-EXPRESSION (digest_mode_flag_q == SHA2_256)
                ----------------1---------------
-1-StatusTests
0CoveredT2,T3,T4
1CoveredT2,T3,T4

 LINE       357
 EXPRESSION ((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512))
             ----------------1---------------    ----------------2---------------
-1--2-StatusTests
00Not Covered
01CoveredT2,T3,T4
10CoveredT2,T3,T4

 LINE       357
 SUB-EXPRESSION (digest_mode_flag_q == SHA2_384)
                ----------------1---------------
-1-StatusTests
0CoveredT2,T3,T4
1CoveredT2,T3,T4

 LINE       357
 SUB-EXPRESSION (digest_mode_flag_q == SHA2_512)
                ----------------1---------------
-1-StatusTests
0CoveredT2,T3,T4
1CoveredT2,T3,T4

 LINE       368
 EXPRESSION ((hash_start_i || hash_continue_i) ? digest_mode_i : (hash_done_i ? SHA2_None : digest_mode_flag_q))
             ----------------1----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T4

 LINE       368
 SUB-EXPRESSION (hash_start_i || hash_continue_i)
                 ------1-----    -------2-------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT4,T5,T6
10CoveredT2,T3,T4

 LINE       368
 SUB-EXPRESSION (hash_done_i ? SHA2_None : digest_mode_flag_q)
                 -----1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T4

 LINE       378
 EXPRESSION ((hash_process_flag_q || hash_stop_flag_q) && (st_q == StIdle))
             --------------------1--------------------    --------2-------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T3,T4
11CoveredT2,T3,T4

 LINE       378
 SUB-EXPRESSION (hash_process_flag_q || hash_stop_flag_q)
                 ---------1---------    --------2-------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT4,T5,T6
10CoveredT2,T3,T4

 LINE       378
 SUB-EXPRESSION (st_q == StIdle)
                --------1-------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

FSM Coverage for Module : prim_sha2_pad
Summary for FSM :: st_q
TotalCoveredPercent
States 6 6 100.00 (Not included in score)
Transitions 15 11 73.33
Sequences 0 0

State, Transition and Sequence Details for FSM :: st_q
statesLine No.CoveredTests
StFifoReceive 208 Covered T2,T3,T4
StIdle 200 Covered T1,T2,T3
StLenHi 258 Covered T2,T3,T4
StLenLo 314 Covered T2,T3,T4
StPad00 264 Covered T2,T3,T4
StPad80 221 Covered T2,T3,T4


transitionsLine No.CoveredTests
StFifoReceive->StIdle 200 Covered T4,T5,T6
StFifoReceive->StPad80 221 Covered T2,T3,T4
StIdle->StFifoReceive 208 Covered T2,T3,T4
StLenHi->StFifoReceive 341 Not Covered
StLenHi->StIdle 200 Covered T19
StLenHi->StLenLo 314 Covered T2,T3,T4
StLenLo->StFifoReceive 341 Not Covered
StLenLo->StIdle 200 Covered T2,T3,T4
StPad00->StFifoReceive 341 Not Covered
StPad00->StIdle 200 Covered T9,T20,T21
StPad00->StLenHi 302 Covered T2,T3,T4
StPad80->StFifoReceive 341 Not Covered
StPad80->StIdle 200 Covered T7
StPad80->StLenHi 258 Covered T2,T5,T6
StPad80->StPad00 264 Covered T2,T3,T4



Branch Coverage for Module : prim_sha2_pad
Line No.TotalCoveredPercent
Branches 76 65 85.53
TERNARY 60 3 3 100.00
TERNARY 72 3 3 100.00
TERNARY 76 3 3 100.00
TERNARY 368 3 3 100.00
IF 81 2 2 100.00
CASE 101 24 18 75.00
IF 159 1 1 100.00
IF 190 2 2 100.00
CASE 202 22 18 81.82
IF 340 3 3 100.00
IF 348 6 5 83.33
IF 364 2 2 100.00
IF 373 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_sha2_0/rtl/prim_sha2_pad.sv' or '../src/lowrisc_prim_sha2_0/rtl/prim_sha2_pad.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 60 (((digest_mode_flag_q == SHA2_256) || (~MultimodeEn))) ? -2-: 60 (((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512))) ?

Branches:
-1--2-StatusTests
1 - Covered T2,T3,T4
0 1 Covered T2,T3,T4
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 72 ((((~sha_en_i) || hash_go) || hash_done_i)) ? -2-: 72 (hash_stop_i) ?

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T4,T5,T6
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 76 ((((~sha_en_i) || hash_go) || hash_done_i)) ? -2-: 76 (hash_process_i) ?

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T2,T3,T4
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 368 ((hash_start_i || hash_continue_i)) ? -2-: 368 (hash_done_i) ?

Branches:
-1--2-StatusTests
1 - Covered T2,T3,T4
0 1 Covered T2,T3,T4
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 81 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 101 case (sel_data) -2-: 112 if (((digest_mode_flag_q == SHA2_256) || (~MultimodeEn))) -3-: 113 case (message_length_i[4:3]) -4-: 120 if (((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512))) -5-: 121 case (message_length_i[5:3]) -6-: 141 (((digest_mode_flag_q == SHA2_256) || (~MultimodeEn))) ? -7-: 141 (((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512))) ? -8-: 148 (((digest_mode_flag_q == SHA2_256) || (~MultimodeEn))) ? -9-: 148 (((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512))) ?

Branches:
-1--2--3--4--5--6--7--8--9-StatusTests
FifoIn - - - - - - - - Covered T1,T2,T3
Pad80 1 2'b00 - - - - - - Covered T2,T4,T5
Pad80 1 2'b01 - - - - - - Covered T2,T3,T4
Pad80 1 2'b10 - - - - - - Covered T2,T3,T6
Pad80 1 2'b11 - - - - - - Covered T2,T5,T13
Pad80 1 default - - - - - - Not Covered
Pad80 0 - 1 3'b000 - - - - Covered T2,T3,T4
Pad80 0 - 1 3'b001 - - - - Covered T2,T3,T4
Pad80 0 - 1 3'b010 - - - - Covered T2,T4,T13
Pad80 0 - 1 3'b011 - - - - Covered T2,T5,T14
Pad80 0 - 1 3'b100 - - - - Covered T2,T5,T14
Pad80 0 - 1 3'b101 - - - - Covered T2,T3,T4
Pad80 0 - 1 3'b110 - - - - Covered T2,T3,T4
Pad80 0 - 1 3'b111 - - - - Covered T2,T3,T4
Pad80 0 - 1 default - - - - Not Covered
Pad80 0 - 0 - - - - - Not Covered
Pad00 - - - - - - - - Covered T2,T3,T4
LenHi - - - - 1 - - - Covered T2,T3,T4
LenHi - - - - 0 1 - - Covered T2,T3,T4
LenHi - - - - 0 0 - - Not Covered
LenLo - - - - - - 1 - Covered T2,T3,T4
LenLo - - - - - - 0 1 Covered T2,T3,T4
LenLo - - - - - - 0 0 Not Covered
default - - - - - - - - Not Covered


LineNo. Expression -1-: 159 if ((!MultimodeEn))

Branches:
-1-StatusTests
1 Unreachable
0 Covered T1,T2,T3


LineNo. Expression -1-: 190 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 202 case (st_q) -2-: 206 if ((sha_en_i && hash_go)) -3-: 216 if ((fifo_partial && fifo_rvalid_i)) -4-: 222 if ((!hash_process_flag_q)) -5-: 227 if (txcnt_eq_msg_len) -6-: 240 if ((txcnt_eq_msg_len && hash_stop_flag_q)) -7-: 251 (((digest_mode_flag_q == SHA2_256) || (~MultimodeEn))) ? -8-: 251 (((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512))) ? -9-: 257 if ((shaf_rready_i && txcnt_eq_1a0)) -10-: 263 if ((shaf_rready_i && (!txcnt_eq_1a0))) -11-: 300 if (shaf_rready_i) -12-: 302 if (txcnt_eq_1a0) -13-: 313 if (shaf_rready_i) -14-: 326 if (shaf_rready_i)

Branches:
-1--2--3--4--5--6--7--8--9--10--11--12--13--14-StatusTests
StIdle 1 - - - - - - - - - - - - Covered T2,T3,T4
StIdle 0 - - - - - - - - - - - - Covered T1,T2,T3
StFifoReceive - 1 - - - - - - - - - - - Covered T2,T3,T4
StFifoReceive - 0 1 - - - - - - - - - - Covered T2,T3,T4
StFifoReceive - 0 0 1 - - - - - - - - - Covered T2,T3,T4
StFifoReceive - 0 0 0 - - - - - - - - - Covered T5,T6,T7
StFifoReceive - - - - 1 - - - - - - - - Covered T4,T5,T6
StFifoReceive - - - - 0 - - - - - - - - Covered T2,T3,T4
StPad80 - - - - - 1 - - - - - - - Covered T2,T3,T4
StPad80 - - - - - 0 1 - - - - - - Covered T2,T3,T4
StPad80 - - - - - 0 0 - - - - - - Not Covered
StPad80 - - - - - - - 1 - - - - - Covered T2,T5,T6
StPad80 - - - - - - - 0 1 - - - - Covered T2,T3,T4
StPad80 - - - - - - - 0 0 - - - - Covered T2,T4,T5
StPad00 - - - - - - - - - 1 1 - - Covered T2,T3,T4
StPad00 - - - - - - - - - 1 0 - - Covered T2,T3,T4
StPad00 - - - - - - - - - 0 - - - Covered T2,T3,T4
StLenHi - - - - - - - - - - - 1 - Covered T2,T3,T4
StLenHi - - - - - - - - - - - 0 - Not Covered
StLenLo - - - - - - - - - - - - 1 Covered T2,T3,T4
StLenLo - - - - - - - - - - - - 0 Not Covered
default - - - - - - - - - - - - - Not Covered


LineNo. Expression -1-: 340 if ((!sha_en_i)) -2-: 341 if (hash_go)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T2,T3,T4
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 348 if (hash_start_i) -2-: 351 if (hash_continue_i) -3-: 354 if (inc_txcount) -4-: 355 if (((digest_mode_flag_q == SHA2_256) || (!MultimodeEn))) -5-: 357 if (((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512)))

Branches:
-1--2--3--4--5-StatusTests
1 - - - - Covered T2,T3,T4
0 1 - - - Covered T4,T5,T6
0 0 1 1 - Covered T2,T3,T4
0 0 1 0 1 Covered T2,T3,T4
0 0 1 0 0 Not Covered
0 0 0 - - Covered T1,T2,T3


LineNo. Expression -1-: 364 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 373 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_prim_sha2_512.gen_multimode_logic.u_prim_sha2_multimode.u_pad
Line No.TotalCoveredPercent
TOTAL12912496.12
CONT_ASSIGN4811100.00
CONT_ASSIGN5611100.00
CONT_ASSIGN6011100.00
CONT_ASSIGN6711100.00
CONT_ASSIGN7211100.00
CONT_ASSIGN7611100.00
ALWAYS8155100.00
ALWAYS101232295.65
ALWAYS19033100.00
ALWAYS196747094.59
ALWAYS3461010100.00
ALWAYS36433100.00
CONT_ASSIGN36811100.00
ALWAYS37333100.00
CONT_ASSIGN37811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_sha2_0/rtl/prim_sha2_pad.sv' or '../src/lowrisc_prim_sha2_0/rtl/prim_sha2_pad.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
48 1 1
56 1 1
60 1 1
67 1 1
72 1 1
76 1 1
81 1 1
82 1 1
83 1 1
85 1 1
86 1 1
101 1 1
103 1 1
112 1 1
113 1 1
114 1 1
115 1 1
116 1 1
117 1 1
Exclude Annotation: VC_COV_UNR
120 1 1
121 1 1
122 1 1
123 1 1
124 1 1
125 1 1
126 1 1
127 1 1
128 1 1
129 1 1
Exclude Annotation: VC_COV_UNR
133 0 1
137 1 1
141 1 1
148 1 1
Exclude Annotation: VC_COV_UNR
159 1 1(1 unreachable)
MISSING_ELSE
190 2 2
191 1 1
196 1 1
197 1 1
198 1 1
199 1 1
200 1 1
202 1 1
204 1 1
205 1 1
206 1 1
207 1 1
208 1 1
210 1 1
215 1 1
216 1 1
218 1 1
219 1 1
220 1 1
221 1 1
222 1 1
223 1 1
224 1 1
225 1 1
226 1 1
227 1 1
229 1 1
230 1 1
231 1 1
232 1 1
234 1 1
235 1 1
236 1 1
237 1 1
240 1 1
241 1 1
242 1 1
243 1 1
244 1 1
MISSING_ELSE
249 1 1
250 1 1
251 1 1
257 1 1
258 1 1
259 1 1
263 1 1
264 1 1
265 1 1
267 1 1
268 1 1
297 1 1
298 1 1
300 1 1
301 1 1
302 2 2
303 1 1
305 1 1
310 1 1
311 1 1
313 1 1
314 1 1
315 1 1
317 0 1
318 0 1
323 1 1
324 1 1
326 1 1
327 1 1
328 1 1
330 0 1
331 0 1
Exclude Annotation: VC_COV_UNR
340 2 2
341 2 2
MISSING_ELSE
346 1 1
348 1 1
350 1 1
351 1 1
353 1 1
354 1 1
355 1 1
356 1 1
357 1 1
358 1 1
==> MISSING_ELSE
MISSING_ELSE
364 2 2
365 1 1
368 1 1
373 2 2
374 1 1
378 1 1


Cond Coverage for Instance : tb.dut.u_prim_sha2_512.gen_multimode_logic.u_prim_sha2_multimode.u_pad
TotalCoveredPercent
Conditions13813194.93
Logical13813194.93
Non-Logical00
Event00

 LINE       48
 EXPRESSION (hash_start_i | hash_continue_i)
             ------1-----   -------2-------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT4,T5,T6
10CoveredT2,T3,T4

 LINE       60
 EXPRESSION 
 Number  Term
      1  ((digest_mode_flag_q == SHA2_256) || ((~MultimodeEn))) ? (tx_count[8:0] == 9'h1a0) : (((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512)) ? (tx_count[9:0] == 10'h340) : '0))
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T4

 LINE       60
 SUB-EXPRESSION ((digest_mode_flag_q == SHA2_256) || ((~MultimodeEn)))
                 ----------------1---------------    --------2-------
-1--2-StatusTests
0-CoveredT1,T2,T3
1-CoveredT2,T3,T4

 LINE       60
 SUB-EXPRESSION (digest_mode_flag_q == SHA2_256)
                ----------------1---------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T4

 LINE       60
 SUB-EXPRESSION (tx_count[8:0] == 9'h1a0)
                ------------1------------
-1-StatusTests
0CoveredT2,T3,T4
1CoveredT2,T3,T4

 LINE       60
 SUB-EXPRESSION (((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512)) ? (tx_count[9:0] == 10'h340) : '0)
                 -----------------------------------1----------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T4

 LINE       60
 SUB-EXPRESSION ((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512))
                 ----------------1---------------    ----------------2---------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT2,T3,T4
10CoveredT2,T3,T4

 LINE       60
 SUB-EXPRESSION (digest_mode_flag_q == SHA2_384)
                ----------------1---------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T4

 LINE       60
 SUB-EXPRESSION (digest_mode_flag_q == SHA2_512)
                ----------------1---------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T4

 LINE       60
 SUB-EXPRESSION (tx_count[9:0] == 10'h340)
                -------------1------------
-1-StatusTests
0CoveredT2,T3,T4
1CoveredT2,T3,T4

 LINE       67
 EXPRESSION (tx_count == message_length_i)
            ---------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       72
 EXPRESSION ((((~sha_en_i)) || hash_go || hash_done_i) ? 1'b0 : (hash_stop_i ? 1'b1 : hash_stop_flag_q))
             --------------------1--------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       72
 SUB-EXPRESSION (((~sha_en_i)) || hash_go || hash_done_i)
                 ------1------    ---2---    -----3-----
-1--2--3-StatusTests
000CoveredT1,T2,T3
001CoveredT2,T3,T4
010CoveredT2,T3,T4
100CoveredT1,T2,T3

 LINE       72
 SUB-EXPRESSION (hash_stop_i ? 1'b1 : hash_stop_flag_q)
                 -----1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT4,T5,T6

 LINE       76
 EXPRESSION ((((~sha_en_i)) || hash_go || hash_done_i) ? 1'b0 : (hash_process_i ? 1'b1 : hash_process_flag_q))
             --------------------1--------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       76
 SUB-EXPRESSION (((~sha_en_i)) || hash_go || hash_done_i)
                 ------1------    ---2---    -----3-----
-1--2--3-StatusTests
000CoveredT1,T2,T3
001CoveredT2,T3,T4
010CoveredT2,T3,T4
100CoveredT1,T2,T3

 LINE       76
 SUB-EXPRESSION (hash_process_i ? 1'b1 : hash_process_flag_q)
                 -------1------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T4

 LINE       112
 EXPRESSION ((digest_mode_flag_q == SHA2_256) || ((~MultimodeEn)))
             ----------------1---------------    --------2-------
-1--2-StatusTests
0-CoveredT2,T3,T4
1-CoveredT2,T3,T4

 LINE       112
 SUB-EXPRESSION (digest_mode_flag_q == SHA2_256)
                ----------------1---------------
-1-StatusTests
0CoveredT2,T3,T4
1CoveredT2,T3,T4

 LINE       120
 EXPRESSION ((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512))
             ----------------1---------------    ----------------2---------------
-1--2-StatusTests
00Not Covered
01CoveredT2,T3,T4
10CoveredT2,T3,T4

 LINE       120
 SUB-EXPRESSION (digest_mode_flag_q == SHA2_384)
                ----------------1---------------
-1-StatusTests
0CoveredT2,T3,T4
1CoveredT2,T3,T4

 LINE       120
 SUB-EXPRESSION (digest_mode_flag_q == SHA2_512)
                ----------------1---------------
-1-StatusTests
0CoveredT2,T3,T4
1CoveredT2,T3,T4

 LINE       141
 EXPRESSION 
 Number  Term
      1  ((digest_mode_flag_q == SHA2_256) || ((~MultimodeEn))) ? ({32'b0, message_length_i[63:32]}) : (((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512)) ? message_length_i[127:64] : '0))
-1-StatusTests
0CoveredT2,T3,T4
1CoveredT2,T3,T4

 LINE       141
 SUB-EXPRESSION ((digest_mode_flag_q == SHA2_256) || ((~MultimodeEn)))
                 ----------------1---------------    --------2-------
-1--2-StatusTests
0-CoveredT2,T3,T4
1-CoveredT2,T3,T4

 LINE       141
 SUB-EXPRESSION (digest_mode_flag_q == SHA2_256)
                ----------------1---------------
-1-StatusTests
0CoveredT2,T3,T4
1CoveredT2,T3,T4

 LINE       141
 SUB-EXPRESSION (((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512)) ? message_length_i[127:64] : '0)
                 -----------------------------------1----------------------------------
-1-StatusTestsExclude Annotation
0Excluded VC_COV_UNR
1CoveredT2,T3,T4

 LINE       141
 SUB-EXPRESSION ((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512))
                 ----------------1---------------    ----------------2---------------
-1--2-StatusTestsExclude Annotation
00Excluded VC_COV_UNR
01CoveredT2,T3,T4
10CoveredT2,T3,T4

 LINE       141
 SUB-EXPRESSION (digest_mode_flag_q == SHA2_384)
                ----------------1---------------
-1-StatusTests
0CoveredT2,T3,T4
1CoveredT2,T3,T4

 LINE       141
 SUB-EXPRESSION (digest_mode_flag_q == SHA2_512)
                ----------------1---------------
-1-StatusTests
0CoveredT2,T3,T4
1CoveredT2,T3,T4

 LINE       148
 EXPRESSION 
 Number  Term
      1  ((digest_mode_flag_q == SHA2_256) || ((~MultimodeEn))) ? ({32'b0, message_length_i[31:0]}) : (((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512)) ? message_length_i[63:0] : '0))
-1-StatusTests
0CoveredT2,T3,T4
1CoveredT2,T3,T4

 LINE       148
 SUB-EXPRESSION ((digest_mode_flag_q == SHA2_256) || ((~MultimodeEn)))
                 ----------------1---------------    --------2-------
-1--2-StatusTests
0-CoveredT2,T3,T4
1-CoveredT2,T3,T4

 LINE       148
 SUB-EXPRESSION (digest_mode_flag_q == SHA2_256)
                ----------------1---------------
-1-StatusTests
0CoveredT2,T3,T4
1CoveredT2,T3,T4

 LINE       148
 SUB-EXPRESSION (((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512)) ? message_length_i[63:0] : '0)
                 -----------------------------------1----------------------------------
-1-StatusTestsExclude Annotation
0Excluded VC_COV_UNR
1CoveredT2,T3,T4

 LINE       148
 SUB-EXPRESSION ((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512))
                 ----------------1---------------    ----------------2---------------
-1--2-StatusTestsExclude Annotation
00Excluded VC_COV_UNR
01CoveredT2,T3,T4
10CoveredT2,T3,T4

 LINE       148
 SUB-EXPRESSION (digest_mode_flag_q == SHA2_384)
                ----------------1---------------
-1-StatusTests
0CoveredT2,T3,T4
1CoveredT2,T3,T4

 LINE       148
 SUB-EXPRESSION (digest_mode_flag_q == SHA2_512)
                ----------------1---------------
-1-StatusTests
0CoveredT2,T3,T4
1CoveredT2,T3,T4

 LINE       206
 EXPRESSION (sha_en_i && hash_go)
             ----1---    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT2,T3,T4

 LINE       216
 EXPRESSION (fifo_partial && fifo_rvalid_i)
             ------1-----    ------2------
-1--2-StatusTests
01CoveredT2,T3,T4
10CoveredT2,T3,T4
11CoveredT2,T3,T4

 LINE       240
 EXPRESSION (txcnt_eq_msg_len && hash_stop_flag_q)
             --------1-------    --------2-------
-1--2-StatusTests
01CoveredT8,T17,T18
10CoveredT2,T3,T4
11CoveredT4,T5,T6

 LINE       251
 EXPRESSION 
 Number  Term
      1  ((digest_mode_flag_q == SHA2_256) || ((~MultimodeEn))) ? (shaf_rready_i && ((|message_length_i[4:3]))) : (((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512)) ? (shaf_rready_i && ((|message_length_i[5:3]))) : '0))
-1-StatusTests
0CoveredT2,T3,T4
1CoveredT2,T3,T4

 LINE       251
 SUB-EXPRESSION ((digest_mode_flag_q == SHA2_256) || ((~MultimodeEn)))
                 ----------------1---------------    --------2-------
-1--2-StatusTests
0-CoveredT2,T3,T4
1-CoveredT2,T3,T4

 LINE       251
 SUB-EXPRESSION (digest_mode_flag_q == SHA2_256)
                ----------------1---------------
-1-StatusTests
0CoveredT2,T3,T4
1CoveredT2,T3,T4

 LINE       251
 SUB-EXPRESSION (shaf_rready_i && ((|message_length_i[4:3])))
                 ------1------    -------------2------------
-1--2-StatusTests
01CoveredT2,T4,T6
10CoveredT2,T4,T5
11CoveredT2,T3,T4

 LINE       251
 SUB-EXPRESSION (((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512)) ? (shaf_rready_i && ((|message_length_i[5:3]))) : '0)
                 -----------------------------------1----------------------------------
-1-StatusTests
0Not Covered
1CoveredT2,T3,T4

 LINE       251
 SUB-EXPRESSION ((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512))
                 ----------------1---------------    ----------------2---------------
-1--2-StatusTests
00Not Covered
01CoveredT2,T3,T4
10CoveredT2,T3,T4

 LINE       251
 SUB-EXPRESSION (digest_mode_flag_q == SHA2_384)
                ----------------1---------------
-1-StatusTests
0CoveredT2,T3,T4
1CoveredT2,T3,T4

 LINE       251
 SUB-EXPRESSION (digest_mode_flag_q == SHA2_512)
                ----------------1---------------
-1-StatusTests
0CoveredT2,T3,T4
1CoveredT2,T3,T4

 LINE       251
 SUB-EXPRESSION (shaf_rready_i && ((|message_length_i[5:3])))
                 ------1------    -------------2------------
-1--2-StatusTests
01Not Covered
10CoveredT2,T3,T4
11CoveredT2,T3,T4

 LINE       257
 EXPRESSION (shaf_rready_i && txcnt_eq_1a0)
             ------1------    ------2-----
-1--2-StatusTests
01Not Covered
10CoveredT2,T3,T4
11CoveredT2,T5,T6

 LINE       263
 EXPRESSION (shaf_rready_i && ((!txcnt_eq_1a0)))
             ------1------    --------2--------
-1--2-StatusTestsExclude Annotation
01CoveredT2,T4,T5
10Excluded VC_COV_UNR
11CoveredT2,T3,T4

 LINE       355
 EXPRESSION ((digest_mode_flag_q == SHA2_256) || ((!MultimodeEn)))
             ----------------1---------------    --------2-------
-1--2-StatusTests
0-CoveredT2,T3,T4
1-CoveredT2,T3,T4

 LINE       355
 SUB-EXPRESSION (digest_mode_flag_q == SHA2_256)
                ----------------1---------------
-1-StatusTests
0CoveredT2,T3,T4
1CoveredT2,T3,T4

 LINE       357
 EXPRESSION ((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512))
             ----------------1---------------    ----------------2---------------
-1--2-StatusTests
00Not Covered
01CoveredT2,T3,T4
10CoveredT2,T3,T4

 LINE       357
 SUB-EXPRESSION (digest_mode_flag_q == SHA2_384)
                ----------------1---------------
-1-StatusTests
0CoveredT2,T3,T4
1CoveredT2,T3,T4

 LINE       357
 SUB-EXPRESSION (digest_mode_flag_q == SHA2_512)
                ----------------1---------------
-1-StatusTests
0CoveredT2,T3,T4
1CoveredT2,T3,T4

 LINE       368
 EXPRESSION ((hash_start_i || hash_continue_i) ? digest_mode_i : (hash_done_i ? SHA2_None : digest_mode_flag_q))
             ----------------1----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T4

 LINE       368
 SUB-EXPRESSION (hash_start_i || hash_continue_i)
                 ------1-----    -------2-------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT4,T5,T6
10CoveredT2,T3,T4

 LINE       368
 SUB-EXPRESSION (hash_done_i ? SHA2_None : digest_mode_flag_q)
                 -----1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T4

 LINE       378
 EXPRESSION ((hash_process_flag_q || hash_stop_flag_q) && (st_q == StIdle))
             --------------------1--------------------    --------2-------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T3,T4
11CoveredT2,T3,T4

 LINE       378
 SUB-EXPRESSION (hash_process_flag_q || hash_stop_flag_q)
                 ---------1---------    --------2-------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT4,T5,T6
10CoveredT2,T3,T4

 LINE       378
 SUB-EXPRESSION (st_q == StIdle)
                --------1-------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

FSM Coverage for Instance : tb.dut.u_prim_sha2_512.gen_multimode_logic.u_prim_sha2_multimode.u_pad
Summary for FSM :: st_q
TotalCoveredPercent
States 6 6 100.00 (Not included in score)
Transitions 11 11 100.00
Sequences 0 0

State, Transition and Sequence Details for FSM :: st_q
statesLine No.CoveredTests
StFifoReceive 208 Covered T2,T3,T4
StIdle 200 Covered T1,T2,T3
StLenHi 258 Covered T2,T3,T4
StLenLo 314 Covered T2,T3,T4
StPad00 264 Covered T2,T3,T4
StPad80 221 Covered T2,T3,T4


transitionsLine No.CoveredTestsExclude Annotation
StFifoReceive->StIdle 200 Covered T4,T5,T6
StFifoReceive->StPad80 221 Covered T2,T3,T4
StIdle->StFifoReceive 208 Covered T2,T3,T4
StLenHi->StFifoReceive 341 Excluded [INVALID] Intend to remove transition
StLenHi->StIdle 200 Covered T19
StLenHi->StLenLo 314 Covered T2,T3,T4
StLenLo->StFifoReceive 341 Excluded [INVALID] Intend to remove transition
StLenLo->StIdle 200 Covered T2,T3,T4
StPad00->StFifoReceive 341 Excluded [INVALID] Intend to remove transition
StPad00->StIdle 200 Covered T9,T20,T21
StPad00->StLenHi 302 Covered T2,T3,T4
StPad80->StFifoReceive 341 Excluded [INVALID] Intend to remove transition
StPad80->StIdle 200 Covered T7
StPad80->StLenHi 258 Covered T2,T5,T6
StPad80->StPad00 264 Covered T2,T3,T4



Branch Coverage for Instance : tb.dut.u_prim_sha2_512.gen_multimode_logic.u_prim_sha2_multimode.u_pad
Line No.TotalCoveredPercent
Branches 70 65 92.86
TERNARY 60 3 3 100.00
TERNARY 72 3 3 100.00
TERNARY 76 3 3 100.00
TERNARY 368 3 3 100.00
IF 81 2 2 100.00
CASE 101 19 18 94.74
IF 159 1 1 100.00
IF 190 2 2 100.00
CASE 202 21 18 85.71
IF 340 3 3 100.00
IF 348 6 5 83.33
IF 364 2 2 100.00
IF 373 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_sha2_0/rtl/prim_sha2_pad.sv' or '../src/lowrisc_prim_sha2_0/rtl/prim_sha2_pad.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 60 (((digest_mode_flag_q == SHA2_256) || (~MultimodeEn))) ? -2-: 60 (((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512))) ?

Branches:
-1--2-StatusTests
1 - Covered T2,T3,T4
0 1 Covered T2,T3,T4
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 72 ((((~sha_en_i) || hash_go) || hash_done_i)) ? -2-: 72 (hash_stop_i) ?

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T4,T5,T6
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 76 ((((~sha_en_i) || hash_go) || hash_done_i)) ? -2-: 76 (hash_process_i) ?

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T2,T3,T4
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 368 ((hash_start_i || hash_continue_i)) ? -2-: 368 (hash_done_i) ?

Branches:
-1--2-StatusTests
1 - Covered T2,T3,T4
0 1 Covered T2,T3,T4
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 81 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 101 case (sel_data) -2-: 112 if (((digest_mode_flag_q == SHA2_256) || (~MultimodeEn))) -3-: 113 case (message_length_i[4:3]) -4-: 120 if (((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512))) -5-: 121 case (message_length_i[5:3]) -6-: 141 (((digest_mode_flag_q == SHA2_256) || (~MultimodeEn))) ? -7-: 141 (((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512))) ? -8-: 148 (((digest_mode_flag_q == SHA2_256) || (~MultimodeEn))) ? -9-: 148 (((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512))) ?

Branches:
-1--2--3--4--5--6--7--8--9-StatusTestsExclude Annotation
FifoIn - - - - - - - - Covered T1,T2,T3
Pad80 1 2'b00 - - - - - - Covered T2,T4,T5
Pad80 1 2'b01 - - - - - - Covered T2,T3,T4
Pad80 1 2'b10 - - - - - - Covered T2,T3,T6
Pad80 1 2'b11 - - - - - - Covered T2,T5,T13
Pad80 1 default - - - - - - Excluded VC_COV_UNR
Pad80 0 - 1 3'b000 - - - - Covered T2,T3,T4
Pad80 0 - 1 3'b001 - - - - Covered T2,T3,T4
Pad80 0 - 1 3'b010 - - - - Covered T2,T4,T13
Pad80 0 - 1 3'b011 - - - - Covered T2,T5,T14
Pad80 0 - 1 3'b100 - - - - Covered T2,T5,T14
Pad80 0 - 1 3'b101 - - - - Covered T2,T3,T4
Pad80 0 - 1 3'b110 - - - - Covered T2,T3,T4
Pad80 0 - 1 3'b111 - - - - Covered T2,T3,T4
Pad80 0 - 1 default - - - - Excluded VC_COV_UNR
Pad80 0 - 0 - - - - - Not Covered
Pad00 - - - - - - - - Covered T2,T3,T4
LenHi - - - - 1 - - - Covered T2,T3,T4
LenHi - - - - 0 1 - - Covered T2,T3,T4
LenHi - - - - 0 0 - - Excluded VC_COV_UNR
LenLo - - - - - - 1 - Covered T2,T3,T4
LenLo - - - - - - 0 1 Covered T2,T3,T4
LenLo - - - - - - 0 0 Excluded VC_COV_UNR
default - - - - - - - - Excluded VC_COV_UNR


LineNo. Expression -1-: 159 if ((!MultimodeEn))

Branches:
-1-StatusTests
1 Unreachable
0 Covered T1,T2,T3


LineNo. Expression -1-: 190 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 202 case (st_q) -2-: 206 if ((sha_en_i && hash_go)) -3-: 216 if ((fifo_partial && fifo_rvalid_i)) -4-: 222 if ((!hash_process_flag_q)) -5-: 227 if (txcnt_eq_msg_len) -6-: 240 if ((txcnt_eq_msg_len && hash_stop_flag_q)) -7-: 251 (((digest_mode_flag_q == SHA2_256) || (~MultimodeEn))) ? -8-: 251 (((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512))) ? -9-: 257 if ((shaf_rready_i && txcnt_eq_1a0)) -10-: 263 if ((shaf_rready_i && (!txcnt_eq_1a0))) -11-: 300 if (shaf_rready_i) -12-: 302 if (txcnt_eq_1a0) -13-: 313 if (shaf_rready_i) -14-: 326 if (shaf_rready_i)

Branches:
-1--2--3--4--5--6--7--8--9--10--11--12--13--14-StatusTestsExclude Annotation
StIdle 1 - - - - - - - - - - - - Covered T2,T3,T4
StIdle 0 - - - - - - - - - - - - Covered T1,T2,T3
StFifoReceive - 1 - - - - - - - - - - - Covered T2,T3,T4
StFifoReceive - 0 1 - - - - - - - - - - Covered T2,T3,T4
StFifoReceive - 0 0 1 - - - - - - - - - Covered T2,T3,T4
StFifoReceive - 0 0 0 - - - - - - - - - Covered T5,T6,T7
StFifoReceive - - - - 1 - - - - - - - - Covered T4,T5,T6
StFifoReceive - - - - 0 - - - - - - - - Covered T2,T3,T4
StPad80 - - - - - 1 - - - - - - - Covered T2,T3,T4
StPad80 - - - - - 0 1 - - - - - - Covered T2,T3,T4
StPad80 - - - - - 0 0 - - - - - - Not Covered
StPad80 - - - - - - - 1 - - - - - Covered T2,T5,T6
StPad80 - - - - - - - 0 1 - - - - Covered T2,T3,T4
StPad80 - - - - - - - 0 0 - - - - Covered T2,T4,T5
StPad00 - - - - - - - - - 1 1 - - Covered T2,T3,T4
StPad00 - - - - - - - - - 1 0 - - Covered T2,T3,T4
StPad00 - - - - - - - - - 0 - - - Covered T2,T3,T4
StLenHi - - - - - - - - - - - 1 - Covered T2,T3,T4
StLenHi - - - - - - - - - - - 0 - Not Covered
StLenLo - - - - - - - - - - - - 1 Covered T2,T3,T4
StLenLo - - - - - - - - - - - - 0 Not Covered
default - - - - - - - - - - - - - Excluded VC_COV_UNR


LineNo. Expression -1-: 340 if ((!sha_en_i)) -2-: 341 if (hash_go)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T2,T3,T4
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 348 if (hash_start_i) -2-: 351 if (hash_continue_i) -3-: 354 if (inc_txcount) -4-: 355 if (((digest_mode_flag_q == SHA2_256) || (!MultimodeEn))) -5-: 357 if (((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512)))

Branches:
-1--2--3--4--5-StatusTests
1 - - - - Covered T2,T3,T4
0 1 - - - Covered T4,T5,T6
0 0 1 1 - Covered T2,T3,T4
0 0 1 0 1 Covered T2,T3,T4
0 0 1 0 0 Not Covered
0 0 0 - - Covered T1,T2,T3


LineNo. Expression -1-: 364 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 373 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%