Module Definition
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Module : prim_sha2
SCORELINECONDTOGGLEFSMBRANCHASSERT
93.96 98.58 95.17 90.00 92.11

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_sha2_0/rtl/prim_sha2.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_prim_sha2_512.gen_multimode_logic.u_prim_sha2_multimode 99.12 100.00 97.87 100.00 98.59



Module Instance : tb.dut.u_prim_sha2_512.gen_multimode_logic.u_prim_sha2_multimode

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.12 100.00 97.87 100.00 98.59


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.57 98.13 96.42 100.00 95.74


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.39 100.00 98.18 100.00 u_prim_sha2_512


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_pad 95.98 96.12 94.93 100.00 92.86

Line Coverage for Module : prim_sha2
Line No.TotalCoveredPercent
TOTAL14113998.58
CONT_ASSIGN7811100.00
CONT_ASSIGN8011100.00
ALWAYS921414100.00
ALWAYS11744100.00
ALWAYS1231010100.00
ALWAYS14033100.00
ALWAYS1461919100.00
ALWAYS17433100.00
CONT_ASSIGN17911100.00
ALWAYS27177100.00
ALWAYS28833100.00
CONT_ASSIGN29311100.00
ALWAYS29833100.00
CONT_ASSIGN30311100.00
ALWAYS30633100.00
CONT_ASSIGN31211100.00
ALWAYS31533100.00
ALWAYS3202626100.00
ALWAYS37133100.00
ALWAYS38533100.00
ALWAYS39233100.00
CONT_ASSIGN39611100.00
ALWAYS399232191.30
CONT_ASSIGN44911100.00
CONT_ASSIGN45311100.00
CONT_ASSIGN48011100.00
CONT_ASSIGN48311100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_sha2_0/rtl/prim_sha2.sv' or '../src/lowrisc_prim_sha2_0/rtl/prim_sha2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
78 1 1
80 1 1
92 1 1
93 1 1
94 1 1
95 1 1
96 1 1
97 1 1
100 1 1
101 1 1
102 1 1
104 1 1
106 1 1
107 1 1
==> MISSING_ELSE
109 1 1
111 1 1
MISSING_ELSE
117 2 2
118 2 2
==> MISSING_ELSE
123 1 1
124 1 1
125 1 1
126 1 1
127 1 1
128 1 1
129 1 1
130 1 1
132 1 1
133 1 1
==> MISSING_ELSE
MISSING_ELSE
140 2 2
141 1 1
146 1 1
147 1 1
148 1 1
149 1 1
150 1 1
151 1 1
152 1 1
153 1 1
154 1 1
155 1 1
156 1 1
==> MISSING_ELSE
159 1 1
160 1 1
161 1 1
162 1 1
163 1 1
165 1 1
166 1 1
167 1 1
MISSING_ELSE
174 2 2
175 1 1
179 1 1
271 1 1
272 1 1
273 1 1
274 1 1
275 1 1
279 1 1
281 1 1
MISSING_ELSE
288 2 2
289 1 1
293 1 1
298 2 2
299 1 1
303 1 1
306 2 2
307 1 1
312 1 1
315 2 2
316 1 1
320 1 1
321 1 1
322 1 1
324 1 1
326 2 2
327 1 1
331 1 1
333 1 1
334 1 1
335 1 1
336 1 1
338 1 1
340 1 1
341 1 1
346 1 1
347 1 1
349 1 1
350 1 1
351 1 1
353 1 1
362 1 1
363 1 1
364 1 1
365 1 1
366 1 1
MISSING_ELSE
371 2 2
372 1 1
385 2 2
386 1 1
392 2 2
393 1 1
396 1 1
399 1 1
400 1 1
401 1 1
402 1 1
403 1 1
405 1 1
407 1 1
408 1 1
409 1 1
411 1 1
416 1 1
417 1 1
420 1 1
421 1 1
422 1 1
424 1 1
429 1 1
430 1 1
431 0 1
432 0 1
434 1 1
443 2 2
MISSING_ELSE
449 1 1
453 1 1
480 1 1
483 1 1


Cond Coverage for Module : prim_sha2
TotalCoveredPercent
Conditions14513895.17
Logical14513895.17
Non-Logical00
Event00

 LINE       78
 EXPRESSION (hash_start_i | hash_continue_i)
             ------1-----   -------2-------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT4,T5,T6
10CoveredT2,T3,T4

 LINE       80
 EXPRESSION (hash_go ? digest_mode_i : (hash_done_o ? SHA2_None : digest_mode_flag_q))
             ---1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T4

 LINE       80
 SUB-EXPRESSION (hash_done_o ? SHA2_None : digest_mode_flag_q)
                 -----1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T4

 LINE       95
 EXPRESSION (((!sha_en_i)) || hash_go)
             ------1------    ---2---
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT2,T3,T4
10CoveredT1,T2,T3

 LINE       97
 EXPRESSION (((!run_hash)) && update_w_from_fifo)
             ------1------    ---------2--------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT2,T3,T4

 LINE       102
 EXPRESSION (digest_mode_flag_q == SHA2_256)
            ----------------1---------------
-1-StatusTests
0CoveredT2,T3,T4
1CoveredT2,T3,T4

 LINE       106
 EXPRESSION ((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512))
             ----------------1---------------    ----------------2---------------
-1--2-StatusTests
00Not Covered
01CoveredT2,T3,T4
10CoveredT2,T3,T4

 LINE       106
 SUB-EXPRESSION (digest_mode_flag_q == SHA2_384)
                ----------------1---------------
-1-StatusTests
0CoveredT2,T3,T4
1CoveredT2,T3,T4

 LINE       106
 SUB-EXPRESSION (digest_mode_flag_q == SHA2_512)
                ----------------1---------------
-1-StatusTests
0CoveredT2,T3,T4
1CoveredT2,T3,T4

 LINE       129
 EXPRESSION (digest_mode_flag_q == SHA2_256)
            ----------------1---------------
-1-StatusTests
0CoveredT2,T3,T4
1CoveredT2,T3,T4

 LINE       132
 EXPRESSION ((digest_mode_flag_q == SHA2_512) || (digest_mode_flag_q == SHA2_384))
             ----------------1---------------    ----------------2---------------
-1--2-StatusTests
00Not Covered
01CoveredT2,T3,T4
10CoveredT2,T3,T4

 LINE       132
 SUB-EXPRESSION (digest_mode_flag_q == SHA2_512)
                ----------------1---------------
-1-StatusTests
0CoveredT2,T3,T4
1CoveredT2,T3,T4

 LINE       132
 SUB-EXPRESSION (digest_mode_flag_q == SHA2_384)
                ----------------1---------------
-1-StatusTests
0CoveredT2,T3,T4
1CoveredT2,T3,T4

 LINE       151
 EXPRESSION (digest_mode_i == SHA2_256)
            -------------1-------------
-1-StatusTests
0CoveredT2,T3,T4
1CoveredT2,T3,T4

 LINE       153
 EXPRESSION (digest_mode_i == SHA2_384)
            -------------1-------------
-1-StatusTests
0CoveredT2,T3,T4
1CoveredT2,T3,T4

 LINE       155
 EXPRESSION (digest_mode_i == SHA2_512)
            -------------1-------------
-1-StatusTests
0Not Covered
1CoveredT2,T3,T4

 LINE       163
 EXPRESSION (digest_we_i[i] ? digest_i[i] : gen_multimode.digest_q[i])
             -------1------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT4,T5,T6

 LINE       272
 EXPRESSION (((!sha_en_i)) || hash_go)
             ------1------    ---2---
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT2,T3,T4
10CoveredT1,T2,T3

 LINE       293
 EXPRESSION ((((~sha_en_i)) || hash_go) ? '0 : (update_w_from_fifo ? ((w_index_q + 1)) : w_index_q))
             -------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       293
 SUB-EXPRESSION (((~sha_en_i)) || hash_go)
                 ------1------    ---2---
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT2,T3,T4
10CoveredT1,T2,T3

 LINE       293
 SUB-EXPRESSION (update_w_from_fifo ? ((w_index_q + 1)) : w_index_q)
                 ---------1--------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T4

 LINE       335
 EXPRESSION (w_index_q == 4'd15)
            ----------1---------
-1-StatusTests
0CoveredT2,T3,T4
1CoveredT2,T3,T4

 LINE       346
 EXPRESSION (msg_feed_complete && one_chunk_done)
             --------1--------    -------2------
-1--2-StatusTests
01CoveredT2,T3,T4
10CoveredT2,T3,T4
11CoveredT2,T3,T4

 LINE       396
 EXPRESSION (hash_start_i | (((~sha_en_i)) & sha_en_q))
             ------1-----   -------------2------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T4
10CoveredT2,T3,T4

 LINE       396
 SUB-EXPRESSION (((~sha_en_i)) & sha_en_q)
                 ------1------   ----2---
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T4

 LINE       407
 EXPRESSION (fifo_st_q == FifoWait)
            -----------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T4

 LINE       417
 EXPRESSION 
 Number  Term
      1  (((digest_mode_flag_q == SHA2_256) || ((~MultimodeEn))) && (round_q < 7'h30)) || 
      2  (((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512)) && (round_q < 7'h40)))
-1--2-StatusTests
00CoveredT2,T3,T4
01CoveredT2,T3,T4
10CoveredT2,T3,T4

 LINE       417
 SUB-EXPRESSION (((digest_mode_flag_q == SHA2_256) || ((~MultimodeEn))) && (round_q < 7'h30))
                 ---------------------------1--------------------------    --------2--------
-1--2-StatusTests
01CoveredT2,T3,T4
10CoveredT2,T3,T4
11CoveredT2,T3,T4

 LINE       417
 SUB-EXPRESSION ((digest_mode_flag_q == SHA2_256) || ((~MultimodeEn)))
                 ----------------1---------------    --------2-------
-1--2-StatusTests
0-CoveredT2,T3,T4
1-CoveredT2,T3,T4

 LINE       417
 SUB-EXPRESSION (digest_mode_flag_q == SHA2_256)
                ----------------1---------------
-1-StatusTests
0CoveredT2,T3,T4
1CoveredT2,T3,T4

 LINE       417
 SUB-EXPRESSION (((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512)) && (round_q < 7'h40))
                 -----------------------------------1----------------------------------    --------2--------
-1--2-StatusTests
01CoveredT2,T3,T4
10CoveredT2,T3,T4
11CoveredT2,T3,T4

 LINE       417
 SUB-EXPRESSION ((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512))
                 ----------------1---------------    ----------------2---------------
-1--2-StatusTests
00CoveredT2,T3,T4
01CoveredT2,T3,T4
10CoveredT2,T3,T4

 LINE       417
 SUB-EXPRESSION (digest_mode_flag_q == SHA2_384)
                ----------------1---------------
-1-StatusTests
0CoveredT2,T3,T4
1CoveredT2,T3,T4

 LINE       417
 SUB-EXPRESSION (digest_mode_flag_q == SHA2_512)
                ----------------1---------------
-1-StatusTests
0CoveredT2,T3,T4
1CoveredT2,T3,T4

 LINE       430
 EXPRESSION (fifo_st_q == FifoWait)
            -----------1-----------
-1-StatusTests
0CoveredT2,T3,T4
1Not Covered

 LINE       443
 EXPRESSION (((!sha_en_i)) || hash_go)
             ------1------    ---2---
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT2,T3,T4
10CoveredT1,T2,T3

 LINE       449
 EXPRESSION 
 Number  Term
      1  update_digest && 
      2  (fifo_st_q == FifoIdle) && 
      3  (((digest_mode_flag_q == SHA2_256) && (message_length_i[8:0] == '0)) || ((digest_mode_flag_q inside {SHA2_384, SHA2_512}) && (message_length_i[9:0] == '0))))
-1--2--3-StatusTests
011Not Covered
101CoveredT2,T3,T4
110CoveredT2,T3,T4
111CoveredT2,T3,T4

 LINE       449
 SUB-EXPRESSION (fifo_st_q == FifoIdle)
                -----------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       449
 SUB-EXPRESSION 
 Number  Term
      1  ((digest_mode_flag_q == SHA2_256) && (message_length_i[8:0] == '0)) || 
      2  ((digest_mode_flag_q inside {SHA2_384, SHA2_512}) && (message_length_i[9:0] == '0)))
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT2,T3,T4
10CoveredT2,T3,T4

 LINE       449
 SUB-EXPRESSION ((digest_mode_flag_q == SHA2_256) && (message_length_i[8:0] == '0))
                 ----------------1---------------    --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T3,T4
11CoveredT2,T3,T4

 LINE       449
 SUB-EXPRESSION (digest_mode_flag_q == SHA2_256)
                ----------------1---------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T4

 LINE       449
 SUB-EXPRESSION (message_length_i[8:0] == '0)
                --------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       449
 SUB-EXPRESSION ((digest_mode_flag_q inside {SHA2_384, SHA2_512}) && (message_length_i[9:0] == '0))
                 ------------------------1-----------------------    --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T3,T4
11CoveredT2,T3,T4

 LINE       449
 SUB-EXPRESSION (message_length_i[9:0] == '0)
                --------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       453
 EXPRESSION 
 Number  Term
      1  (((digest_mode_flag_q == SHA2_256) || ((~MultimodeEn))) && (round_q == 7'd63)) ? 1'b1 : ((((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512)) && (round_q == 7'd79)) ? 1'b1 : 1'b0))
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T4

 LINE       453
 SUB-EXPRESSION (((digest_mode_flag_q == SHA2_256) || ((~MultimodeEn))) && (round_q == 7'd63))
                 ---------------------------1--------------------------    ---------2--------
-1--2-StatusTests
01CoveredT2,T3,T4
10CoveredT2,T3,T4
11CoveredT2,T3,T4

 LINE       453
 SUB-EXPRESSION ((digest_mode_flag_q == SHA2_256) || ((~MultimodeEn)))
                 ----------------1---------------    --------2-------
-1--2-StatusTests
0-CoveredT1,T2,T3
1-CoveredT2,T3,T4

 LINE       453
 SUB-EXPRESSION (digest_mode_flag_q == SHA2_256)
                ----------------1---------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T4

 LINE       453
 SUB-EXPRESSION (round_q == 7'd63)
                ---------1--------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T4

 LINE       453
 SUB-EXPRESSION ((((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512)) && (round_q == 7'd79)) ? 1'b1 : 1'b0)
                 -----------------------------------------------1----------------------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T4

 LINE       453
 SUB-EXPRESSION (((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512)) && (round_q == 7'd79))
                 -----------------------------------1----------------------------------    ---------2--------
-1--2-StatusTests
01Not Covered
10CoveredT2,T3,T4
11CoveredT2,T3,T4

 LINE       453
 SUB-EXPRESSION ((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512))
                 ----------------1---------------    ----------------2---------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT2,T3,T4
10CoveredT2,T3,T4

 LINE       453
 SUB-EXPRESSION (digest_mode_flag_q == SHA2_384)
                ----------------1---------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T4

 LINE       453
 SUB-EXPRESSION (digest_mode_flag_q == SHA2_512)
                ----------------1---------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T4

 LINE       453
 SUB-EXPRESSION (round_q == 7'd79)
                ---------1--------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T4

 LINE       480
 EXPRESSION (init_hash | run_hash | update_digest)
             ----1----   ----2---   ------3------
-1--2--3-StatusTests
000CoveredT1,T2,T3
001CoveredT2,T3,T4
010CoveredT2,T3,T4
100CoveredT2,T3,T4

 LINE       483
 EXPRESSION ((fifo_st_q == FifoIdle) && (sha_st_q == ShaIdle) && ((!hash_go)))
             -----------1-----------    ----------2----------    ------3-----
-1--2--3-StatusTests
011CoveredT2,T3,T4
101CoveredT2,T3,T4
110CoveredT2,T3,T4
111CoveredT1,T2,T3

 LINE       483
 SUB-EXPRESSION (fifo_st_q == FifoIdle)
                -----------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       483
 SUB-EXPRESSION (sha_st_q == ShaIdle)
                ----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

FSM Coverage for Module : prim_sha2
Summary for FSM :: fifo_st_q
TotalCoveredPercent
States 3 3 100.00 (Not included in score)
Transitions 5 5 100.00
Sequences 0 0

State, Transition and Sequence Details for FSM :: fifo_st_q
statesLine No.CoveredTests
FifoIdle 320 Covered T1,T2,T3
FifoLoadFromFifo 326 Covered T2,T3,T4
FifoWait 336 Covered T2,T3,T4


transitionsLine No.CoveredTests
FifoIdle->FifoLoadFromFifo 326 Covered T2,T3,T4
FifoLoadFromFifo->FifoIdle 320 Covered T7,T20,T19
FifoLoadFromFifo->FifoWait 336 Covered T2,T3,T4
FifoWait->FifoIdle 320 Covered T2,T3,T4
FifoWait->FifoLoadFromFifo 351 Covered T2,T3,T4


Summary for FSM :: sha_st_q
TotalCoveredPercent
States 3 3 100.00 (Not included in score)
Transitions 5 4 80.00
Sequences 0 0

State, Transition and Sequence Details for FSM :: sha_st_q
statesLine No.CoveredTests
ShaCompress 409 Covered T2,T3,T4
ShaIdle 411 Covered T1,T2,T3
ShaUpdateDigest 422 Covered T2,T3,T4


transitionsLine No.CoveredTests
ShaCompress->ShaIdle 443 Covered T7,T8,T9
ShaCompress->ShaUpdateDigest 422 Covered T2,T3,T4
ShaIdle->ShaCompress 409 Covered T2,T3,T4
ShaUpdateDigest->ShaCompress 432 Not Covered
ShaUpdateDigest->ShaIdle 434 Covered T2,T3,T4



Branch Coverage for Module : prim_sha2
Line No.TotalCoveredPercent
Branches 76 70 92.11
TERNARY 80 3 3 100.00
TERNARY 293 3 3 100.00
TERNARY 453 3 3 100.00
IF 272 4 4 100.00
IF 288 2 2 100.00
IF 298 2 2 100.00
IF 306 2 2 100.00
IF 315 2 2 100.00
CASE 324 9 8 88.89
IF 362 3 3 100.00
IF 371 2 2 100.00
IF 385 2 2 100.00
IF 392 2 2 100.00
CASE 405 8 6 75.00
IF 443 2 2 100.00
IF 93 8 7 87.50
IF 117 3 2 66.67
IF 124 6 5 83.33
IF 140 2 2 100.00
IF 147 6 6 100.00
IF 174 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_sha2_0/rtl/prim_sha2.sv' or '../src/lowrisc_prim_sha2_0/rtl/prim_sha2.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 80 (hash_go) ? -2-: 80 (hash_done_o) ?

Branches:
-1--2-StatusTests
1 - Covered T2,T3,T4
0 1 Covered T2,T3,T4
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 293 (((~sha_en_i) || hash_go)) ? -2-: 293 (update_w_from_fifo) ?

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T2,T3,T4
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 453 ((((digest_mode_flag_q == SHA2_256) || (~MultimodeEn)) && (round_q == 7'd63))) ? -2-: 453 ((((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512)) && (round_q == 7'd79))) ?

Branches:
-1--2-StatusTests
1 - Covered T2,T3,T4
0 1 Covered T2,T3,T4
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 272 if (((!sha_en_i) || hash_go)) -2-: 274 if (run_hash) -3-: 275 if ((((round_q[(RndWidth256 - 1):0] == 6'((unsigned'((prim_sha2_pkg::NumRound256 - 1))))) && ((digest_mode_flag_q == SHA2_256) || (!MultimodeEn))) || ((round_q == 7'((unsigned'((prim_sha2_pkg::NumRound512 - 1))))) && ((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512)))))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 1 Covered T2,T3,T4
0 1 0 Covered T2,T3,T4
0 0 - Covered T1,T2,T3


LineNo. Expression -1-: 288 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 298 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 306 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 315 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 324 case (fifo_st_q) -2-: 326 if (hash_go) -3-: 331 if ((!shaf_rvalid)) -4-: 335 if ((w_index_q == 4'd15)) -5-: 346 if ((msg_feed_complete && one_chunk_done)) -6-: 350 if (one_chunk_done)

Branches:
-1--2--3--4--5--6-StatusTests
FifoIdle 1 - - - - Covered T2,T3,T4
FifoIdle 0 - - - - Covered T1,T2,T3
FifoLoadFromFifo - 1 - - - Covered T2,T3,T4
FifoLoadFromFifo - 0 1 - - Covered T2,T3,T4
FifoLoadFromFifo - 0 0 - - Covered T2,T3,T4
FifoWait - - - 1 - Covered T2,T3,T4
FifoWait - - - 0 1 Covered T2,T3,T4
FifoWait - - - 0 0 Covered T2,T3,T4
default - - - - - Not Covered


LineNo. Expression -1-: 362 if ((!sha_en_i)) -2-: 365 if (hash_go)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T2,T3,T4
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 371 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 385 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 392 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 405 case (sha_st_q) -2-: 407 if ((fifo_st_q == FifoWait)) -3-: 417 if (((((digest_mode_flag_q == SHA2_256) || (~MultimodeEn)) && (round_q < 7'h30)) || (((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512)) && (round_q < 7'h40)))) -4-: 421 if (one_chunk_done) -5-: 430 if ((fifo_st_q == FifoWait))

Branches:
-1--2--3--4--5-StatusTests
ShaIdle 1 - - - Covered T2,T3,T4
ShaIdle 0 - - - Covered T1,T2,T3
ShaCompress - 1 - - Covered T2,T3,T4
ShaCompress - 0 1 - Covered T2,T3,T4
ShaCompress - 0 0 - Covered T2,T3,T4
ShaUpdateDigest - - - 1 Not Covered
ShaUpdateDigest - - - 0 Covered T2,T3,T4
default - - - - Not Covered


LineNo. Expression -1-: 443 if (((!sha_en_i) || hash_go))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 93 if (wipe_secret_i) -2-: 95 if (((!sha_en_i) || hash_go)) -3-: 97 if (((!run_hash) && update_w_from_fifo)) -4-: 101 if (calculate_next_w) -5-: 102 if ((digest_mode_flag_q == SHA2_256)) -6-: 106 if (((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512))) -7-: 109 if (run_hash)

Branches:
-1--2--3--4--5--6--7-StatusTests
1 - - - - - - Covered T2,T3,T13
0 1 - - - - - Covered T1,T2,T3
0 0 1 - - - - Covered T2,T3,T4
0 0 0 1 1 - - Covered T2,T3,T4
0 0 0 1 0 1 - Covered T2,T3,T4
0 0 0 1 0 0 - Not Covered
0 0 0 0 - - 1 Covered T2,T3,T4
0 0 0 0 - - 0 Covered T1,T2,T3


LineNo. Expression -1-: 117 if ((!rst_ni)) -2-: 118 if (MultimodeEn)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Not Covered


LineNo. Expression -1-: 124 if (wipe_secret_i) -2-: 126 if (init_hash) -3-: 128 if (run_hash) -4-: 129 if ((digest_mode_flag_q == SHA2_256)) -5-: 132 if (((digest_mode_flag_q == SHA2_512) || (digest_mode_flag_q == SHA2_384)))

Branches:
-1--2--3--4--5-StatusTests
1 - - - - Covered T2,T3,T13
0 1 - - - Covered T2,T3,T4
0 0 1 1 - Covered T2,T3,T4
0 0 1 0 1 Covered T2,T3,T4
0 0 1 0 0 Not Covered
0 0 0 - - Covered T1,T2,T3


LineNo. Expression -1-: 140 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 147 if (wipe_secret_i) -2-: 149 if (hash_start_i) -3-: 159 if (clear_digest) -4-: 161 if ((!sha_en_i)) -5-: 165 if (update_digest)

Branches:
-1--2--3--4--5-StatusTests
1 - - - - Covered T2,T3,T13
0 1 - - - Covered T2,T3,T4
0 0 1 - - Covered T1,T2,T4
0 0 0 1 - Covered T1,T2,T3
0 0 0 0 1 Covered T2,T3,T4
0 0 0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 174 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_prim_sha2_512.gen_multimode_logic.u_prim_sha2_multimode
Line No.TotalCoveredPercent
TOTAL139139100.00
CONT_ASSIGN7811100.00
CONT_ASSIGN8011100.00
ALWAYS921414100.00
ALWAYS11744100.00
ALWAYS1231010100.00
ALWAYS14033100.00
ALWAYS1461919100.00
ALWAYS17433100.00
CONT_ASSIGN17911100.00
ALWAYS27177100.00
ALWAYS28833100.00
CONT_ASSIGN29311100.00
ALWAYS29833100.00
CONT_ASSIGN30311100.00
ALWAYS30633100.00
CONT_ASSIGN31211100.00
ALWAYS31533100.00
ALWAYS3202626100.00
ALWAYS37133100.00
ALWAYS38533100.00
ALWAYS39233100.00
CONT_ASSIGN39611100.00
ALWAYS3992121100.00
CONT_ASSIGN44911100.00
CONT_ASSIGN45311100.00
CONT_ASSIGN48011100.00
CONT_ASSIGN48311100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_sha2_0/rtl/prim_sha2.sv' or '../src/lowrisc_prim_sha2_0/rtl/prim_sha2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
78 1 1
80 1 1
92 1 1
93 1 1
94 1 1
95 1 1
96 1 1
97 1 1
100 1 1
101 1 1
102 1 1
104 1 1
106 1 1
107 1 1
==> MISSING_ELSE
109 1 1
111 1 1
MISSING_ELSE
117 2 2
118 2 2
==> MISSING_ELSE
123 1 1
124 1 1
125 1 1
126 1 1
127 1 1
128 1 1
129 1 1
130 1 1
132 1 1
133 1 1
==> MISSING_ELSE
MISSING_ELSE
140 2 2
141 1 1
146 1 1
147 1 1
148 1 1
149 1 1
150 1 1
151 1 1
152 1 1
153 1 1
154 1 1
155 1 1
156 1 1
==> MISSING_ELSE
159 1 1
160 1 1
161 1 1
162 1 1
163 1 1
165 1 1
166 1 1
167 1 1
MISSING_ELSE
174 2 2
175 1 1
179 1 1
271 1 1
272 1 1
273 1 1
274 1 1
275 1 1
279 1 1
281 1 1
MISSING_ELSE
288 2 2
289 1 1
293 1 1
298 2 2
299 1 1
303 1 1
306 2 2
307 1 1
312 1 1
315 2 2
316 1 1
320 1 1
321 1 1
322 1 1
324 1 1
326 2 2
327 1 1
331 1 1
333 1 1
334 1 1
335 1 1
336 1 1
338 1 1
340 1 1
341 1 1
346 1 1
347 1 1
349 1 1
350 1 1
351 1 1
353 1 1
Exclude Annotation: VC_COV_UNR
362 1 1
363 1 1
364 1 1
365 1 1
366 1 1
MISSING_ELSE
371 2 2
372 1 1
385 2 2
386 1 1
392 2 2
393 1 1
396 1 1
399 1 1
400 1 1
401 1 1
402 1 1
403 1 1
405 1 1
407 1 1
408 1 1
409 1 1
411 1 1
416 1 1
417 1 1
420 1 1
421 1 1
422 1 1
424 1 1
429 1 1
430 1 1
431 excluded
Exclude Annotation: VC_COV_UNR
432 excluded
Exclude Annotation: VC_COV_UNR
434 1 1
Exclude Annotation: VC_COV_UNR
443 2 2
MISSING_ELSE
449 1 1
453 1 1
480 1 1
483 1 1


Cond Coverage for Instance : tb.dut.u_prim_sha2_512.gen_multimode_logic.u_prim_sha2_multimode
TotalCoveredPercent
Conditions14113897.87
Logical14113897.87
Non-Logical00
Event00

 LINE       78
 EXPRESSION (hash_start_i | hash_continue_i)
             ------1-----   -------2-------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT4,T5,T6
10CoveredT2,T3,T4

 LINE       80
 EXPRESSION (hash_go ? digest_mode_i : (hash_done_o ? SHA2_None : digest_mode_flag_q))
             ---1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T4

 LINE       80
 SUB-EXPRESSION (hash_done_o ? SHA2_None : digest_mode_flag_q)
                 -----1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T4

 LINE       95
 EXPRESSION (((!sha_en_i)) || hash_go)
             ------1------    ---2---
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT2,T3,T4
10CoveredT1,T2,T3

 LINE       97
 EXPRESSION (((!run_hash)) && update_w_from_fifo)
             ------1------    ---------2--------
-1--2-StatusTestsExclude Annotation
01Excluded VC_COV_UNR
10CoveredT1,T2,T3
11CoveredT2,T3,T4

 LINE       102
 EXPRESSION (digest_mode_flag_q == SHA2_256)
            ----------------1---------------
-1-StatusTests
0CoveredT2,T3,T4
1CoveredT2,T3,T4

 LINE       106
 EXPRESSION ((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512))
             ----------------1---------------    ----------------2---------------
-1--2-StatusTestsExclude Annotation
00Excluded VC_COV_UNR
01CoveredT2,T3,T4
10CoveredT2,T3,T4

 LINE       106
 SUB-EXPRESSION (digest_mode_flag_q == SHA2_384)
                ----------------1---------------
-1-StatusTests
0CoveredT2,T3,T4
1CoveredT2,T3,T4

 LINE       106
 SUB-EXPRESSION (digest_mode_flag_q == SHA2_512)
                ----------------1---------------
-1-StatusTests
0CoveredT2,T3,T4
1CoveredT2,T3,T4

 LINE       129
 EXPRESSION (digest_mode_flag_q == SHA2_256)
            ----------------1---------------
-1-StatusTests
0CoveredT2,T3,T4
1CoveredT2,T3,T4

 LINE       132
 EXPRESSION ((digest_mode_flag_q == SHA2_512) || (digest_mode_flag_q == SHA2_384))
             ----------------1---------------    ----------------2---------------
-1--2-StatusTests
00Not Covered
01CoveredT2,T3,T4
10CoveredT2,T3,T4

 LINE       132
 SUB-EXPRESSION (digest_mode_flag_q == SHA2_512)
                ----------------1---------------
-1-StatusTests
0CoveredT2,T3,T4
1CoveredT2,T3,T4

 LINE       132
 SUB-EXPRESSION (digest_mode_flag_q == SHA2_384)
                ----------------1---------------
-1-StatusTests
0CoveredT2,T3,T4
1CoveredT2,T3,T4

 LINE       151
 EXPRESSION (digest_mode_i == SHA2_256)
            -------------1-------------
-1-StatusTests
0CoveredT2,T3,T4
1CoveredT2,T3,T4

 LINE       153
 EXPRESSION (digest_mode_i == SHA2_384)
            -------------1-------------
-1-StatusTests
0CoveredT2,T3,T4
1CoveredT2,T3,T4

 LINE       155
 EXPRESSION (digest_mode_i == SHA2_512)
            -------------1-------------
-1-StatusTestsExclude Annotation
0Excluded VC_COV_UNR
1CoveredT2,T3,T4

 LINE       163
 EXPRESSION (digest_we_i[i] ? digest_i[i] : gen_multimode.digest_q[i])
             -------1------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT4,T5,T6

 LINE       272
 EXPRESSION (((!sha_en_i)) || hash_go)
             ------1------    ---2---
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT2,T3,T4
10CoveredT1,T2,T3

 LINE       293
 EXPRESSION ((((~sha_en_i)) || hash_go) ? '0 : (update_w_from_fifo ? ((w_index_q + 1)) : w_index_q))
             -------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       293
 SUB-EXPRESSION (((~sha_en_i)) || hash_go)
                 ------1------    ---2---
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT2,T3,T4
10CoveredT1,T2,T3

 LINE       293
 SUB-EXPRESSION (update_w_from_fifo ? ((w_index_q + 1)) : w_index_q)
                 ---------1--------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T4

 LINE       335
 EXPRESSION (w_index_q == 4'd15)
            ----------1---------
-1-StatusTests
0CoveredT2,T3,T4
1CoveredT2,T3,T4

 LINE       346
 EXPRESSION (msg_feed_complete && one_chunk_done)
             --------1--------    -------2------
-1--2-StatusTests
01CoveredT2,T3,T4
10CoveredT2,T3,T4
11CoveredT2,T3,T4

 LINE       396
 EXPRESSION (hash_start_i | (((~sha_en_i)) & sha_en_q))
             ------1-----   -------------2------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T4
10CoveredT2,T3,T4

 LINE       396
 SUB-EXPRESSION (((~sha_en_i)) & sha_en_q)
                 ------1------   ----2---
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T4

 LINE       407
 EXPRESSION (fifo_st_q == FifoWait)
            -----------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T4

 LINE       417
 EXPRESSION 
 Number  Term
      1  (((digest_mode_flag_q == SHA2_256) || ((~MultimodeEn))) && (round_q < 7'h30)) || 
      2  (((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512)) && (round_q < 7'h40)))
-1--2-StatusTests
00CoveredT2,T3,T4
01CoveredT2,T3,T4
10CoveredT2,T3,T4

 LINE       417
 SUB-EXPRESSION (((digest_mode_flag_q == SHA2_256) || ((~MultimodeEn))) && (round_q < 7'h30))
                 ---------------------------1--------------------------    --------2--------
-1--2-StatusTests
01CoveredT2,T3,T4
10CoveredT2,T3,T4
11CoveredT2,T3,T4

 LINE       417
 SUB-EXPRESSION ((digest_mode_flag_q == SHA2_256) || ((~MultimodeEn)))
                 ----------------1---------------    --------2-------
-1--2-StatusTests
0-CoveredT2,T3,T4
1-CoveredT2,T3,T4

 LINE       417
 SUB-EXPRESSION (digest_mode_flag_q == SHA2_256)
                ----------------1---------------
-1-StatusTests
0CoveredT2,T3,T4
1CoveredT2,T3,T4

 LINE       417
 SUB-EXPRESSION (((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512)) && (round_q < 7'h40))
                 -----------------------------------1----------------------------------    --------2--------
-1--2-StatusTests
01CoveredT2,T3,T4
10CoveredT2,T3,T4
11CoveredT2,T3,T4

 LINE       417
 SUB-EXPRESSION ((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512))
                 ----------------1---------------    ----------------2---------------
-1--2-StatusTests
00CoveredT2,T3,T4
01CoveredT2,T3,T4
10CoveredT2,T3,T4

 LINE       417
 SUB-EXPRESSION (digest_mode_flag_q == SHA2_384)
                ----------------1---------------
-1-StatusTests
0CoveredT2,T3,T4
1CoveredT2,T3,T4

 LINE       417
 SUB-EXPRESSION (digest_mode_flag_q == SHA2_512)
                ----------------1---------------
-1-StatusTests
0CoveredT2,T3,T4
1CoveredT2,T3,T4

 LINE       430
 EXPRESSION (fifo_st_q == FifoWait)
            -----------1-----------
-1-StatusTestsExclude Annotation
0CoveredT2,T3,T4
1Excluded VC_COV_UNR

 LINE       443
 EXPRESSION (((!sha_en_i)) || hash_go)
             ------1------    ---2---
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT2,T3,T4
10CoveredT1,T2,T3

 LINE       449
 EXPRESSION 
 Number  Term
      1  update_digest && 
      2  (fifo_st_q == FifoIdle) && 
      3  (((digest_mode_flag_q == SHA2_256) && (message_length_i[8:0] == '0)) || ((digest_mode_flag_q inside {SHA2_384, SHA2_512}) && (message_length_i[9:0] == '0))))
-1--2--3-StatusTests
011Not Covered
101CoveredT2,T3,T4
110CoveredT2,T3,T4
111CoveredT2,T3,T4

 LINE       449
 SUB-EXPRESSION (fifo_st_q == FifoIdle)
                -----------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       449
 SUB-EXPRESSION 
 Number  Term
      1  ((digest_mode_flag_q == SHA2_256) && (message_length_i[8:0] == '0)) || 
      2  ((digest_mode_flag_q inside {SHA2_384, SHA2_512}) && (message_length_i[9:0] == '0)))
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT2,T3,T4
10CoveredT2,T3,T4

 LINE       449
 SUB-EXPRESSION ((digest_mode_flag_q == SHA2_256) && (message_length_i[8:0] == '0))
                 ----------------1---------------    --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T3,T4
11CoveredT2,T3,T4

 LINE       449
 SUB-EXPRESSION (digest_mode_flag_q == SHA2_256)
                ----------------1---------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T4

 LINE       449
 SUB-EXPRESSION (message_length_i[8:0] == '0)
                --------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       449
 SUB-EXPRESSION ((digest_mode_flag_q inside {SHA2_384, SHA2_512}) && (message_length_i[9:0] == '0))
                 ------------------------1-----------------------    --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T3,T4
11CoveredT2,T3,T4

 LINE       449
 SUB-EXPRESSION (message_length_i[9:0] == '0)
                --------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       453
 EXPRESSION 
 Number  Term
      1  (((digest_mode_flag_q == SHA2_256) || ((~MultimodeEn))) && (round_q == 7'd63)) ? 1'b1 : ((((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512)) && (round_q == 7'd79)) ? 1'b1 : 1'b0))
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T4

 LINE       453
 SUB-EXPRESSION (((digest_mode_flag_q == SHA2_256) || ((~MultimodeEn))) && (round_q == 7'd63))
                 ---------------------------1--------------------------    ---------2--------
-1--2-StatusTests
01CoveredT2,T3,T4
10CoveredT2,T3,T4
11CoveredT2,T3,T4

 LINE       453
 SUB-EXPRESSION ((digest_mode_flag_q == SHA2_256) || ((~MultimodeEn)))
                 ----------------1---------------    --------2-------
-1--2-StatusTests
0-CoveredT1,T2,T3
1-CoveredT2,T3,T4

 LINE       453
 SUB-EXPRESSION (digest_mode_flag_q == SHA2_256)
                ----------------1---------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T4

 LINE       453
 SUB-EXPRESSION (round_q == 7'd63)
                ---------1--------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T4

 LINE       453
 SUB-EXPRESSION ((((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512)) && (round_q == 7'd79)) ? 1'b1 : 1'b0)
                 -----------------------------------------------1----------------------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T4

 LINE       453
 SUB-EXPRESSION (((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512)) && (round_q == 7'd79))
                 -----------------------------------1----------------------------------    ---------2--------
-1--2-StatusTests
01Not Covered
10CoveredT2,T3,T4
11CoveredT2,T3,T4

 LINE       453
 SUB-EXPRESSION ((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512))
                 ----------------1---------------    ----------------2---------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT2,T3,T4
10CoveredT2,T3,T4

 LINE       453
 SUB-EXPRESSION (digest_mode_flag_q == SHA2_384)
                ----------------1---------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T4

 LINE       453
 SUB-EXPRESSION (digest_mode_flag_q == SHA2_512)
                ----------------1---------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T4

 LINE       453
 SUB-EXPRESSION (round_q == 7'd79)
                ---------1--------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T4

 LINE       480
 EXPRESSION (init_hash | run_hash | update_digest)
             ----1----   ----2---   ------3------
-1--2--3-StatusTests
000CoveredT1,T2,T3
001CoveredT2,T3,T4
010CoveredT2,T3,T4
100CoveredT2,T3,T4

 LINE       483
 EXPRESSION ((fifo_st_q == FifoIdle) && (sha_st_q == ShaIdle) && ((!hash_go)))
             -----------1-----------    ----------2----------    ------3-----
-1--2--3-StatusTests
011CoveredT2,T3,T4
101CoveredT2,T3,T4
110CoveredT2,T3,T4
111CoveredT1,T2,T3

 LINE       483
 SUB-EXPRESSION (fifo_st_q == FifoIdle)
                -----------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       483
 SUB-EXPRESSION (sha_st_q == ShaIdle)
                ----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

FSM Coverage for Instance : tb.dut.u_prim_sha2_512.gen_multimode_logic.u_prim_sha2_multimode
Summary for FSM :: fifo_st_q
TotalCoveredPercent
States 3 3 100.00 (Not included in score)
Transitions 5 5 100.00
Sequences 0 0

State, Transition and Sequence Details for FSM :: fifo_st_q
statesLine No.CoveredTests
FifoIdle 320 Covered T1,T2,T3
FifoLoadFromFifo 326 Covered T2,T3,T4
FifoWait 336 Covered T2,T3,T4


transitionsLine No.CoveredTests
FifoIdle->FifoLoadFromFifo 326 Covered T2,T3,T4
FifoLoadFromFifo->FifoIdle 320 Covered T7,T20,T19
FifoLoadFromFifo->FifoWait 336 Covered T2,T3,T4
FifoWait->FifoIdle 320 Covered T2,T3,T4
FifoWait->FifoLoadFromFifo 351 Covered T2,T3,T4


Summary for FSM :: sha_st_q
TotalCoveredPercent
States 3 3 100.00 (Not included in score)
Transitions 4 4 100.00
Sequences 0 0

State, Transition and Sequence Details for FSM :: sha_st_q
statesLine No.CoveredTests
ShaCompress 409 Covered T2,T3,T4
ShaIdle 411 Covered T1,T2,T3
ShaUpdateDigest 422 Covered T2,T3,T4


transitionsLine No.CoveredTestsExclude Annotation
ShaCompress->ShaIdle 443 Covered T7,T8,T9
ShaCompress->ShaUpdateDigest 422 Covered T2,T3,T4
ShaIdle->ShaCompress 409 Covered T2,T3,T4
ShaUpdateDigest->ShaCompress 432 Excluded VC_COV_UNR
ShaUpdateDigest->ShaIdle 434 Covered T2,T3,T4



Branch Coverage for Instance : tb.dut.u_prim_sha2_512.gen_multimode_logic.u_prim_sha2_multimode
Line No.TotalCoveredPercent
Branches 71 70 98.59
TERNARY 80 3 3 100.00
TERNARY 293 3 3 100.00
TERNARY 453 3 3 100.00
IF 272 4 4 100.00
IF 288 2 2 100.00
IF 298 2 2 100.00
IF 306 2 2 100.00
IF 315 2 2 100.00
CASE 324 8 8 100.00
IF 362 3 3 100.00
IF 371 2 2 100.00
IF 385 2 2 100.00
IF 392 2 2 100.00
CASE 405 6 6 100.00
IF 443 2 2 100.00
IF 93 7 7 100.00
IF 117 2 2 100.00
IF 124 6 5 83.33
IF 140 2 2 100.00
IF 147 6 6 100.00
IF 174 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_sha2_0/rtl/prim_sha2.sv' or '../src/lowrisc_prim_sha2_0/rtl/prim_sha2.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 80 (hash_go) ? -2-: 80 (hash_done_o) ?

Branches:
-1--2-StatusTests
1 - Covered T2,T3,T4
0 1 Covered T2,T3,T4
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 293 (((~sha_en_i) || hash_go)) ? -2-: 293 (update_w_from_fifo) ?

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T2,T3,T4
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 453 ((((digest_mode_flag_q == SHA2_256) || (~MultimodeEn)) && (round_q == 7'd63))) ? -2-: 453 ((((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512)) && (round_q == 7'd79))) ?

Branches:
-1--2-StatusTests
1 - Covered T2,T3,T4
0 1 Covered T2,T3,T4
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 272 if (((!sha_en_i) || hash_go)) -2-: 274 if (run_hash) -3-: 275 if ((((round_q[(RndWidth256 - 1):0] == 6'((unsigned'((prim_sha2_pkg::NumRound256 - 1))))) && ((digest_mode_flag_q == SHA2_256) || (!MultimodeEn))) || ((round_q == 7'((unsigned'((prim_sha2_pkg::NumRound512 - 1))))) && ((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512)))))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 1 Covered T2,T3,T4
0 1 0 Covered T2,T3,T4
0 0 - Covered T1,T2,T3


LineNo. Expression -1-: 288 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 298 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 306 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 315 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 324 case (fifo_st_q) -2-: 326 if (hash_go) -3-: 331 if ((!shaf_rvalid)) -4-: 335 if ((w_index_q == 4'd15)) -5-: 346 if ((msg_feed_complete && one_chunk_done)) -6-: 350 if (one_chunk_done)

Branches:
-1--2--3--4--5--6-StatusTestsExclude Annotation
FifoIdle 1 - - - - Covered T2,T3,T4
FifoIdle 0 - - - - Covered T1,T2,T3
FifoLoadFromFifo - 1 - - - Covered T2,T3,T4
FifoLoadFromFifo - 0 1 - - Covered T2,T3,T4
FifoLoadFromFifo - 0 0 - - Covered T2,T3,T4
FifoWait - - - 1 - Covered T2,T3,T4
FifoWait - - - 0 1 Covered T2,T3,T4
FifoWait - - - 0 0 Covered T2,T3,T4
default - - - - - Excluded VC_COV_UNR


LineNo. Expression -1-: 362 if ((!sha_en_i)) -2-: 365 if (hash_go)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T2,T3,T4
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 371 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 385 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 392 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 405 case (sha_st_q) -2-: 407 if ((fifo_st_q == FifoWait)) -3-: 417 if (((((digest_mode_flag_q == SHA2_256) || (~MultimodeEn)) && (round_q < 7'h30)) || (((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512)) && (round_q < 7'h40)))) -4-: 421 if (one_chunk_done) -5-: 430 if ((fifo_st_q == FifoWait))

Branches:
-1--2--3--4--5-StatusTestsExclude Annotation
ShaIdle 1 - - - Covered T2,T3,T4
ShaIdle 0 - - - Covered T1,T2,T3
ShaCompress - 1 - - Covered T2,T3,T4
ShaCompress - 0 1 - Covered T2,T3,T4
ShaCompress - 0 0 - Covered T2,T3,T4
ShaUpdateDigest - - - 1 Excluded VC_COV_UNR
ShaUpdateDigest - - - 0 Covered T2,T3,T4
default - - - - Excluded VC_COV_UNR


LineNo. Expression -1-: 443 if (((!sha_en_i) || hash_go))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 93 if (wipe_secret_i) -2-: 95 if (((!sha_en_i) || hash_go)) -3-: 97 if (((!run_hash) && update_w_from_fifo)) -4-: 101 if (calculate_next_w) -5-: 102 if ((digest_mode_flag_q == SHA2_256)) -6-: 106 if (((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512))) -7-: 109 if (run_hash)

Branches:
-1--2--3--4--5--6--7-StatusTestsExclude Annotation
1 - - - - - - Covered T2,T3,T13
0 1 - - - - - Covered T1,T2,T3
0 0 1 - - - - Covered T2,T3,T4
0 0 0 1 1 - - Covered T2,T3,T4
0 0 0 1 0 1 - Covered T2,T3,T4
0 0 0 1 0 0 - Excluded VC_COV_UNR
0 0 0 0 - - 1 Covered T2,T3,T4
0 0 0 0 - - 0 Covered T1,T2,T3


LineNo. Expression -1-: 117 if ((!rst_ni)) -2-: 118 if (MultimodeEn)

Branches:
-1--2-StatusTestsExclude Annotation
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Excluded VC_COV_UNR


LineNo. Expression -1-: 124 if (wipe_secret_i) -2-: 126 if (init_hash) -3-: 128 if (run_hash) -4-: 129 if ((digest_mode_flag_q == SHA2_256)) -5-: 132 if (((digest_mode_flag_q == SHA2_512) || (digest_mode_flag_q == SHA2_384)))

Branches:
-1--2--3--4--5-StatusTests
1 - - - - Covered T2,T3,T13
0 1 - - - Covered T2,T3,T4
0 0 1 1 - Covered T2,T3,T4
0 0 1 0 1 Covered T2,T3,T4
0 0 1 0 0 Not Covered
0 0 0 - - Covered T1,T2,T3


LineNo. Expression -1-: 140 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 147 if (wipe_secret_i) -2-: 149 if (hash_start_i) -3-: 159 if (clear_digest) -4-: 161 if ((!sha_en_i)) -5-: 165 if (update_digest)

Branches:
-1--2--3--4--5-StatusTests
1 - - - - Covered T2,T3,T13
0 1 - - - Covered T2,T3,T4
0 0 1 - - Covered T1,T2,T4
0 0 0 1 - Covered T1,T2,T3
0 0 0 0 1 Covered T2,T3,T4
0 0 0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 174 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3

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