Unified Coverage Report :: Module :: hmac_csr_assert_fpv

Module : hmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_hmac_csr_assert_0/hmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.hmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.hmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.71	100.00	93.33	100.00	100.00	98.90	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : hmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	514677709	2125428	0	0
intr_enable_rd_A	514677709	3504	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	514677709	2125428	0	0
T6	136851	50065	0	0
T7	0	277758	0	0
T8	0	110294	0	0
T11	0	111646	0	0
T12	0	169206	0	0
T13	0	58484	0	0
T23	0	307675	0	0
T24	0	292448	0	0
T36	348356	0	0	0
T44	8252	0	0	0
T45	6393	0	0	0
T49	1086	0	0	0
T50	44379	0	0	0
T51	295142	0	0	0
T52	210870	0	0	0
T61	0	175965	0	0
T62	0	316053	0	0
T63	123726	0	0	0
T64	70626	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	514677709	3504	0	0
T11	0	151	0	0
T12	0	132	0	0
T33	0	45	0	0
T60	851270	61	0	0
T65	0	44	0	0
T66	0	45	0	0
T67	0	14	0	0
T68	0	17	0	0
T69	0	29	0	0
T70	0	40	0	0
T71	109823	0	0	0
T72	577503	0	0	0
T73	1451	0	0	0
T74	67623	0	0	0
T75	29236	0	0	0
T76	216286	0	0	0
T77	100331	0	0	0
T78	851419	0	0	0
T79	1082	0	0	0