Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : hmac
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.93 100.00 90.81 100.00 100.00 96.77 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_hmac_0.1/rtl/hmac.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut 98.71 100.00 93.33 100.00 100.00 98.90 100.00



Module Instance : tb.dut

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.71 100.00 93.33 100.00 100.00 98.90 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.73 95.40 97.17 100.00 97.06 98.27 98.48


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
tb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_alert_tx[0].u_prim_alert_sender 100.00 100.00
hmac_csr_assert 100.00 100.00
intr_hw_fifo_empty 100.00 100.00 100.00 100.00 100.00
intr_hw_hmac_done 100.00 100.00 100.00 100.00 100.00
intr_hw_hmac_err 100.00 100.00 100.00 100.00 100.00
tlul_assert_device 100.00 100.00 100.00 100.00
u_hmac 98.46 100.00 96.15 100.00 97.70
u_msg_fifo 100.00 100.00 100.00 100.00 100.00
u_packer 97.51 100.00 93.75 96.30 100.00
u_prim_sha2_512 96.72 98.60 96.71 95.00 96.59
u_reg 98.15 93.17 97.59 100.00 100.00 100.00
u_tlul_adapter 92.44 90.04 100.00 98.48 81.25

Line Coverage for Module : hmac
Line No.TotalCoveredPercent
TOTAL198198100.00
CONT_ASSIGN13511100.00
CONT_ASSIGN13611100.00
CONT_ASSIGN13711100.00
CONT_ASSIGN13811100.00
ALWAYS1501515100.00
ALWAYS19233100.00
CONT_ASSIGN19911100.00
CONT_ASSIGN20011100.00
ALWAYS20477100.00
ALWAYS21933100.00
ALWAYS2311919100.00
CONT_ASSIGN27711100.00
CONT_ASSIGN28211100.00
CONT_ASSIGN28311100.00
CONT_ASSIGN28511100.00
ALWAYS28755100.00
CONT_ASSIGN30111100.00
ALWAYS30433100.00
CONT_ASSIGN30811100.00
ALWAYS31077100.00
CONT_ASSIGN32511100.00
CONT_ASSIGN32611100.00
CONT_ASSIGN32711100.00
CONT_ASSIGN32911100.00
CONT_ASSIGN33011100.00
CONT_ASSIGN33111100.00
CONT_ASSIGN33211100.00
CONT_ASSIGN33311100.00
CONT_ASSIGN33411100.00
CONT_ASSIGN33511100.00
CONT_ASSIGN33711100.00
CONT_ASSIGN33811100.00
CONT_ASSIGN33911100.00
CONT_ASSIGN34011100.00
CONT_ASSIGN34311100.00
CONT_ASSIGN34411100.00
CONT_ASSIGN34911100.00
CONT_ASSIGN35011100.00
CONT_ASSIGN35111100.00
CONT_ASSIGN35211100.00
ALWAYS35566100.00
ALWAYS36544100.00
ALWAYS40466100.00
CONT_ASSIGN45411100.00
CONT_ASSIGN45511100.00
CONT_ASSIGN46211100.00
CONT_ASSIGN47011100.00
CONT_ASSIGN47211100.00
ALWAYS47577100.00
CONT_ASSIGN51811100.00
CONT_ASSIGN52111100.00
CONT_ASSIGN52711100.00
CONT_ASSIGN53211100.00
CONT_ASSIGN53311100.00
CONT_ASSIGN53511100.00
CONT_ASSIGN53611100.00
CONT_ASSIGN53711100.00
ALWAYS54299100.00
CONT_ASSIGN61711100.00
ALWAYS62233100.00
ALWAYS63033100.00
ALWAYS6351010100.00
CONT_ASSIGN65211100.00
CONT_ASSIGN65311100.00
CONT_ASSIGN66011100.00
CONT_ASSIGN66111100.00
CONT_ASSIGN77111100.00
CONT_ASSIGN80011100.00
CONT_ASSIGN80111100.00
CONT_ASSIGN80211100.00
CONT_ASSIGN80711100.00
CONT_ASSIGN81211100.00
ALWAYS81566100.00
CONT_ASSIGN83111100.00
ALWAYS83777100.00
CONT_ASSIGN88011100.00
CONT_ASSIGN88411100.00
ALWAYS88633100.00
CONT_ASSIGN89211100.00
ALWAYS91466100.00
ALWAYS92166100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_hmac_0.1/rtl/hmac.sv' or '../src/lowrisc_ip_hmac_0.1/rtl/hmac.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
135 1 1
136 1 1
137 1 1
138 1 1
150 1 1
151 1 1
153 1 1
155 1 1
157 1 1
158 1 1
160 1 1
MISSING_ELSE
165 1 1
166 1 1
167 1 1
MISSING_ELSE
172 1 1
176 1 1
MISSING_ELSE
181 1 1
182 1 1
183 1 1
==> MISSING_ELSE
192 1 1
193 1 1
195 1 1
199 1 1
200 1 1
204 1 1
205 1 1
206 1 1
207 1 1
209 1 1
210 1 1
212 1 1
MISSING_ELSE
MISSING_ELSE
219 2 2
220 1 1
231 1 1
232 1 1
234 1 1
236 1 1
240 1 1
242 1 1
243 1 1
244 1 1
246 1 1
249 1 1
252 1 1
MISSING_ELSE
256 1 1
257 1 1
261 1 1
262 1 1
266 1 1
267 1 1
270 1 1
271 1 1
277 1 1
282 1 1
283 1 1
285 1 1
287 1 1
289 1 1
290 1 1
291 1 1
292 1 1
301 1 1
304 2 2
305 1 1
308 1 1
310 1 1
312 1 1
313 1 1
314 1 1
315 1 1
316 1 1
317 1 1
325 1 1
326 1 1
327 1 1
329 1 1
330 1 1
331 1 1
332 1 1
333 1 1
334 1 1
335 1 1
337 1 1
338 1 1
339 1 1
340 1 1
343 1 1
344 1 1
349 1 1
350 1 1
351 1 1
352 1 1
355 1 1
356 1 1
357 1 1
358 1 1
359 1 1
360 1 1
MISSING_ELSE
365 1 1
366 1 1
397 1 1
398 1 1
MISSING_ELSE
404 1 1
405 1 1
406 1 1
407 1 1
408 1 1
409 1 1
MISSING_ELSE
454 1 1
455 1 1
462 1 1
470 1 1
472 1 1
475 1 1
476 1 1
477 1 1
478 1 1
480 1 1
481 1 1
482 1 1
518 1 1
521 1 1
527 1 1
532 1 1
533 1 1
535 1 1
536 1 1
537 1 1
542 1 1
543 1 1
545 1 1
546 1 1
547 1 1
549 1 1
550 1 1
552 1 1
553 1 1
==> MISSING_ELSE
MISSING_ELSE
617 1 1
622 1 1
623 1 1
624 1 1
630 2 2
631 1 1
635 1 1
636 1 1
637 1 1
638 1 1
MISSING_ELSE
640 1 1
641 1 1
MISSING_ELSE
MISSING_ELSE
645 1 1
646 1 1
647 1 1
648 1 1
MISSING_ELSE
652 1 1
653 1 1
660 1 1
661 1 1
771 1 1
800 1 1
801 1 1
802 1 1
807 1 1
812 1 1
815 1 1
816 1 1
817 1 1
818 1 1
819 1 1
MISSING_ELSE
823 1 1
831 1 1
837 1 1
839 1 1
842 1 1
846 1 1
850 1 1
854 1 1
858 1 1
880 1 1
884 1 1
886 1 1
887 1 1
889 1 1
892 1 1
914 2 2
915 2 2
916 2 2
MISSING_ELSE
921 2 2
922 2 2
923 2 2
MISSING_ELSE


Cond Coverage for Module : hmac
TotalCoveredPercent
Conditions18516890.81
Logical18516890.81
Non-Logical00
Event00

 LINE       240
 EXPRESSION (digest_size == SHA2_256)
            ------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T4

 LINE       244
 EXPRESSION ((digest_size == SHA2_384) || (digest_size == SHA2_512))
             ------------1------------    ------------2------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3

 LINE       244
 SUB-EXPRESSION (digest_size == SHA2_384)
                ------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       244
 SUB-EXPRESSION (digest_size == SHA2_512)
                ------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       246
 EXPRESSION (reg2hw.digest[(2 * i)].qe ? prim_sha2_pkg::conv_endian32(reg2hw.digest[(2 * i)].q, digest_swap) : digest[i][63:32])
             ------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT4,T5,T15

 LINE       249
 EXPRESSION (reg2hw.digest[((2 * i) + 1)].qe ? prim_sha2_pkg::conv_endian32(reg2hw.digest[((2 * i) + 1)].q, digest_swap) : digest[i][31:0])
             ---------------1---------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT4,T5,T15

 LINE       252
 EXPRESSION (reg2hw.digest[(2 * i)].qe | reg2hw.digest[((2 * i) + 1)].qe)
             ------------1------------   ---------------2---------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT4,T5,T15
10CoveredT4,T5,T15

 LINE       256
 EXPRESSION (digest_size_started_q == SHA2_256)
            -----------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T4

 LINE       262
 EXPRESSION ((digest_size_started_q == SHA2_384) || (digest_size_started_q == SHA2_512))
             -----------------1-----------------    -----------------2-----------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3

 LINE       262
 SUB-EXPRESSION (digest_size_started_q == SHA2_384)
                -----------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       262
 SUB-EXPRESSION (digest_size_started_q == SHA2_512)
                -----------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       301
 EXPRESSION (hash_start_or_continue ? digest_size : digest_size_started_q)
             -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       337
 EXPRESSION (reg2hw.cmd.hash_start.qe & reg2hw.cmd.hash_start.q)
             ------------1-----------   -----------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       338
 EXPRESSION (reg2hw.cmd.hash_stop.qe & reg2hw.cmd.hash_stop.q)
             -----------1-----------   -----------2----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT3,T4,T5

 LINE       339
 EXPRESSION (reg2hw.cmd.hash_continue.qe & reg2hw.cmd.hash_continue.q)
             -------------1-------------   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT3,T4,T5

 LINE       340
 EXPRESSION (reg2hw.cmd.hash_process.qe & reg2hw.cmd.hash_process.q)
             -------------1------------   ------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       349
 EXPRESSION (reg_hash_start & sha_en & ((~cfg_block)) & ((~invalid_config)))
             -------1------   ---2--   -------3------   ---------4---------
-1--2--3--4-StatusTests
0111CoveredT1,T2,T3
1011CoveredT4,T25,T29
1101CoveredT4,T40,T25
1110CoveredT1,T2,T3
1111CoveredT1,T2,T3

 LINE       350
 EXPRESSION (reg_hash_continue & sha_en & ((~cfg_block)) & ((~invalid_config)))
             --------1--------   ---2--   -------3------   ---------4---------
-1--2--3--4-StatusTests
0111CoveredT1,T2,T3
1011Not Covered
1101Not Covered
1110Not Covered
1111CoveredT3,T4,T5

 LINE       351
 EXPRESSION (reg_hash_process & sha_en & cfg_block & ((~invalid_config)))
             --------1-------   ---2--   ----3----   ---------4---------
-1--2--3--4-StatusTests
0111CoveredT1,T2,T3
1011Not Covered
1101Not Covered
1110Not Covered
1111CoveredT1,T2,T3

 LINE       352
 EXPRESSION (hash_start | hash_continue)
             -----1----   ------2------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT3,T4,T5
10CoveredT1,T2,T3

 LINE       359
 EXPRESSION (reg_hash_done || reg_hash_stop)
             ------1------    ------2------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT3,T4,T5
10CoveredT1,T2,T3

 LINE       397
 EXPRESSION (((!cfg_block)) && reg2hw.cfg.hmac_en.qe)
             -------1------    ----------2----------
-1--2-StatusTests
01CoveredT4,T22,T40
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       454
 EXPRESSION (fifo_empty_q & ((~fifo_empty)))
             ------1-----   -------2-------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       455
 EXPRESSION (((~fifo_full_q)) & fifo_full)
             --------1-------   ----2----
-1--2-StatusTests
01CoveredT17,T25,T9
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       462
 EXPRESSION 
 Number  Term
      1  (reg_hash_start || reg_hash_continue || reg_hash_process || reg_hash_stop) ? 1'b0 : (fifo_empty_negedge ? 1'b0 : (fifo_full_posedge ? 1'b1 : fifo_full_seen_q)))
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       462
 SUB-EXPRESSION (reg_hash_start || reg_hash_continue || reg_hash_process || reg_hash_stop)
                 -------1------    --------2--------    --------3-------    ------4------
-1--2--3--4-StatusTests
0000CoveredT1,T2,T3
0001CoveredT3,T4,T5
0010CoveredT1,T2,T3
0100CoveredT3,T4,T5
1000CoveredT1,T2,T3

 LINE       462
 SUB-EXPRESSION (fifo_empty_negedge ? 1'b0 : (fifo_full_posedge ? 1'b1 : fifo_full_seen_q))
                 ---------1--------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       462
 SUB-EXPRESSION (fifo_full_posedge ? 1'b1 : fifo_full_seen_q)
                 --------1--------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       470
 EXPRESSION (((~msg_allowed)) || ((~fifo_full_seen_q)))
             --------1-------    ----------2----------
-1--2-StatusTests
00CoveredT17,T25,T9
01CoveredT1,T2,T3
10CoveredT1,T2,T3

 LINE       472
 EXPRESSION (fifo_empty_gate ? 1'b0 : fifo_empty)
             -------1-------
-1-StatusTests
0CoveredT17,T25,T9
1CoveredT1,T2,T3

 LINE       518
 EXPRESSION (msg_fifo_req & ((~msg_fifo_we)))
             ------1-----   --------2-------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11Not Covered

 LINE       521
 EXPRESSION (msg_fifo_req & ((~hmac_fifo_wsel)) & packer_ready)
             ------1-----   ---------2---------   ------3-----
-1--2--3-StatusTests
011CoveredT1,T2,T3
101Not Covered
110UnreachableT9,T6,T10
111CoveredT1,T2,T3

 LINE       537
 EXPRESSION ((hmac_fifo_wsel && fifo_wready) ? hmac_fifo_wvalid : reg_fifo_wvalid)
             ---------------1---------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       537
 SUB-EXPRESSION (hmac_fifo_wsel && fifo_wready)
                 -------1------    -----2-----
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T2,T3

 LINE       547
 EXPRESSION (digest_size == SHA2_256)
            ------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T4

 LINE       550
 EXPRESSION ((digest_size == SHA2_384) || (digest_size == SHA2_512))
             ------------1------------    ------------2------------
-1--2-StatusTests
00Not Covered
01CoveredT1,T3,T4
10CoveredT1,T2,T3

 LINE       550
 SUB-EXPRESSION (digest_size == SHA2_384)
                ------------1------------
-1-StatusTests
0CoveredT1,T3,T4
1CoveredT1,T2,T3

 LINE       550
 SUB-EXPRESSION (digest_size == SHA2_512)
                ------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T4

 LINE       564
 EXPRESSION (fifo_wvalid & sha_en)
             -----1-----   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T2,T3

 LINE       617
 EXPRESSION (msg_fifo_req & msg_fifo_we & ((~hmac_fifo_wsel)) & msg_allowed)
             ------1-----   -----2-----   ---------3---------   -----4-----
-1--2--3--4-StatusTests
0111CoveredT1,T2,T3
1011Not Covered
1101Not Covered
1110CoveredT1,T2,T3
1111CoveredT1,T2,T3

 LINE       647
 EXPRESSION (msg_write && sha_en && packer_ready)
             ----1----    ---2--    ------3-----
-1--2--3-StatusTests
011CoveredT1,T2,T3
101Not Covered
110UnreachableT9,T6,T10
111CoveredT1,T2,T3

 LINE       667
 EXPRESSION (msg_write & sha_en)
             ----1----   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T2,T3

 LINE       667
 EXPRESSION (fifo_wready & ((~hmac_fifo_wsel)))
             -----1-----   ---------2---------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       771
 SUB-EXPRESSION (reg2hw.alert_test.q & reg2hw.alert_test.qe)
                 ---------1---------   ----------2---------
-1--2-StatusTests
01CoveredT18,T41,T42
10CoveredT1,T2,T3
11CoveredT18,T41,T42

 LINE       800
 EXPRESSION ((reg_hash_start | reg_hash_continue) & ((~sha_en)))
             ------------------1-----------------   -----2-----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT4,T40,T25

 LINE       800
 SUB-EXPRESSION (reg_hash_start | reg_hash_continue)
                 -------1------   --------2--------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT3,T4,T5
10CoveredT1,T2,T3

 LINE       801
 EXPRESSION ((reg_hash_start | reg_hash_continue) & cfg_block)
             ------------------1-----------------   ----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT4,T40,T25

 LINE       801
 SUB-EXPRESSION (reg_hash_start | reg_hash_continue)
                 -------1------   --------2--------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT3,T4,T5
10CoveredT1,T2,T3

 LINE       802
 EXPRESSION (msg_fifo_req & ((~msg_allowed)))
             ------1-----   --------2-------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       807
 EXPRESSION ((digest_size == SHA2_None) | ((key_length == Key_None) && hmac_en) | ((key_length == Key_1024) && (digest_size == SHA2_256) && hmac_en))
             -------------1------------   ------------------2------------------   ---------------------------------3--------------------------------
-1--2--3-StatusTests
000CoveredT1,T2,T3
001CoveredT4,T14,T25
010CoveredT1,T2,T3
100CoveredT1,T2,T3

 LINE       807
 SUB-EXPRESSION (digest_size == SHA2_None)
                -------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       807
 SUB-EXPRESSION ((key_length == Key_None) && hmac_en)
                 ------------1-----------    ---2---
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       807
 SUB-EXPRESSION (key_length == Key_None)
                ------------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       807
 SUB-EXPRESSION ((key_length == Key_1024) && (digest_size == SHA2_256) && hmac_en)
                 ------------1-----------    ------------2------------    ---3---
-1--2--3-StatusTests
011CoveredT1,T3,T4
101CoveredT1,T3,T4
110CoveredT4,T15,T40
111CoveredT4,T14,T25

 LINE       807
 SUB-EXPRESSION (key_length == Key_1024)
                ------------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T4

 LINE       807
 SUB-EXPRESSION (digest_size == SHA2_256)
                ------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T4

 LINE       812
 EXPRESSION ((reg_hash_start || reg_hash_continue) & invalid_config)
             ------------------1------------------   -------2------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       812
 SUB-EXPRESSION (reg_hash_start || reg_hash_continue)
                 -------1------    --------2--------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT3,T4,T5
10CoveredT1,T2,T3

 LINE       831
 EXPRESSION 
 Number  Term
      1  ((~reg2hw.intr_state.hmac_err.q)) & 
      2  (hash_start_sha_disabled | update_seckey_inprocess | hash_start_active | msg_push_not_allowed | invalid_config_atstart))
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       831
 SUB-EXPRESSION (hash_start_sha_disabled | update_seckey_inprocess | hash_start_active | msg_push_not_allowed | invalid_config_atstart)
                 -----------1-----------   -----------2-----------   --------3--------   ----------4---------   -----------5----------
-1--2--3--4--5-StatusTests
00000CoveredT1,T2,T3
00001CoveredT1,T2,T3
00010CoveredT1,T2,T3
00100CoveredT4,T40,T25
01000CoveredT4,T22,T40
10000CoveredT4,T25,T29

 LINE       880
 EXPRESSION (((!reg_fifo_wvalid)) && ((!fifo_rvalid)) && hmac_core_idle && sha_core_idle)
             ----------1---------    --------2-------    -------3------    ------4------
-1--2--3--4-StatusTests
0111Not Covered
1011Not Covered
1101CoveredT1,T2,T3
1110CoveredT1,T2,T3
1111CoveredT1,T2,T3

 LINE       915
 EXPRESSION (hash_process || reg_hash_stop)
             ------1-----    ------2------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT3,T4,T5
10CoveredT1,T2,T3

 LINE       923
 EXPRESSION (hash_process || reg_hash_stop)
             ------1-----    ------2------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT3,T4,T5
10CoveredT1,T2,T3

Toggle Coverage for Module : hmac
TotalCoveredPercent
Totals 30 30 100.00
Total Bits 346 346 100.00
Total Bits 0->1 173 173 100.00
Total Bits 1->0 173 173 100.00

Ports 30 30 100.00
Port Bits 346 346 100.00
Port Bits 0->1 173 173 100.00
Port Bits 1->0 173 173 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T4,T25,T43 Yes T1,T2,T3 INPUT
tl_i.d_ready Yes Yes T1,T2,T4 Yes T1,T2,T3 INPUT
tl_i.a_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.instr_type[3:0] Yes Yes T4,T15,T39 Yes T4,T15,T39 INPUT
tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_address[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_source[7:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_size[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_opcode[2:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_o.a_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_o.d_error Yes Yes T6,T7,T8 Yes T6,T7,T8 OUTPUT
tl_o.d_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_o.d_user.rsp_intg[5:0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_o.d_user.rsp_intg[6] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_o.d_sink Unreachable Unreachable Unreachable OUTPUT
tl_o.d_source[7:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_o.d_size[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_opcode[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_i[0].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[0].ack_p Yes Yes T18,T41,T42 Yes T18,T41,T42 INPUT
alert_rx_i[0].ping_n Unreachable Unreachable Unreachable INPUT
alert_rx_i[0].ping_p Unreachable Unreachable Unreachable INPUT
alert_tx_o[0].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[0].alert_p Yes Yes T18,T41,T42 Yes T18,T41,T42 OUTPUT
intr_hmac_done_o Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
intr_fifo_empty_o Yes Yes T4,T17,T25 Yes T4,T17,T25 OUTPUT
intr_hmac_err_o Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
idle_o[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT

*Tests covering at least one bit in the range

FSM Coverage for Module : hmac
Summary for FSM :: done_state_q
TotalCoveredPercent
States 4 4 100.00 (Not included in score)
Transitions 5 5 100.00
Sequences 0 0

State, Transition and Sequence Details for FSM :: done_state_q
statesLine No.CoveredTests
DoneAwaitCmd 167 Covered T1,T2,T3
DoneAwaitHashComplete 176 Covered T3,T4,T5
DoneAwaitHashDone 157 Covered T1,T2,T3
DoneAwaitMessageComplete 160 Covered T3,T4,T5


transitionsLine No.CoveredTests
DoneAwaitCmd->DoneAwaitHashDone 157 Covered T1,T2,T3
DoneAwaitCmd->DoneAwaitMessageComplete 160 Covered T3,T4,T5
DoneAwaitHashComplete->DoneAwaitCmd 183 Covered T3,T4,T5
DoneAwaitHashDone->DoneAwaitCmd 167 Covered T1,T2,T3
DoneAwaitMessageComplete->DoneAwaitHashComplete 176 Covered T3,T4,T5



Branch Coverage for Module : hmac
Line No.TotalCoveredPercent
Branches 93 90 96.77
TERNARY 301 2 2 100.00
TERNARY 462 4 4 100.00
TERNARY 472 2 2 100.00
TERNARY 537 2 2 100.00
CASE 153 10 8 80.00
IF 192 2 2 100.00
IF 205 3 3 100.00
IF 219 2 2 100.00
IF 240 6 6 100.00
IF 256 3 3 100.00
CASE 289 4 4 100.00
IF 304 2 2 100.00
CASE 312 6 6 100.00
IF 355 4 4 100.00
IF 365 3 3 100.00
IF 404 4 4 100.00
IF 475 2 2 100.00
IF 545 4 3 75.00
IF 630 2 2 100.00
IF 636 5 5 100.00
IF 645 3 3 100.00
IF 816 2 2 100.00
CASE 839 6 6 100.00
IF 886 2 2 100.00
IF 914 4 4 100.00
IF 921 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_hmac_0.1/rtl/hmac.sv' or '../src/lowrisc_ip_hmac_0.1/rtl/hmac.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 301 (hash_start_or_continue) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 462 ((((reg_hash_start || reg_hash_continue) || reg_hash_process) || reg_hash_stop)) ? -2-: 462 (fifo_empty_negedge) ? -3-: 462 (fifo_full_posedge) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T1,T2,T3
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 472 (fifo_empty_gate) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T17,T25,T9


LineNo. Expression -1-: 537 ((hmac_fifo_wsel && fifo_wready)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 153 case (done_state_q) -2-: 155 if (sha_hash_process) -3-: 158 if (reg_hash_stop) -4-: 165 if (reg_hash_done) -5-: 172 if (digest_on_blk) -6-: 181 if ((!hash_running))

Branches:
-1--2--3--4--5--6-StatusTests
DoneAwaitCmd 1 - - - - Covered T1,T2,T3
DoneAwaitCmd 0 1 - - - Covered T3,T4,T5
DoneAwaitCmd 0 0 - - - Covered T1,T2,T3
DoneAwaitHashDone - - 1 - - Covered T1,T2,T3
DoneAwaitHashDone - - 0 - - Covered T1,T2,T3
DoneAwaitMessageComplete - - - 1 - Covered T3,T4,T5
DoneAwaitMessageComplete - - - 0 - Covered T3,T4,T5
DoneAwaitHashComplete - - - - 1 Covered T3,T4,T5
DoneAwaitHashComplete - - - - 0 Not Covered
default - - - - - Not Covered


LineNo. Expression -1-: 192 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 205 if (wipe_secret) -2-: 207 if ((!cfg_block))

Branches:
-1--2-StatusTests
1 - Covered T1,T4,T25
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 219 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 240 if ((digest_size == SHA2_256)) -2-: 244 if (((digest_size == SHA2_384) || (digest_size == SHA2_512))) -3-: 246 (reg2hw.digest[(2 * i)].qe) ? -4-: 249 (reg2hw.digest[((2 * i) + 1)].qe) ?

Branches:
-1--2--3--4-StatusTests
1 - - - Covered T1,T3,T4
0 1 1 - Covered T4,T5,T15
0 1 0 - Covered T1,T2,T3
0 1 - 1 Covered T4,T5,T15
0 1 - 0 Covered T1,T2,T3
0 0 - - Covered T1,T2,T3


LineNo. Expression -1-: 256 if ((digest_size_started_q == SHA2_256)) -2-: 262 if (((digest_size_started_q == SHA2_384) || (digest_size_started_q == SHA2_512)))

Branches:
-1--2-StatusTests
1 - Covered T1,T3,T4
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 289 case (digest_size_supplied)

Branches:
-1-StatusTests
SHA2_256 Covered T1,T3,T4
SHA2_384 Covered T1,T2,T3
SHA2_512 Covered T1,T2,T3
default Covered T1,T2,T3


LineNo. Expression -1-: 304 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 312 case (key_length_supplied)

Branches:
-1-StatusTests
Key_128 Covered T1,T3,T4
Key_256 Covered T1,T2,T3
Key_384 Covered T1,T3,T4
Key_512 Covered T1,T2,T3
Key_1024 Covered T1,T3,T4
default Covered T1,T2,T3


LineNo. Expression -1-: 355 if ((!rst_ni)) -2-: 357 if (hash_start_or_continue) -3-: 359 if ((reg_hash_done || reg_hash_stop))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T1,T2,T3
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 365 if ((!rst_ni)) -2-: 397 if (((!cfg_block) && reg2hw.cfg.hmac_en.qe))

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 404 if ((!rst_ni)) -2-: 406 if (hash_start_or_continue) -3-: 408 if (packer_flush_done)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T1,T2,T3
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 475 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 545 if (hmac_fifo_wsel) -2-: 547 if ((digest_size == SHA2_256)) -3-: 550 if (((digest_size == SHA2_384) || (digest_size == SHA2_512)))

Branches:
-1--2--3-StatusTests
1 1 - Covered T1,T3,T4
1 0 1 Covered T1,T2,T3
1 0 0 Not Covered
0 - - Covered T1,T2,T3


LineNo. Expression -1-: 630 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 636 if ((!cfg_block)) -2-: 637 if (reg2hw.msg_length_lower.qe) -3-: 640 if (reg2hw.msg_length_upper.qe)

Branches:
-1--2--3-StatusTests
1 1 - Covered T3,T4,T5
1 0 - Covered T1,T2,T3
1 - 1 Covered T3,T4,T5
1 - 0 Covered T1,T2,T3
0 - - Covered T1,T2,T3


LineNo. Expression -1-: 645 if (hash_start) -2-: 647 if (((msg_write && sha_en) && packer_ready))

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 816 if (cfg_block)

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 839 case (1'b1)

Branches:
-1-StatusTests
invalid_config_atstart Covered T1,T2,T3
hash_start_sha_disabled Covered T4,T25,T29
hash_start_active Covered T4,T40,T25
msg_push_not_allowed Covered T1,T2,T3
update_seckey_inprocess Covered T4,T22,T40
default Covered T1,T2,T3


LineNo. Expression -1-: 886 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 914 if ((!rst_ni)) -2-: 915 if ((hash_process || reg_hash_stop)) -3-: 916 if (reg_hash_done)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T1,T2,T3
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 921 if ((!rst_ni)) -2-: 922 if (hash_start_or_continue) -3-: 923 if ((hash_process || reg_hash_stop))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T1,T2,T3
0 0 0 Covered T1,T2,T3


Assert Coverage for Module : hmac
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 13 13 100.00 13 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 13 13 100.00 13 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AlertKnownO_A 505207750 505141086 0 0
FpvSecCmRegWeOnehotCheck_A 505207750 130 0 0
IntrFifoEmptyOKnown 505207750 505141086 0 0
IntrHmacDoneOKnown 505207750 505141086 0 0
TlOAReadyKnown 505207750 505141086 0 0
TlODValidKnown 505207750 505141086 0 0
ValidHashProcessAssert 505207750 19215 0 0
ValidHmacEnConditionAssert 505207750 12293 0 0
ValidWriteAssert 505207750 19986379 0 0
gen_assert_wmask_bytealign[0].unnamed$$_0 505207750 19986379 0 0
gen_assert_wmask_bytealign[1].unnamed$$_0 505207750 19986379 0 0
gen_assert_wmask_bytealign[2].unnamed$$_0 505207750 19986379 0 0
gen_assert_wmask_bytealign[3].unnamed$$_0 505207750 19986379 0 0


AlertKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 505207750 505141086 0 0
T1 632330 632248 0 0
T2 21045 20978 0 0
T3 333149 333075 0 0
T4 653077 652971 0 0
T5 175511 175432 0 0
T14 143242 143157 0 0
T15 296555 296460 0 0
T16 228356 228280 0 0
T17 53663 53601 0 0
T18 1102 1039 0 0

FpvSecCmRegWeOnehotCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 505207750 130 0 0
T36 348356 0 0 0
T44 8252 30 0 0
T45 6393 20 0 0
T46 0 20 0 0
T47 0 30 0 0
T48 0 30 0 0
T49 1086 0 0 0
T50 44379 0 0 0
T51 295142 0 0 0
T52 210870 0 0 0
T53 11140 0 0 0
T54 559908 0 0 0
T55 688643 0 0 0

IntrFifoEmptyOKnown
NameAttemptsReal SuccessesFailuresIncomplete
Total 505207750 505141086 0 0
T1 632330 632248 0 0
T2 21045 20978 0 0
T3 333149 333075 0 0
T4 653077 652971 0 0
T5 175511 175432 0 0
T14 143242 143157 0 0
T15 296555 296460 0 0
T16 228356 228280 0 0
T17 53663 53601 0 0
T18 1102 1039 0 0

IntrHmacDoneOKnown
NameAttemptsReal SuccessesFailuresIncomplete
Total 505207750 505141086 0 0
T1 632330 632248 0 0
T2 21045 20978 0 0
T3 333149 333075 0 0
T4 653077 652971 0 0
T5 175511 175432 0 0
T14 143242 143157 0 0
T15 296555 296460 0 0
T16 228356 228280 0 0
T17 53663 53601 0 0
T18 1102 1039 0 0

TlOAReadyKnown
NameAttemptsReal SuccessesFailuresIncomplete
Total 505207750 505141086 0 0
T1 632330 632248 0 0
T2 21045 20978 0 0
T3 333149 333075 0 0
T4 653077 652971 0 0
T5 175511 175432 0 0
T14 143242 143157 0 0
T15 296555 296460 0 0
T16 228356 228280 0 0
T17 53663 53601 0 0
T18 1102 1039 0 0

TlODValidKnown
NameAttemptsReal SuccessesFailuresIncomplete
Total 505207750 505141086 0 0
T1 632330 632248 0 0
T2 21045 20978 0 0
T3 333149 333075 0 0
T4 653077 652971 0 0
T5 175511 175432 0 0
T14 143242 143157 0 0
T15 296555 296460 0 0
T16 228356 228280 0 0
T17 53663 53601 0 0
T18 1102 1039 0 0

ValidHashProcessAssert
NameAttemptsReal SuccessesFailuresIncomplete
Total 505207750 19215 0 0
T1 632330 21 0 0
T2 21045 2 0 0
T3 333149 10 0 0
T4 653077 182 0 0
T5 175511 19 0 0
T14 143242 14 0 0
T15 296555 21 0 0
T16 228356 17 0 0
T17 53663 6 0 0
T18 1102 0 0 0
T22 0 194 0 0

ValidHmacEnConditionAssert
NameAttemptsReal SuccessesFailuresIncomplete
Total 505207750 12293 0 0
T1 632330 19 0 0
T2 21045 3 0 0
T3 333149 1 0 0
T4 653077 238 0 0
T5 175511 6 0 0
T14 143242 15 0 0
T15 296555 15 0 0
T16 228356 11 0 0
T17 53663 11 0 0
T18 1102 0 0 0
T56 0 1 0 0

ValidWriteAssert
NameAttemptsReal SuccessesFailuresIncomplete
Total 505207750 19986379 0 0
T1 632330 21571 0 0
T2 21045 354 0 0
T3 333149 40667 0 0
T4 653077 241593 0 0
T5 175511 20662 0 0
T14 143242 16780 0 0
T15 296555 22850 0 0
T16 228356 10396 0 0
T17 53663 13073 0 0
T18 1102 0 0 0
T22 0 74244 0 0

gen_assert_wmask_bytealign[0].unnamed$$_0
NameAttemptsReal SuccessesFailuresIncomplete
Total 505207750 19986379 0 0
T1 632330 21571 0 0
T2 21045 354 0 0
T3 333149 40667 0 0
T4 653077 241593 0 0
T5 175511 20662 0 0
T14 143242 16780 0 0
T15 296555 22850 0 0
T16 228356 10396 0 0
T17 53663 13073 0 0
T18 1102 0 0 0
T22 0 74244 0 0

gen_assert_wmask_bytealign[1].unnamed$$_0
NameAttemptsReal SuccessesFailuresIncomplete
Total 505207750 19986379 0 0
T1 632330 21571 0 0
T2 21045 354 0 0
T3 333149 40667 0 0
T4 653077 241593 0 0
T5 175511 20662 0 0
T14 143242 16780 0 0
T15 296555 22850 0 0
T16 228356 10396 0 0
T17 53663 13073 0 0
T18 1102 0 0 0
T22 0 74244 0 0

gen_assert_wmask_bytealign[2].unnamed$$_0
NameAttemptsReal SuccessesFailuresIncomplete
Total 505207750 19986379 0 0
T1 632330 21571 0 0
T2 21045 354 0 0
T3 333149 40667 0 0
T4 653077 241593 0 0
T5 175511 20662 0 0
T14 143242 16780 0 0
T15 296555 22850 0 0
T16 228356 10396 0 0
T17 53663 13073 0 0
T18 1102 0 0 0
T22 0 74244 0 0

gen_assert_wmask_bytealign[3].unnamed$$_0
NameAttemptsReal SuccessesFailuresIncomplete
Total 505207750 19986379 0 0
T1 632330 21571 0 0
T2 21045 354 0 0
T3 333149 40667 0 0
T4 653077 241593 0 0
T5 175511 20662 0 0
T14 143242 16780 0 0
T15 296555 22850 0 0
T16 228356 10396 0 0
T17 53663 13073 0 0
T18 1102 0 0 0
T22 0 74244 0 0

Line Coverage for Instance : tb.dut
Line No.TotalCoveredPercent
TOTAL198198100.00
CONT_ASSIGN13511100.00
CONT_ASSIGN13611100.00
CONT_ASSIGN13711100.00
CONT_ASSIGN13811100.00
ALWAYS1501515100.00
ALWAYS19233100.00
CONT_ASSIGN19911100.00
CONT_ASSIGN20011100.00
ALWAYS20477100.00
ALWAYS21933100.00
ALWAYS2311919100.00
CONT_ASSIGN27711100.00
CONT_ASSIGN28211100.00
CONT_ASSIGN28311100.00
CONT_ASSIGN28511100.00
ALWAYS28755100.00
CONT_ASSIGN30111100.00
ALWAYS30433100.00
CONT_ASSIGN30811100.00
ALWAYS31077100.00
CONT_ASSIGN32511100.00
CONT_ASSIGN32611100.00
CONT_ASSIGN32711100.00
CONT_ASSIGN32911100.00
CONT_ASSIGN33011100.00
CONT_ASSIGN33111100.00
CONT_ASSIGN33211100.00
CONT_ASSIGN33311100.00
CONT_ASSIGN33411100.00
CONT_ASSIGN33511100.00
CONT_ASSIGN33711100.00
CONT_ASSIGN33811100.00
CONT_ASSIGN33911100.00
CONT_ASSIGN34011100.00
CONT_ASSIGN34311100.00
CONT_ASSIGN34411100.00
CONT_ASSIGN34911100.00
CONT_ASSIGN35011100.00
CONT_ASSIGN35111100.00
CONT_ASSIGN35211100.00
ALWAYS35566100.00
ALWAYS36544100.00
ALWAYS40466100.00
CONT_ASSIGN45411100.00
CONT_ASSIGN45511100.00
CONT_ASSIGN46211100.00
CONT_ASSIGN47011100.00
CONT_ASSIGN47211100.00
ALWAYS47577100.00
CONT_ASSIGN51811100.00
CONT_ASSIGN52111100.00
CONT_ASSIGN52711100.00
CONT_ASSIGN53211100.00
CONT_ASSIGN53311100.00
CONT_ASSIGN53511100.00
CONT_ASSIGN53611100.00
CONT_ASSIGN53711100.00
ALWAYS54299100.00
CONT_ASSIGN61711100.00
ALWAYS62233100.00
ALWAYS63033100.00
ALWAYS6351010100.00
CONT_ASSIGN65211100.00
CONT_ASSIGN65311100.00
CONT_ASSIGN66011100.00
CONT_ASSIGN66111100.00
CONT_ASSIGN77111100.00
CONT_ASSIGN80011100.00
CONT_ASSIGN80111100.00
CONT_ASSIGN80211100.00
CONT_ASSIGN80711100.00
CONT_ASSIGN81211100.00
ALWAYS81566100.00
CONT_ASSIGN83111100.00
ALWAYS83777100.00
CONT_ASSIGN88011100.00
CONT_ASSIGN88411100.00
ALWAYS88633100.00
CONT_ASSIGN89211100.00
ALWAYS91466100.00
ALWAYS92166100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_hmac_0.1/rtl/hmac.sv' or '../src/lowrisc_ip_hmac_0.1/rtl/hmac.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
135 1 1
136 1 1
137 1 1
138 1 1
150 1 1
151 1 1
153 1 1
155 1 1
157 1 1
158 1 1
160 1 1
MISSING_ELSE
165 1 1
166 1 1
167 1 1
MISSING_ELSE
172 1 1
176 1 1
MISSING_ELSE
181 1 1
182 1 1
183 1 1
==> MISSING_ELSE
Exclude Annotation: VC_COV_UNR
192 1 1
193 1 1
195 1 1
199 1 1
200 1 1
204 1 1
205 1 1
206 1 1
207 1 1
209 1 1
210 1 1
212 1 1
MISSING_ELSE
MISSING_ELSE
219 2 2
220 1 1
231 1 1
232 1 1
234 1 1
236 1 1
240 1 1
242 1 1
243 1 1
244 1 1
246 1 1
249 1 1
252 1 1
MISSING_ELSE
256 1 1
257 1 1
261 1 1
262 1 1
266 1 1
267 1 1
270 1 1
271 1 1
277 1 1
282 1 1
283 1 1
285 1 1
287 1 1
289 1 1
290 1 1
291 1 1
292 1 1
301 1 1
304 2 2
305 1 1
308 1 1
310 1 1
312 1 1
313 1 1
314 1 1
315 1 1
316 1 1
317 1 1
325 1 1
326 1 1
327 1 1
329 1 1
330 1 1
331 1 1
332 1 1
333 1 1
334 1 1
335 1 1
337 1 1
338 1 1
339 1 1
340 1 1
343 1 1
344 1 1
349 1 1
350 1 1
351 1 1
352 1 1
355 1 1
356 1 1
357 1 1
358 1 1
359 1 1
360 1 1
MISSING_ELSE
365 1 1
366 1 1
397 1 1
398 1 1
MISSING_ELSE
404 1 1
405 1 1
406 1 1
407 1 1
408 1 1
409 1 1
MISSING_ELSE
454 1 1
455 1 1
462 1 1
470 1 1
472 1 1
475 1 1
476 1 1
477 1 1
478 1 1
480 1 1
481 1 1
482 1 1
518 1 1
521 1 1
527 1 1
532 1 1
533 1 1
535 1 1
536 1 1
537 1 1
542 1 1
543 1 1
545 1 1
546 1 1
547 1 1
549 1 1
550 1 1
552 1 1
553 1 1
==> MISSING_ELSE
MISSING_ELSE
617 1 1
622 1 1
623 1 1
624 1 1
630 2 2
631 1 1
635 1 1
636 1 1
637 1 1
638 1 1
MISSING_ELSE
640 1 1
641 1 1
MISSING_ELSE
MISSING_ELSE
645 1 1
646 1 1
647 1 1
648 1 1
MISSING_ELSE
652 1 1
653 1 1
660 1 1
661 1 1
771 1 1
800 1 1
801 1 1
802 1 1
807 1 1
812 1 1
815 1 1
816 1 1
817 1 1
818 1 1
819 1 1
MISSING_ELSE
823 1 1
831 1 1
837 1 1
839 1 1
842 1 1
846 1 1
850 1 1
854 1 1
858 1 1
880 1 1
884 1 1
886 1 1
887 1 1
889 1 1
892 1 1
914 2 2
915 2 2
916 2 2
MISSING_ELSE
921 2 2
922 2 2
923 2 2
MISSING_ELSE


Cond Coverage for Instance : tb.dut
TotalCoveredPercent
Conditions18016893.33
Logical18016893.33
Non-Logical00
Event00

 LINE       240
 EXPRESSION (digest_size == SHA2_256)
            ------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T4

 LINE       244
 EXPRESSION ((digest_size == SHA2_384) || (digest_size == SHA2_512))
             ------------1------------    ------------2------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3

 LINE       244
 SUB-EXPRESSION (digest_size == SHA2_384)
                ------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       244
 SUB-EXPRESSION (digest_size == SHA2_512)
                ------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       246
 EXPRESSION (reg2hw.digest[(2 * i)].qe ? prim_sha2_pkg::conv_endian32(reg2hw.digest[(2 * i)].q, digest_swap) : digest[i][63:32])
             ------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT4,T5,T15

 LINE       249
 EXPRESSION (reg2hw.digest[((2 * i) + 1)].qe ? prim_sha2_pkg::conv_endian32(reg2hw.digest[((2 * i) + 1)].q, digest_swap) : digest[i][31:0])
             ---------------1---------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT4,T5,T15

 LINE       252
 EXPRESSION (reg2hw.digest[(2 * i)].qe | reg2hw.digest[((2 * i) + 1)].qe)
             ------------1------------   ---------------2---------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT4,T5,T15
10CoveredT4,T5,T15

 LINE       256
 EXPRESSION (digest_size_started_q == SHA2_256)
            -----------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T4

 LINE       262
 EXPRESSION ((digest_size_started_q == SHA2_384) || (digest_size_started_q == SHA2_512))
             -----------------1-----------------    -----------------2-----------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3

 LINE       262
 SUB-EXPRESSION (digest_size_started_q == SHA2_384)
                -----------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       262
 SUB-EXPRESSION (digest_size_started_q == SHA2_512)
                -----------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       301
 EXPRESSION (hash_start_or_continue ? digest_size : digest_size_started_q)
             -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       337
 EXPRESSION (reg2hw.cmd.hash_start.qe & reg2hw.cmd.hash_start.q)
             ------------1-----------   -----------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       338
 EXPRESSION (reg2hw.cmd.hash_stop.qe & reg2hw.cmd.hash_stop.q)
             -----------1-----------   -----------2----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT3,T4,T5

 LINE       339
 EXPRESSION (reg2hw.cmd.hash_continue.qe & reg2hw.cmd.hash_continue.q)
             -------------1-------------   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT3,T4,T5

 LINE       340
 EXPRESSION (reg2hw.cmd.hash_process.qe & reg2hw.cmd.hash_process.q)
             -------------1------------   ------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       349
 EXPRESSION (reg_hash_start & sha_en & ((~cfg_block)) & ((~invalid_config)))
             -------1------   ---2--   -------3------   ---------4---------
-1--2--3--4-StatusTests
0111CoveredT1,T2,T3
1011CoveredT4,T25,T29
1101CoveredT4,T40,T25
1110CoveredT1,T2,T3
1111CoveredT1,T2,T3

 LINE       350
 EXPRESSION (reg_hash_continue & sha_en & ((~cfg_block)) & ((~invalid_config)))
             --------1--------   ---2--   -------3------   ---------4---------
-1--2--3--4-StatusTests
0111CoveredT1,T2,T3
1011Not Covered
1101Not Covered
1110Not Covered
1111CoveredT3,T4,T5

 LINE       351
 EXPRESSION (reg_hash_process & sha_en & cfg_block & ((~invalid_config)))
             --------1-------   ---2--   ----3----   ---------4---------
-1--2--3--4-StatusTestsExclude Annotation
0111CoveredT1,T2,T3
1011Excluded VC_COV_UNR
1101Not Covered
1110Excluded VC_COV_UNR
1111CoveredT1,T2,T3

 LINE       352
 EXPRESSION (hash_start | hash_continue)
             -----1----   ------2------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT3,T4,T5
10CoveredT1,T2,T3

 LINE       359
 EXPRESSION (reg_hash_done || reg_hash_stop)
             ------1------    ------2------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT3,T4,T5
10CoveredT1,T2,T3

 LINE       397
 EXPRESSION (((!cfg_block)) && reg2hw.cfg.hmac_en.qe)
             -------1------    ----------2----------
-1--2-StatusTests
01CoveredT4,T22,T40
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       454
 EXPRESSION (fifo_empty_q & ((~fifo_empty)))
             ------1-----   -------2-------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       455
 EXPRESSION (((~fifo_full_q)) & fifo_full)
             --------1-------   ----2----
-1--2-StatusTests
01CoveredT17,T25,T9
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       462
 EXPRESSION 
 Number  Term
      1  (reg_hash_start || reg_hash_continue || reg_hash_process || reg_hash_stop) ? 1'b0 : (fifo_empty_negedge ? 1'b0 : (fifo_full_posedge ? 1'b1 : fifo_full_seen_q)))
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       462
 SUB-EXPRESSION (reg_hash_start || reg_hash_continue || reg_hash_process || reg_hash_stop)
                 -------1------    --------2--------    --------3-------    ------4------
-1--2--3--4-StatusTests
0000CoveredT1,T2,T3
0001CoveredT3,T4,T5
0010CoveredT1,T2,T3
0100CoveredT3,T4,T5
1000CoveredT1,T2,T3

 LINE       462
 SUB-EXPRESSION (fifo_empty_negedge ? 1'b0 : (fifo_full_posedge ? 1'b1 : fifo_full_seen_q))
                 ---------1--------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       462
 SUB-EXPRESSION (fifo_full_posedge ? 1'b1 : fifo_full_seen_q)
                 --------1--------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       470
 EXPRESSION (((~msg_allowed)) || ((~fifo_full_seen_q)))
             --------1-------    ----------2----------
-1--2-StatusTests
00CoveredT17,T25,T9
01CoveredT1,T2,T3
10CoveredT1,T2,T3

 LINE       472
 EXPRESSION (fifo_empty_gate ? 1'b0 : fifo_empty)
             -------1-------
-1-StatusTests
0CoveredT17,T25,T9
1CoveredT1,T2,T3

 LINE       518
 EXPRESSION (msg_fifo_req & ((~msg_fifo_we)))
             ------1-----   --------2-------
-1--2-StatusTestsExclude Annotation
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11Excluded VC_COV_UNR

 LINE       521
 EXPRESSION (msg_fifo_req & ((~hmac_fifo_wsel)) & packer_ready)
             ------1-----   ---------2---------   ------3-----
-1--2--3-StatusTests
011CoveredT1,T2,T3
101Not Covered
110UnreachableT9,T6,T10
111CoveredT1,T2,T3

 LINE       537
 EXPRESSION ((hmac_fifo_wsel && fifo_wready) ? hmac_fifo_wvalid : reg_fifo_wvalid)
             ---------------1---------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       537
 SUB-EXPRESSION (hmac_fifo_wsel && fifo_wready)
                 -------1------    -----2-----
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T2,T3

 LINE       547
 EXPRESSION (digest_size == SHA2_256)
            ------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T4

 LINE       550
 EXPRESSION ((digest_size == SHA2_384) || (digest_size == SHA2_512))
             ------------1------------    ------------2------------
-1--2-StatusTests
00Not Covered
01CoveredT1,T3,T4
10CoveredT1,T2,T3

 LINE       550
 SUB-EXPRESSION (digest_size == SHA2_384)
                ------------1------------
-1-StatusTests
0CoveredT1,T3,T4
1CoveredT1,T2,T3

 LINE       550
 SUB-EXPRESSION (digest_size == SHA2_512)
                ------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T4

 LINE       564
 EXPRESSION (fifo_wvalid & sha_en)
             -----1-----   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T2,T3

 LINE       617
 EXPRESSION (msg_fifo_req & msg_fifo_we & ((~hmac_fifo_wsel)) & msg_allowed)
             ------1-----   -----2-----   ---------3---------   -----4-----
-1--2--3--4-StatusTestsExclude Annotation
0111CoveredT1,T2,T3
1011Excluded VC_COV_UNR
1101Not Covered
1110CoveredT1,T2,T3
1111CoveredT1,T2,T3

 LINE       647
 EXPRESSION (msg_write && sha_en && packer_ready)
             ----1----    ---2--    ------3-----
-1--2--3-StatusTests
011CoveredT1,T2,T3
101Not Covered
110UnreachableT9,T6,T10
111CoveredT1,T2,T3

 LINE       667
 EXPRESSION (msg_write & sha_en)
             ----1----   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T2,T3

 LINE       667
 EXPRESSION (fifo_wready & ((~hmac_fifo_wsel)))
             -----1-----   ---------2---------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       771
 SUB-EXPRESSION (reg2hw.alert_test.q & reg2hw.alert_test.qe)
                 ---------1---------   ----------2---------
-1--2-StatusTests
01CoveredT18,T41,T42
10CoveredT1,T2,T3
11CoveredT18,T41,T42

 LINE       800
 EXPRESSION ((reg_hash_start | reg_hash_continue) & ((~sha_en)))
             ------------------1-----------------   -----2-----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT4,T40,T25

 LINE       800
 SUB-EXPRESSION (reg_hash_start | reg_hash_continue)
                 -------1------   --------2--------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT3,T4,T5
10CoveredT1,T2,T3

 LINE       801
 EXPRESSION ((reg_hash_start | reg_hash_continue) & cfg_block)
             ------------------1-----------------   ----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT4,T40,T25

 LINE       801
 SUB-EXPRESSION (reg_hash_start | reg_hash_continue)
                 -------1------   --------2--------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT3,T4,T5
10CoveredT1,T2,T3

 LINE       802
 EXPRESSION (msg_fifo_req & ((~msg_allowed)))
             ------1-----   --------2-------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       807
 EXPRESSION ((digest_size == SHA2_None) | ((key_length == Key_None) && hmac_en) | ((key_length == Key_1024) && (digest_size == SHA2_256) && hmac_en))
             -------------1------------   ------------------2------------------   ---------------------------------3--------------------------------
-1--2--3-StatusTests
000CoveredT1,T2,T3
001CoveredT4,T14,T25
010CoveredT1,T2,T3
100CoveredT1,T2,T3

 LINE       807
 SUB-EXPRESSION (digest_size == SHA2_None)
                -------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       807
 SUB-EXPRESSION ((key_length == Key_None) && hmac_en)
                 ------------1-----------    ---2---
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       807
 SUB-EXPRESSION (key_length == Key_None)
                ------------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       807
 SUB-EXPRESSION ((key_length == Key_1024) && (digest_size == SHA2_256) && hmac_en)
                 ------------1-----------    ------------2------------    ---3---
-1--2--3-StatusTests
011CoveredT1,T3,T4
101CoveredT1,T3,T4
110CoveredT4,T15,T40
111CoveredT4,T14,T25

 LINE       807
 SUB-EXPRESSION (key_length == Key_1024)
                ------------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T4

 LINE       807
 SUB-EXPRESSION (digest_size == SHA2_256)
                ------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T4

 LINE       812
 EXPRESSION ((reg_hash_start || reg_hash_continue) & invalid_config)
             ------------------1------------------   -------2------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       812
 SUB-EXPRESSION (reg_hash_start || reg_hash_continue)
                 -------1------    --------2--------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT3,T4,T5
10CoveredT1,T2,T3

 LINE       831
 EXPRESSION 
 Number  Term
      1  ((~reg2hw.intr_state.hmac_err.q)) & 
      2  (hash_start_sha_disabled | update_seckey_inprocess | hash_start_active | msg_push_not_allowed | invalid_config_atstart))
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       831
 SUB-EXPRESSION (hash_start_sha_disabled | update_seckey_inprocess | hash_start_active | msg_push_not_allowed | invalid_config_atstart)
                 -----------1-----------   -----------2-----------   --------3--------   ----------4---------   -----------5----------
-1--2--3--4--5-StatusTests
00000CoveredT1,T2,T3
00001CoveredT1,T2,T3
00010CoveredT1,T2,T3
00100CoveredT4,T40,T25
01000CoveredT4,T22,T40
10000CoveredT4,T25,T29

 LINE       880
 EXPRESSION (((!reg_fifo_wvalid)) && ((!fifo_rvalid)) && hmac_core_idle && sha_core_idle)
             ----------1---------    --------2-------    -------3------    ------4------
-1--2--3--4-StatusTestsExclude Annotation
0111Excluded VC_COV_UNR
1011Not Covered
1101CoveredT1,T2,T3
1110CoveredT1,T2,T3
1111CoveredT1,T2,T3

 LINE       915
 EXPRESSION (hash_process || reg_hash_stop)
             ------1-----    ------2------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT3,T4,T5
10CoveredT1,T2,T3

 LINE       923
 EXPRESSION (hash_process || reg_hash_stop)
             ------1-----    ------2------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT3,T4,T5
10CoveredT1,T2,T3

Toggle Coverage for Instance : tb.dut
TotalCoveredPercent
Totals 30 30 100.00
Total Bits 346 346 100.00
Total Bits 0->1 173 173 100.00
Total Bits 1->0 173 173 100.00

Ports 30 30 100.00
Port Bits 346 346 100.00
Port Bits 0->1 173 173 100.00
Port Bits 1->0 173 173 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T4,T25,T43 Yes T1,T2,T3 INPUT
tl_i.d_ready Yes Yes T1,T2,T4 Yes T1,T2,T3 INPUT
tl_i.a_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.instr_type[3:0] Yes Yes T4,T15,T39 Yes T4,T15,T39 INPUT
tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_address[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_source[7:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_size[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_opcode[2:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_o.a_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_o.d_error Yes Yes T6,T7,T8 Yes T6,T7,T8 OUTPUT
tl_o.d_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_o.d_user.rsp_intg[5:0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_o.d_user.rsp_intg[6] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_o.d_sink Unreachable Unreachable Unreachable OUTPUT
tl_o.d_source[7:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_o.d_size[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_opcode[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_i[0].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[0].ack_p Yes Yes T18,T41,T42 Yes T18,T41,T42 INPUT
alert_rx_i[0].ping_n Unreachable Unreachable Unreachable INPUT
alert_rx_i[0].ping_p Unreachable Unreachable Unreachable INPUT
alert_tx_o[0].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[0].alert_p Yes Yes T18,T41,T42 Yes T18,T41,T42 OUTPUT
intr_hmac_done_o Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
intr_fifo_empty_o Yes Yes T4,T17,T25 Yes T4,T17,T25 OUTPUT
intr_hmac_err_o Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
idle_o[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT

*Tests covering at least one bit in the range

FSM Coverage for Instance : tb.dut
Summary for FSM :: done_state_q
TotalCoveredPercent
States 4 4 100.00 (Not included in score)
Transitions 5 5 100.00
Sequences 0 0

State, Transition and Sequence Details for FSM :: done_state_q
statesLine No.CoveredTests
DoneAwaitCmd 167 Covered T1,T2,T3
DoneAwaitHashComplete 176 Covered T3,T4,T5
DoneAwaitHashDone 157 Covered T1,T2,T3
DoneAwaitMessageComplete 160 Covered T3,T4,T5


transitionsLine No.CoveredTests
DoneAwaitCmd->DoneAwaitHashDone 157 Covered T1,T2,T3
DoneAwaitCmd->DoneAwaitMessageComplete 160 Covered T3,T4,T5
DoneAwaitHashComplete->DoneAwaitCmd 183 Covered T3,T4,T5
DoneAwaitHashDone->DoneAwaitCmd 167 Covered T1,T2,T3
DoneAwaitMessageComplete->DoneAwaitHashComplete 176 Covered T3,T4,T5



Branch Coverage for Instance : tb.dut
Line No.TotalCoveredPercent
Branches 91 90 98.90
TERNARY 301 2 2 100.00
TERNARY 462 4 4 100.00
TERNARY 472 2 2 100.00
TERNARY 537 2 2 100.00
CASE 153 8 8 100.00
IF 192 2 2 100.00
IF 205 3 3 100.00
IF 219 2 2 100.00
IF 240 6 6 100.00
IF 256 3 3 100.00
CASE 289 4 4 100.00
IF 304 2 2 100.00
CASE 312 6 6 100.00
IF 355 4 4 100.00
IF 365 3 3 100.00
IF 404 4 4 100.00
IF 475 2 2 100.00
IF 545 4 3 75.00
IF 630 2 2 100.00
IF 636 5 5 100.00
IF 645 3 3 100.00
IF 816 2 2 100.00
CASE 839 6 6 100.00
IF 886 2 2 100.00
IF 914 4 4 100.00
IF 921 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_hmac_0.1/rtl/hmac.sv' or '../src/lowrisc_ip_hmac_0.1/rtl/hmac.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 301 (hash_start_or_continue) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 462 ((((reg_hash_start || reg_hash_continue) || reg_hash_process) || reg_hash_stop)) ? -2-: 462 (fifo_empty_negedge) ? -3-: 462 (fifo_full_posedge) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T1,T2,T3
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 472 (fifo_empty_gate) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T17,T25,T9


LineNo. Expression -1-: 537 ((hmac_fifo_wsel && fifo_wready)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 153 case (done_state_q) -2-: 155 if (sha_hash_process) -3-: 158 if (reg_hash_stop) -4-: 165 if (reg_hash_done) -5-: 172 if (digest_on_blk) -6-: 181 if ((!hash_running))

Branches:
-1--2--3--4--5--6-StatusTestsExclude Annotation
DoneAwaitCmd 1 - - - - Covered T1,T2,T3
DoneAwaitCmd 0 1 - - - Covered T3,T4,T5
DoneAwaitCmd 0 0 - - - Covered T1,T2,T3
DoneAwaitHashDone - - 1 - - Covered T1,T2,T3
DoneAwaitHashDone - - 0 - - Covered T1,T2,T3
DoneAwaitMessageComplete - - - 1 - Covered T3,T4,T5
DoneAwaitMessageComplete - - - 0 - Covered T3,T4,T5
DoneAwaitHashComplete - - - - 1 Covered T3,T4,T5
DoneAwaitHashComplete - - - - 0 Excluded VC_COV_UNR
default - - - - - Excluded VC_COV_UNR


LineNo. Expression -1-: 192 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 205 if (wipe_secret) -2-: 207 if ((!cfg_block))

Branches:
-1--2-StatusTests
1 - Covered T1,T4,T25
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 219 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 240 if ((digest_size == SHA2_256)) -2-: 244 if (((digest_size == SHA2_384) || (digest_size == SHA2_512))) -3-: 246 (reg2hw.digest[(2 * i)].qe) ? -4-: 249 (reg2hw.digest[((2 * i) + 1)].qe) ?

Branches:
-1--2--3--4-StatusTests
1 - - - Covered T1,T3,T4
0 1 1 - Covered T4,T5,T15
0 1 0 - Covered T1,T2,T3
0 1 - 1 Covered T4,T5,T15
0 1 - 0 Covered T1,T2,T3
0 0 - - Covered T1,T2,T3


LineNo. Expression -1-: 256 if ((digest_size_started_q == SHA2_256)) -2-: 262 if (((digest_size_started_q == SHA2_384) || (digest_size_started_q == SHA2_512)))

Branches:
-1--2-StatusTests
1 - Covered T1,T3,T4
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 289 case (digest_size_supplied)

Branches:
-1-StatusTests
SHA2_256 Covered T1,T3,T4
SHA2_384 Covered T1,T2,T3
SHA2_512 Covered T1,T2,T3
default Covered T1,T2,T3


LineNo. Expression -1-: 304 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 312 case (key_length_supplied)

Branches:
-1-StatusTests
Key_128 Covered T1,T3,T4
Key_256 Covered T1,T2,T3
Key_384 Covered T1,T3,T4
Key_512 Covered T1,T2,T3
Key_1024 Covered T1,T3,T4
default Covered T1,T2,T3


LineNo. Expression -1-: 355 if ((!rst_ni)) -2-: 357 if (hash_start_or_continue) -3-: 359 if ((reg_hash_done || reg_hash_stop))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T1,T2,T3
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 365 if ((!rst_ni)) -2-: 397 if (((!cfg_block) && reg2hw.cfg.hmac_en.qe))

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 404 if ((!rst_ni)) -2-: 406 if (hash_start_or_continue) -3-: 408 if (packer_flush_done)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T1,T2,T3
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 475 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 545 if (hmac_fifo_wsel) -2-: 547 if ((digest_size == SHA2_256)) -3-: 550 if (((digest_size == SHA2_384) || (digest_size == SHA2_512)))

Branches:
-1--2--3-StatusTests
1 1 - Covered T1,T3,T4
1 0 1 Covered T1,T2,T3
1 0 0 Not Covered
0 - - Covered T1,T2,T3


LineNo. Expression -1-: 630 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 636 if ((!cfg_block)) -2-: 637 if (reg2hw.msg_length_lower.qe) -3-: 640 if (reg2hw.msg_length_upper.qe)

Branches:
-1--2--3-StatusTests
1 1 - Covered T3,T4,T5
1 0 - Covered T1,T2,T3
1 - 1 Covered T3,T4,T5
1 - 0 Covered T1,T2,T3
0 - - Covered T1,T2,T3


LineNo. Expression -1-: 645 if (hash_start) -2-: 647 if (((msg_write && sha_en) && packer_ready))

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 816 if (cfg_block)

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 839 case (1'b1)

Branches:
-1-StatusTests
invalid_config_atstart Covered T1,T2,T3
hash_start_sha_disabled Covered T4,T25,T29
hash_start_active Covered T4,T40,T25
msg_push_not_allowed Covered T1,T2,T3
update_seckey_inprocess Covered T4,T22,T40
default Covered T1,T2,T3


LineNo. Expression -1-: 886 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 914 if ((!rst_ni)) -2-: 915 if ((hash_process || reg_hash_stop)) -3-: 916 if (reg_hash_done)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T1,T2,T3
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 921 if ((!rst_ni)) -2-: 922 if (hash_start_or_continue) -3-: 923 if ((hash_process || reg_hash_stop))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T1,T2,T3
0 0 0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 13 13 100.00 13 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 13 13 100.00 13 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AlertKnownO_A 505207750 505141086 0 0
FpvSecCmRegWeOnehotCheck_A 505207750 130 0 0
IntrFifoEmptyOKnown 505207750 505141086 0 0
IntrHmacDoneOKnown 505207750 505141086 0 0
TlOAReadyKnown 505207750 505141086 0 0
TlODValidKnown 505207750 505141086 0 0
ValidHashProcessAssert 505207750 19215 0 0
ValidHmacEnConditionAssert 505207750 12293 0 0
ValidWriteAssert 505207750 19986379 0 0
gen_assert_wmask_bytealign[0].unnamed$$_0 505207750 19986379 0 0
gen_assert_wmask_bytealign[1].unnamed$$_0 505207750 19986379 0 0
gen_assert_wmask_bytealign[2].unnamed$$_0 505207750 19986379 0 0
gen_assert_wmask_bytealign[3].unnamed$$_0 505207750 19986379 0 0


AlertKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 505207750 505141086 0 0
T1 632330 632248 0 0
T2 21045 20978 0 0
T3 333149 333075 0 0
T4 653077 652971 0 0
T5 175511 175432 0 0
T14 143242 143157 0 0
T15 296555 296460 0 0
T16 228356 228280 0 0
T17 53663 53601 0 0
T18 1102 1039 0 0

FpvSecCmRegWeOnehotCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 505207750 130 0 0
T36 348356 0 0 0
T44 8252 30 0 0
T45 6393 20 0 0
T46 0 20 0 0
T47 0 30 0 0
T48 0 30 0 0
T49 1086 0 0 0
T50 44379 0 0 0
T51 295142 0 0 0
T52 210870 0 0 0
T53 11140 0 0 0
T54 559908 0 0 0
T55 688643 0 0 0

IntrFifoEmptyOKnown
NameAttemptsReal SuccessesFailuresIncomplete
Total 505207750 505141086 0 0
T1 632330 632248 0 0
T2 21045 20978 0 0
T3 333149 333075 0 0
T4 653077 652971 0 0
T5 175511 175432 0 0
T14 143242 143157 0 0
T15 296555 296460 0 0
T16 228356 228280 0 0
T17 53663 53601 0 0
T18 1102 1039 0 0

IntrHmacDoneOKnown
NameAttemptsReal SuccessesFailuresIncomplete
Total 505207750 505141086 0 0
T1 632330 632248 0 0
T2 21045 20978 0 0
T3 333149 333075 0 0
T4 653077 652971 0 0
T5 175511 175432 0 0
T14 143242 143157 0 0
T15 296555 296460 0 0
T16 228356 228280 0 0
T17 53663 53601 0 0
T18 1102 1039 0 0

TlOAReadyKnown
NameAttemptsReal SuccessesFailuresIncomplete
Total 505207750 505141086 0 0
T1 632330 632248 0 0
T2 21045 20978 0 0
T3 333149 333075 0 0
T4 653077 652971 0 0
T5 175511 175432 0 0
T14 143242 143157 0 0
T15 296555 296460 0 0
T16 228356 228280 0 0
T17 53663 53601 0 0
T18 1102 1039 0 0

TlODValidKnown
NameAttemptsReal SuccessesFailuresIncomplete
Total 505207750 505141086 0 0
T1 632330 632248 0 0
T2 21045 20978 0 0
T3 333149 333075 0 0
T4 653077 652971 0 0
T5 175511 175432 0 0
T14 143242 143157 0 0
T15 296555 296460 0 0
T16 228356 228280 0 0
T17 53663 53601 0 0
T18 1102 1039 0 0

ValidHashProcessAssert
NameAttemptsReal SuccessesFailuresIncomplete
Total 505207750 19215 0 0
T1 632330 21 0 0
T2 21045 2 0 0
T3 333149 10 0 0
T4 653077 182 0 0
T5 175511 19 0 0
T14 143242 14 0 0
T15 296555 21 0 0
T16 228356 17 0 0
T17 53663 6 0 0
T18 1102 0 0 0
T22 0 194 0 0

ValidHmacEnConditionAssert
NameAttemptsReal SuccessesFailuresIncomplete
Total 505207750 12293 0 0
T1 632330 19 0 0
T2 21045 3 0 0
T3 333149 1 0 0
T4 653077 238 0 0
T5 175511 6 0 0
T14 143242 15 0 0
T15 296555 15 0 0
T16 228356 11 0 0
T17 53663 11 0 0
T18 1102 0 0 0
T56 0 1 0 0

ValidWriteAssert
NameAttemptsReal SuccessesFailuresIncomplete
Total 505207750 19986379 0 0
T1 632330 21571 0 0
T2 21045 354 0 0
T3 333149 40667 0 0
T4 653077 241593 0 0
T5 175511 20662 0 0
T14 143242 16780 0 0
T15 296555 22850 0 0
T16 228356 10396 0 0
T17 53663 13073 0 0
T18 1102 0 0 0
T22 0 74244 0 0

gen_assert_wmask_bytealign[0].unnamed$$_0
NameAttemptsReal SuccessesFailuresIncomplete
Total 505207750 19986379 0 0
T1 632330 21571 0 0
T2 21045 354 0 0
T3 333149 40667 0 0
T4 653077 241593 0 0
T5 175511 20662 0 0
T14 143242 16780 0 0
T15 296555 22850 0 0
T16 228356 10396 0 0
T17 53663 13073 0 0
T18 1102 0 0 0
T22 0 74244 0 0

gen_assert_wmask_bytealign[1].unnamed$$_0
NameAttemptsReal SuccessesFailuresIncomplete
Total 505207750 19986379 0 0
T1 632330 21571 0 0
T2 21045 354 0 0
T3 333149 40667 0 0
T4 653077 241593 0 0
T5 175511 20662 0 0
T14 143242 16780 0 0
T15 296555 22850 0 0
T16 228356 10396 0 0
T17 53663 13073 0 0
T18 1102 0 0 0
T22 0 74244 0 0

gen_assert_wmask_bytealign[2].unnamed$$_0
NameAttemptsReal SuccessesFailuresIncomplete
Total 505207750 19986379 0 0
T1 632330 21571 0 0
T2 21045 354 0 0
T3 333149 40667 0 0
T4 653077 241593 0 0
T5 175511 20662 0 0
T14 143242 16780 0 0
T15 296555 22850 0 0
T16 228356 10396 0 0
T17 53663 13073 0 0
T18 1102 0 0 0
T22 0 74244 0 0

gen_assert_wmask_bytealign[3].unnamed$$_0
NameAttemptsReal SuccessesFailuresIncomplete
Total 505207750 19986379 0 0
T1 632330 21571 0 0
T2 21045 354 0 0
T3 333149 40667 0 0
T4 653077 241593 0 0
T5 175511 20662 0 0
T14 143242 16780 0 0
T15 296555 22850 0 0
T16 228356 10396 0 0
T17 53663 13073 0 0
T18 1102 0 0 0
T22 0 74244 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%