Unified Coverage Report :: Module :: prim_fifo_sync

Module : prim_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
86.88	93.33	54.17			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_tlul_adapter.u_rspfifo	84.64	92.86	100.00			85.71	60.00
tb.dut.u_tlul_adapter.u_sramreqfifo	86.43	85.71	100.00			100.00	60.00
tb.dut.u_msg_fifo	100.00	100.00	100.00			100.00	100.00
tb.dut.u_tlul_adapter.u_reqfifo	100.00	100.00	100.00			100.00	100.00
tb.dut.u_reg.u_socket.fifo_h.reqfifo	100.00	100.00					100.00
tb.dut.u_reg.u_socket.fifo_h.rspfifo	100.00	100.00					100.00
tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo	100.00	100.00					100.00

---

Module Instance : tb.dut.u_tlul_adapter.u_rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
84.64	92.86	100.00			85.71	60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
87.20	97.14	100.00			91.67	60.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.80	98.57	100.00			100.00	84.62	u_tlul_adapter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00			100.00

---

Module Instance : tb.dut.u_tlul_adapter.u_sramreqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
86.43	85.71	100.00			100.00	60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
88.57	94.29	100.00			100.00	60.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.80	98.57	100.00			100.00	84.62	u_tlul_adapter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00			100.00

---

Module Instance : tb.dut.u_msg_fifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.71	100.00	93.33	100.00	100.00	98.90	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00			100.00

---

Module Instance : tb.dut.u_tlul_adapter.u_reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.80	98.57	100.00			100.00	84.62	u_tlul_adapter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00			100.00

---

Module Instance : tb.dut.u_reg.u_socket.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg.u_socket.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_fifo_sync ( parameter Width=36,Pass=1,Depth=32,OutputZeroIfEmpty=1,Secure=0,DepthW=6,gen_normal_fifo.PtrW=5 )
Line Coverage for Module self-instances :

SCORE	LINE
100.00	100.00

tb.dut.u_msg_fifo

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	130	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
130	1	1
131	1	1
138	1	1

---

Line Coverage for Module : prim_fifo_sync ( parameter Width=17,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
100.00	100.00

tb.dut.u_tlul_adapter.u_reqfifo

	Line No.	Total	Covered	Percent
TOTAL		15	15	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
ALWAYS	111	2	2	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
108	1	1
111	1	1
112	1	1
			MISSING_ELSE
116	1	1
133	1	1
134	1	1
138	1	1

---

Line Coverage for Module : prim_fifo_sync ( parameter Width=5,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
86.43	85.71

tb.dut.u_tlul_adapter.u_sramreqfifo

	Line No.	Total	Covered	Percent
TOTAL		15	12	80.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	0	0.00
ALWAYS	111	2	1	50.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	133	1	0	0.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
108	0	1
111	1	1
112	0	1
			MISSING_ELSE
116	1	1
133	0	1
134	1	1
138	1	1

---

Line Coverage for Module : prim_fifo_sync ( parameter Width=40,Pass=1,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
84.64	92.86

tb.dut.u_tlul_adapter.u_rspfifo

	Line No.	Total	Covered	Percent
TOTAL		15	13	86.67
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	0	0.00
ALWAYS	111	2	1	50.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	130	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
108	0	1
111	1	1
112	0	1
			MISSING_ELSE
116	1	1
130	1	1
131	1	1
138	1	1

---

Line Coverage for Module : prim_fifo_sync ( parameter Width=108,Pass=1,Depth=0,OutputZeroIfEmpty=1,Secure=0,DepthW=1 + Width=65,Pass=1,Depth=0,OutputZeroIfEmpty=1,Secure=0,DepthW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_socket.fifo_h.reqfifo

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_socket.fifo_h.rspfifo

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Cond Coverage for Module : prim_fifo_sync ( parameter Width=5,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
86.43	100.00

tb.dut.u_tlul_adapter.u_sramreqfifo

	Total	Covered	Percent
Conditions	16	5	31.25
Logical	16	5	31.25
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Not Covered

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (5'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T2,T3

---

Cond Coverage for Module : prim_fifo_sync ( parameter Width=36,Pass=1,Depth=32,OutputZeroIfEmpty=1,Secure=0,DepthW=6,gen_normal_fifo.PtrW=5 )
Cond Coverage for Module self-instances :

SCORE	COND
100.00	100.00

tb.dut.u_msg_fifo

	Total	Covered	Percent
Conditions	24	20	83.33
Logical	24	20	83.33
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T17,T25,T9
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T9,T6,T10
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (36'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Cond Coverage for Module : prim_fifo_sync ( parameter Width=40,Pass=1,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
84.64	100.00

tb.dut.u_tlul_adapter.u_rspfifo

	Total	Covered	Percent
Conditions	24	8	33.33
Logical	24	8	33.33
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Not Covered

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (40'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T2,T3

---

Cond Coverage for Module : prim_fifo_sync ( parameter Width=17,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
100.00	100.00

tb.dut.u_tlul_adapter.u_reqfifo

	Total	Covered	Percent
Conditions	16	11	68.75
Logical	16	11	68.75
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T2,T4
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (17'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_fifo_sync ( parameter Width=36,Pass=1,Depth=32,OutputZeroIfEmpty=1,Secure=0,DepthW=6,gen_normal_fifo.PtrW=5 + Width=40,Pass=1,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 )
Branch Coverage for Module self-instances :

SCORE	BRANCH
100.00	100.00

tb.dut.u_msg_fifo

SCORE	BRANCH
84.64	85.71

tb.dut.u_tlul_adapter.u_rspfifo

	Line No.	Total	Covered	Percent
Branches		9	9	100.00
TERNARY	130	2	2	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	130	((gen_normal_fifo.fifo_empty && wvalid_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_fifo_sync ( parameter Width=17,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 + Width=5,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 )
Branch Coverage for Module self-instances :

SCORE	BRANCH
100.00	100.00

tb.dut.u_tlul_adapter.u_reqfifo

SCORE	BRANCH
86.43	100.00

tb.dut.u_tlul_adapter.u_sramreqfifo

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	598407271	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	2020831000	62035241	0	0
gen_passthru_fifo.paramCheckPass	3954	3954	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	598407271	0	0
T1	5058640	406250	0	0
T2	168360	22785	0	0
T3	2665192	719557	0	0
T4	5224616	4143022	0	0
T5	1404088	391900	0	0
T14	1145936	311575	0	0
T15	2372440	227864	0	0
T16	1826848	305694	0	0
T17	429304	130038	0	0
T18	8816	72	0	0
T22	0	435835	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	6323300	6322480	0	0
T2	210450	209780	0	0
T3	3331490	3330750	0	0
T4	6530770	6529710	0	0
T5	1755110	1754320	0	0
T14	1432420	1431570	0	0
T15	2965550	2964600	0	0
T16	2283560	2282800	0	0
T17	536630	536010	0	0
T18	11020	10390	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	6323300	6322480	0	0
T2	210450	209780	0	0
T3	3331490	3330750	0	0
T4	6530770	6529710	0	0
T5	1755110	1754320	0	0
T14	1432420	1431570	0	0
T15	2965550	2964600	0	0
T16	2283560	2282800	0	0
T17	536630	536010	0	0
T18	11020	10390	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	6323300	6322480	0	0
T2	210450	209780	0	0
T3	3331490	3330750	0	0
T4	6530770	6529710	0	0
T5	1755110	1754320	0	0
T14	1432420	1431570	0	0
T15	2965550	2964600	0	0
T16	2283560	2282800	0	0
T17	536630	536010	0	0
T18	11020	10390	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	2020831000	62035241	0	0
T1	1264660	48810	0	0
T2	42090	1949	0	0
T3	666298	59533	0	0
T4	1306154	444008	0	0
T5	351022	48768	0	0
T14	286484	34115	0	0
T15	593110	60036	0	0
T16	456712	71926	0	0
T17	107326	26734	0	0
T18	2204	0	0	0
T22	0	287347	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	3954	3954	0	0
T1	6	6	0	0
T2	6	6	0	0
T3	6	6	0	0
T4	6	6	0	0
T5	6	6	0	0
T14	6	6	0	0
T15	6	6	0	0
T16	6	6	0	0
T17	6	6	0	0
T18	6	6	0	0

Line Coverage for Instance : tb.dut.u_tlul_adapter.u_rspfifo

	Line No.	Total	Covered	Percent
TOTAL		14	13	92.86
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	0	0.00
ALWAYS	111	1	1	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	130	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
108	0	1
111	1	1
112		excluded
			Exclude Annotation: VC_COV_UNR
			MISSING_ELSE
116	1	1
130	1	1
131	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.u_tlul_adapter.u_rspfifo

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Excluded		VC_COV_UNR
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T2,T3
1	0	Excluded		VC_COV_UNR
1	1	Excluded		VC_COV_UNR

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Excluded		VC_COV_UNR
1	1	1	Excluded		VC_COV_UNR

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Excluded		VC_COV_UNR
1	0	1	Excluded		VC_COV_UNR
1	1	0	Excluded		VC_COV_UNR
1	1	1	Excluded		VC_COV_UNR

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------

-1-	Status	Tests	Exclude Annotation
0	Covered	T1,T2,T3
1	Excluded		VC_COV_UNR

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Excluded		VC_COV_UNR
1	0	Covered	T1,T2,T3
1	1	Excluded		VC_COV_UNR

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Excluded		VC_COV_UNR
1	0	Excluded		VC_COV_UNR
1	1	Covered	T1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (40'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests	Exclude Annotation
0	Excluded		VC_COV_UNR
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_tlul_adapter.u_rspfifo

	Line No.	Total	Covered	Percent
Branches		7	6	85.71
TERNARY	130	1	1	100.00
TERNARY	138	1	1	100.00
IF	69	3	3	100.00
IF	123	2	1	50.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	130	((gen_normal_fifo.fifo_empty && wvalid_i)) ? 

Branches:

-1-	Status	Tests	Exclude Annotation
1	Excluded		VC_COV_UNR
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests	Exclude Annotation
1	Covered	T1,T2,T3
0	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_tlul_adapter.u_rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	3	60.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	3	60.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	505207750	0	0	0
DepthKnown_A	505207750	505141086	0	0
RvalidKnown_A	505207750	505141086	0	0
WreadyKnown_A	505207750	505141086	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	505207750	0	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	505207750	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	505207750	505141086	0	0
T1	632330	632248	0	0
T2	21045	20978	0	0
T3	333149	333075	0	0
T4	653077	652971	0	0
T5	175511	175432	0	0
T14	143242	143157	0	0
T15	296555	296460	0	0
T16	228356	228280	0	0
T17	53663	53601	0	0
T18	1102	1039	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	505207750	505141086	0	0
T1	632330	632248	0	0
T2	21045	20978	0	0
T3	333149	333075	0	0
T4	653077	652971	0	0
T5	175511	175432	0	0
T14	143242	143157	0	0
T15	296555	296460	0	0
T16	228356	228280	0	0
T17	53663	53601	0	0
T18	1102	1039	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	505207750	505141086	0	0
T1	632330	632248	0	0
T2	21045	20978	0	0
T3	333149	333075	0	0
T4	653077	652971	0	0
T5	175511	175432	0	0
T14	143242	143157	0	0
T15	296555	296460	0	0
T16	228356	228280	0	0
T17	53663	53601	0	0
T18	1102	1039	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	505207750	0	0	0

Line Coverage for Instance : tb.dut.u_tlul_adapter.u_sramreqfifo

	Line No.	Total	Covered	Percent
TOTAL		14	12	85.71
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	0	0.00
ALWAYS	111	1	1	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	133	1	0	0.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
108	0	1
111	1	1
112		excluded
			Exclude Annotation: VC_COV_UNR
			MISSING_ELSE
116	1	1
133	0	1
134	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.u_tlul_adapter.u_sramreqfifo

	Total	Covered	Percent
Conditions	5	5	100.00
Logical	5	5	100.00
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Excluded		VC_COV_UNR
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T2,T3
1	0	Excluded		VC_COV_UNR
1	1	Excluded		VC_COV_UNR

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Excluded		VC_COV_UNR
1	1	1	Excluded		VC_COV_UNR

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Excluded		VC_COV_UNR
1	0	1	Excluded		VC_COV_UNR
1	1	0	Excluded		VC_COV_UNR
1	1	1	Excluded		VC_COV_UNR

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (5'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests	Exclude Annotation
0	Excluded		VC_COV_UNR
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_tlul_adapter.u_sramreqfifo

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
TERNARY	138	1	1	100.00
IF	69	3	3	100.00
IF	111	1	1	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests	Exclude Annotation
1	Covered	T1,T2,T3
0	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests	Exclude Annotation
1	Excluded		VC_COV_UNR
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_tlul_adapter.u_sramreqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	3	60.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	3	60.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	505207750	0	0	0
DepthKnown_A	505207750	505141086	0	0
RvalidKnown_A	505207750	505141086	0	0
WreadyKnown_A	505207750	505141086	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	505207750	0	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	505207750	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	505207750	505141086	0	0
T1	632330	632248	0	0
T2	21045	20978	0	0
T3	333149	333075	0	0
T4	653077	652971	0	0
T5	175511	175432	0	0
T14	143242	143157	0	0
T15	296555	296460	0	0
T16	228356	228280	0	0
T17	53663	53601	0	0
T18	1102	1039	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	505207750	505141086	0	0
T1	632330	632248	0	0
T2	21045	20978	0	0
T3	333149	333075	0	0
T4	653077	652971	0	0
T5	175511	175432	0	0
T14	143242	143157	0	0
T15	296555	296460	0	0
T16	228356	228280	0	0
T17	53663	53601	0	0
T18	1102	1039	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	505207750	505141086	0	0
T1	632330	632248	0	0
T2	21045	20978	0	0
T3	333149	333075	0	0
T4	653077	652971	0	0
T5	175511	175432	0	0
T14	143242	143157	0	0
T15	296555	296460	0	0
T16	228356	228280	0	0
T17	53663	53601	0	0
T18	1102	1039	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	505207750	0	0	0

Line Coverage for Instance : tb.dut.u_msg_fifo

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	130	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
130	1	1
131	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.u_msg_fifo

	Total	Covered	Percent
Conditions	20	20	100.00
Logical	20	20	100.00
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T17,T25,T9
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T2,T3
1	0	Excluded		VC_COV_UNR
1	1	Covered	T1,T2,T3

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T9,T6,T10
1	1	0	Excluded		VC_COV_UNR
1	1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Excluded		VC_COV_UNR
1	0	1	Covered	T1,T2,T3
1	1	0	Excluded		VC_COV_UNR
1	1	1	Covered	T1,T2,T3

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (36'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_msg_fifo

	Line No.	Total	Covered	Percent
Branches		9	9	100.00
TERNARY	130	2	2	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	130	((gen_normal_fifo.fifo_empty && wvalid_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_msg_fifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	505207750	23230130	0	0
DepthKnown_A	505207750	505141086	0	0
RvalidKnown_A	505207750	505141086	0	0
WreadyKnown_A	505207750	505141086	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	505207750	23230130	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	505207750	23230130	0	0
T1	632330	27239	0	0
T2	21045	336	0	0
T3	333149	18866	0	0
T4	653077	202415	0	0
T5	175511	28106	0	0
T14	143242	17335	0	0
T15	296555	37186	0	0
T16	228356	25041	0	0
T17	53663	13661	0	0
T18	1102	0	0	0
T22	0	213103	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	505207750	505141086	0	0
T1	632330	632248	0	0
T2	21045	20978	0	0
T3	333149	333075	0	0
T4	653077	652971	0	0
T5	175511	175432	0	0
T14	143242	143157	0	0
T15	296555	296460	0	0
T16	228356	228280	0	0
T17	53663	53601	0	0
T18	1102	1039	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	505207750	505141086	0	0
T1	632330	632248	0	0
T2	21045	20978	0	0
T3	333149	333075	0	0
T4	653077	652971	0	0
T5	175511	175432	0	0
T14	143242	143157	0	0
T15	296555	296460	0	0
T16	228356	228280	0	0
T17	53663	53601	0	0
T18	1102	1039	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	505207750	505141086	0	0
T1	632330	632248	0	0
T2	21045	20978	0	0
T3	333149	333075	0	0
T4	653077	652971	0	0
T5	175511	175432	0	0
T14	143242	143157	0	0
T15	296555	296460	0	0
T16	228356	228280	0	0
T17	53663	53601	0	0
T18	1102	1039	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	505207750	23230130	0	0
T1	632330	27239	0	0
T2	21045	336	0	0
T3	333149	18866	0	0
T4	653077	202415	0	0
T5	175511	28106	0	0
T14	143242	17335	0	0
T15	296555	37186	0	0
T16	228356	25041	0	0
T17	53663	13661	0	0
T18	1102	0	0	0
T22	0	213103	0	0

Line Coverage for Instance : tb.dut.u_tlul_adapter.u_reqfifo

	Line No.	Total	Covered	Percent
TOTAL		15	15	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
ALWAYS	111	2	2	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
108	1	1
111	1	1
112	1	1
			MISSING_ELSE
116	1	1
133	1	1
134	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.u_tlul_adapter.u_reqfifo

	Total	Covered	Percent
Conditions	11	11	100.00
Logical	11	11	100.00
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T2,T3
1	0	Excluded		VC_COV_UNR
1	1	Covered	T1,T2,T3

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Excluded		VC_COV_UNR
1	1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Excluded		VC_COV_UNR
1	0	1	Covered	T1,T2,T4
1	1	0	Excluded		VC_COV_UNR
1	1	1	Covered	T1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (17'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_tlul_adapter.u_reqfifo

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_tlul_adapter.u_reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	505207750	38805111	0	0
DepthKnown_A	505207750	505141086	0	0
RvalidKnown_A	505207750	505141086	0	0
WreadyKnown_A	505207750	505141086	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	505207750	38805111	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	505207750	38805111	0	0
T1	632330	21571	0	0
T2	21045	1613	0	0
T3	333149	40667	0	0
T4	653077	241593	0	0
T5	175511	20662	0	0
T14	143242	16780	0	0
T15	296555	22850	0	0
T16	228356	46885	0	0
T17	53663	13073	0	0
T18	1102	0	0	0
T22	0	74244	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	505207750	505141086	0	0
T1	632330	632248	0	0
T2	21045	20978	0	0
T3	333149	333075	0	0
T4	653077	652971	0	0
T5	175511	175432	0	0
T14	143242	143157	0	0
T15	296555	296460	0	0
T16	228356	228280	0	0
T17	53663	53601	0	0
T18	1102	1039	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	505207750	505141086	0	0
T1	632330	632248	0	0
T2	21045	20978	0	0
T3	333149	333075	0	0
T4	653077	652971	0	0
T5	175511	175432	0	0
T14	143242	143157	0	0
T15	296555	296460	0	0
T16	228356	228280	0	0
T17	53663	53601	0	0
T18	1102	1039	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	505207750	505141086	0	0
T1	632330	632248	0	0
T2	21045	20978	0	0
T3	333149	333075	0	0
T4	653077	652971	0	0
T5	175511	175432	0	0
T14	143242	143157	0	0
T15	296555	296460	0	0
T16	228356	228280	0	0
T17	53663	53601	0	0
T18	1102	1039	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	505207750	38805111	0	0
T1	632330	21571	0	0
T2	21045	1613	0	0
T3	333149	40667	0	0
T4	653077	241593	0	0
T5	175511	20662	0	0
T14	143242	16780	0	0
T15	296555	22850	0	0
T16	228356	46885	0	0
T17	53663	13073	0	0
T18	1102	0	0	0
T22	0	74244	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	514677709	101008375	0	0
DepthKnown_A	514677709	514566413	0	0
RvalidKnown_A	514677709	514566413	0	0
WreadyKnown_A	514677709	514566413	0	0
gen_passthru_fifo.paramCheckPass	659	659	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	514677709	101008375	0	0
T1	632330	89360	0	0
T2	21045	1886	0	0
T3	333149	165006	0	0
T4	653077	924754	0	0
T5	175511	85783	0	0
T14	143242	69365	0	0
T15	296555	41957	0	0
T16	228356	21244	0	0
T17	53663	25826	0	0
T18	1102	18	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	514677709	514566413	0	0
T1	632330	632248	0	0
T2	21045	20978	0	0
T3	333149	333075	0	0
T4	653077	652971	0	0
T5	175511	175432	0	0
T14	143242	143157	0	0
T15	296555	296460	0	0
T16	228356	228280	0	0
T17	53663	53601	0	0
T18	1102	1039	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	514677709	514566413	0	0
T1	632330	632248	0	0
T2	21045	20978	0	0
T3	333149	333075	0	0
T4	653077	652971	0	0
T5	175511	175432	0	0
T14	143242	143157	0	0
T15	296555	296460	0	0
T16	228356	228280	0	0
T17	53663	53601	0	0
T18	1102	1039	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	514677709	514566413	0	0
T1	632330	632248	0	0
T2	21045	20978	0	0
T3	333149	333075	0	0
T4	653077	652971	0	0
T5	175511	175432	0	0
T14	143242	143157	0	0
T15	296555	296460	0	0
T16	228356	228280	0	0
T17	53663	53601	0	0
T18	1102	1039	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	659	659	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	514677709	168811190	0	0
DepthKnown_A	514677709	514566413	0	0
RvalidKnown_A	514677709	514566413	0	0
WreadyKnown_A	514677709	514566413	0	0
gen_passthru_fifo.paramCheckPass	659	659	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	514677709	168811190	0	0
T1	632330	89360	0	0
T2	21045	8532	0	0
T3	333149	165006	0	0
T4	653077	924753	0	0
T5	175511	85783	0	0
T14	143242	69365	0	0
T15	296555	41957	0	0
T16	228356	95640	0	0
T17	53663	25826	0	0
T18	1102	18	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	514677709	514566413	0	0
T1	632330	632248	0	0
T2	21045	20978	0	0
T3	333149	333075	0	0
T4	653077	652971	0	0
T5	175511	175432	0	0
T14	143242	143157	0	0
T15	296555	296460	0	0
T16	228356	228280	0	0
T17	53663	53601	0	0
T18	1102	1039	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	514677709	514566413	0	0
T1	632330	632248	0	0
T2	21045	20978	0	0
T3	333149	333075	0	0
T4	653077	652971	0	0
T5	175511	175432	0	0
T14	143242	143157	0	0
T15	296555	296460	0	0
T16	228356	228280	0	0
T17	53663	53601	0	0
T18	1102	1039	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	514677709	514566413	0	0
T1	632330	632248	0	0
T2	21045	20978	0	0
T3	333149	333075	0	0
T4	653077	652971	0	0
T5	175511	175432	0	0
T14	143242	143157	0	0
T15	296555	296460	0	0
T16	228356	228280	0	0
T17	53663	53601	0	0
T18	1102	1039	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	659	659	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	514677709	24878513	0	0
DepthKnown_A	514677709	514566413	0	0
RvalidKnown_A	514677709	514566413	0	0
WreadyKnown_A	514677709	514566413	0	0
gen_passthru_fifo.paramCheckPass	659	659	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	514677709	24878513	0	0
T1	632330	21571	0	0
T2	21045	354	0	0
T3	333149	40667	0	0
T4	653077	241593	0	0
T5	175511	20662	0	0
T14	143242	16780	0	0
T15	296555	22850	0	0
T16	228356	10396	0	0
T17	53663	13073	0	0
T18	1102	0	0	0
T22	0	74244	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	514677709	514566413	0	0
T1	632330	632248	0	0
T2	21045	20978	0	0
T3	333149	333075	0	0
T4	653077	652971	0	0
T5	175511	175432	0	0
T14	143242	143157	0	0
T15	296555	296460	0	0
T16	228356	228280	0	0
T17	53663	53601	0	0
T18	1102	1039	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	514677709	514566413	0	0
T1	632330	632248	0	0
T2	21045	20978	0	0
T3	333149	333075	0	0
T4	653077	652971	0	0
T5	175511	175432	0	0
T14	143242	143157	0	0
T15	296555	296460	0	0
T16	228356	228280	0	0
T17	53663	53601	0	0
T18	1102	1039	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	514677709	514566413	0	0
T1	632330	632248	0	0
T2	21045	20978	0	0
T3	333149	333075	0	0
T4	653077	652971	0	0
T5	175511	175432	0	0
T14	143242	143157	0	0
T15	296555	296460	0	0
T16	228356	228280	0	0
T17	53663	53601	0	0
T18	1102	1039	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	659	659	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	514677709	39774943	0	0
DepthKnown_A	514677709	514566413	0	0
RvalidKnown_A	514677709	514566413	0	0
WreadyKnown_A	514677709	514566413	0	0
gen_passthru_fifo.paramCheckPass	659	659	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	514677709	39774943	0	0
T1	632330	21571	0	0
T2	21045	1613	0	0
T3	333149	40667	0	0
T4	653077	241593	0	0
T5	175511	20662	0	0
T14	143242	16780	0	0
T15	296555	22850	0	0
T16	228356	46885	0	0
T17	53663	13073	0	0
T18	1102	0	0	0
T22	0	74244	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	514677709	514566413	0	0
T1	632330	632248	0	0
T2	21045	20978	0	0
T3	333149	333075	0	0
T4	653077	652971	0	0
T5	175511	175432	0	0
T14	143242	143157	0	0
T15	296555	296460	0	0
T16	228356	228280	0	0
T17	53663	53601	0	0
T18	1102	1039	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	514677709	514566413	0	0
T1	632330	632248	0	0
T2	21045	20978	0	0
T3	333149	333075	0	0
T4	653077	652971	0	0
T5	175511	175432	0	0
T14	143242	143157	0	0
T15	296555	296460	0	0
T16	228356	228280	0	0
T17	53663	53601	0	0
T18	1102	1039	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	514677709	514566413	0	0
T1	632330	632248	0	0
T2	21045	20978	0	0
T3	333149	333075	0	0
T4	653077	652971	0	0
T5	175511	175432	0	0
T14	143242	143157	0	0
T15	296555	296460	0	0
T16	228356	228280	0	0
T17	53663	53601	0	0
T18	1102	1039	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	659	659	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	514677709	72862762	0	0
DepthKnown_A	514677709	514566413	0	0
RvalidKnown_A	514677709	514566413	0	0
WreadyKnown_A	514677709	514566413	0	0
gen_passthru_fifo.paramCheckPass	659	659	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	514677709	72862762	0	0
T1	632330	67789	0	0
T2	21045	1532	0	0
T3	333149	124339	0	0
T4	653077	683161	0	0
T5	175511	65121	0	0
T14	143242	52585	0	0
T15	296555	19107	0	0
T16	228356	10848	0	0
T17	53663	12753	0	0
T18	1102	18	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	514677709	514566413	0	0
T1	632330	632248	0	0
T2	21045	20978	0	0
T3	333149	333075	0	0
T4	653077	652971	0	0
T5	175511	175432	0	0
T14	143242	143157	0	0
T15	296555	296460	0	0
T16	228356	228280	0	0
T17	53663	53601	0	0
T18	1102	1039	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	514677709	514566413	0	0
T1	632330	632248	0	0
T2	21045	20978	0	0
T3	333149	333075	0	0
T4	653077	652971	0	0
T5	175511	175432	0	0
T14	143242	143157	0	0
T15	296555	296460	0	0
T16	228356	228280	0	0
T17	53663	53601	0	0
T18	1102	1039	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	514677709	514566413	0	0
T1	632330	632248	0	0
T2	21045	20978	0	0
T3	333149	333075	0	0
T4	653077	652971	0	0
T5	175511	175432	0	0
T14	143242	143157	0	0
T15	296555	296460	0	0
T16	228356	228280	0	0
T17	53663	53601	0	0
T18	1102	1039	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	659	659	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	514677709	129036247	0	0
DepthKnown_A	514677709	514566413	0	0
RvalidKnown_A	514677709	514566413	0	0
WreadyKnown_A	514677709	514566413	0	0
gen_passthru_fifo.paramCheckPass	659	659	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	514677709	129036247	0	0
T1	632330	67789	0	0
T2	21045	6919	0	0
T3	333149	124339	0	0
T4	653077	683160	0	0
T5	175511	65121	0	0
T14	143242	52585	0	0
T15	296555	19107	0	0
T16	228356	48755	0	0
T17	53663	12753	0	0
T18	1102	18	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	514677709	514566413	0	0
T1	632330	632248	0	0
T2	21045	20978	0	0
T3	333149	333075	0	0
T4	653077	652971	0	0
T5	175511	175432	0	0
T14	143242	143157	0	0
T15	296555	296460	0	0
T16	228356	228280	0	0
T17	53663	53601	0	0
T18	1102	1039	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	514677709	514566413	0	0
T1	632330	632248	0	0
T2	21045	20978	0	0
T3	333149	333075	0	0
T4	653077	652971	0	0
T5	175511	175432	0	0
T14	143242	143157	0	0
T15	296555	296460	0	0
T16	228356	228280	0	0
T17	53663	53601	0	0
T18	1102	1039	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	514677709	514566413	0	0
T1	632330	632248	0	0
T2	21045	20978	0	0
T3	333149	333075	0	0
T4	653077	652971	0	0
T5	175511	175432	0	0
T14	143242	143157	0	0
T15	296555	296460	0	0
T16	228356	228280	0	0
T17	53663	53601	0	0
T18	1102	1039	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	659	659	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0