Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

42598114

1

T1

30427

T2

35207

T3

50274

full_word

38861663

1

T1

24409

T2

32888

T3

40119

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	81459347	1			T1	54836		T2	68095		T3	90393
auto[TlIntgErrCmd]	143	1			T73	13		T74	6		T75	8
auto[TlIntgErrData]	155	1			T73	3		T74	8		T75	6
auto[TlIntgErrBoth]	132	1			T73	4		T74	6		T75	6

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

38382834

1

T1

27544

T2

33360

T3

45518

auto[1]

43076943

1

T1

27292

T2

34735

T3

44875

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	19706375	1			T1	13791		T2	16604		T3	22902
auto[TlIntgErrNone]	partial	auto[1]	22891350	1			T1	16636		T2	18603		T3	27372
auto[TlIntgErrNone]	full_word	auto[0]	18676264	1			T1	13753		T2	16756		T3	22616
auto[TlIntgErrNone]	full_word	auto[1]	20185358	1			T1	10656		T2	16132		T3	17503
auto[TlIntgErrCmd]	partial	auto[0]	51	1			T73	4		T74	3		T75	4
auto[TlIntgErrCmd]	partial	auto[1]	78	1			T73	8		T75	3		T139	2
auto[TlIntgErrCmd]	full_word	auto[0]	6	1			T74	2		T75	1		T140	2
auto[TlIntgErrCmd]	full_word	auto[1]	8	1			T73	1		T74	1		T139	1
auto[TlIntgErrData]	partial	auto[0]	64	1			T73	2		T74	6		T75	2
auto[TlIntgErrData]	partial	auto[1]	74	1			T73	1		T74	2		T75	4
auto[TlIntgErrData]	full_word	auto[0]	10	1			T139	2		T141	1		T142	1
auto[TlIntgErrData]	full_word	auto[1]	7	1			T138	2		T141	1		T143	2
auto[TlIntgErrBoth]	partial	auto[0]	58	1			T73	1		T74	3		T75	3
auto[TlIntgErrBoth]	partial	auto[1]	64	1			T73	3		T74	2		T75	3
auto[TlIntgErrBoth]	full_word	auto[0]	6	1			T136	1		T140	3		T144	1
auto[TlIntgErrBoth]	full_word	auto[1]	4	1			T74	1		T137	2		T145	1