Unified Coverage Report :: Module :: hmac_csr_assert_fpv

Module : hmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_hmac_csr_assert_0/hmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.hmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.hmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.71	100.00	93.33	100.00	100.00	98.90	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : hmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	434660999	1152910	0	0
intr_enable_rd_A	434660999	3702	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434660999	1152910	0	0
T8	641770	99346	0	0
T9	0	225964	0	0
T10	0	68295	0	0
T14	0	127849	0	0
T15	0	172877	0	0
T23	0	257193	0	0
T24	0	137242	0	0
T73	0	3	0	0
T77	0	3110	0	0
T78	0	49462	0	0
T79	170854	0	0	0
T80	275005	0	0	0
T81	33014	0	0	0
T82	23086	0	0	0
T83	615686	0	0	0
T84	747	0	0	0
T85	1484	0	0	0
T86	290308	0	0	0
T87	847	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434660999	3702	0	0
T5	533433	0	0	0
T7	78623	0	0	0
T8	0	158	0	0
T14	0	191	0	0
T15	0	221	0	0
T18	2460	36	0	0
T19	139041	0	0	0
T25	538573	0	0	0
T26	48659	0	0	0
T27	132371	0	0	0
T28	86333	0	0	0
T31	603465	0	0	0
T47	177635	0	0	0
T88	0	10	0	0
T89	0	13	0	0
T90	0	66	0	0
T91	0	25	0	0
T92	0	37	0	0
T93	0	39	0	0