Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

47618103

1

T1

34111

T2

18283

T3

88242

full_word

42200156

1

T1

33343

T2

14586

T3

69411

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	89817829	1			T1	67454		T2	32869		T3	157653
auto[TlIntgErrCmd]	134	1			T68	3		T69	4		T70	7
auto[TlIntgErrData]	147	1			T68	5		T69	6		T70	9
auto[TlIntgErrBoth]	149	1			T68	2		T69	10		T70	14

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

42379101

1

T1

28854

T2

16524

T3

79194

auto[1]

47439158

1

T1

38600

T2

16345

T3

78459

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	21745818	1			T1	14773		T2	8311		T3	39719
auto[TlIntgErrNone]	partial	auto[1]	25871888	1			T1	19338		T2	9972		T3	48523
auto[TlIntgErrNone]	full_word	auto[0]	20633088	1			T1	14081		T2	8213		T3	39475
auto[TlIntgErrNone]	full_word	auto[1]	21567035	1			T1	19262		T2	6373		T3	29936
auto[TlIntgErrCmd]	partial	auto[0]	56	1			T68	1		T69	1		T70	4
auto[TlIntgErrCmd]	partial	auto[1]	68	1			T68	2		T69	3		T70	2
auto[TlIntgErrCmd]	full_word	auto[0]	5	1			T126	1		T127	1		T128	1
auto[TlIntgErrCmd]	full_word	auto[1]	5	1			T70	1		T129	1		T130	1
auto[TlIntgErrData]	partial	auto[0]	65	1			T68	1		T69	3		T70	1
auto[TlIntgErrData]	partial	auto[1]	73	1			T68	2		T69	3		T70	8
auto[TlIntgErrData]	full_word	auto[0]	7	1			T68	2		T131	1		T132	1
auto[TlIntgErrData]	full_word	auto[1]	2	1			T133	2		-	-		-	-
auto[TlIntgErrBoth]	partial	auto[0]	59	1			T69	4		T70	6		T126	5
auto[TlIntgErrBoth]	partial	auto[1]	76	1			T69	6		T70	5		T126	5
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T70	1		T131	1		T133	1
auto[TlIntgErrBoth]	full_word	auto[1]	11	1			T68	2		T70	2		T125	1