Unified Coverage Report :: Module :: hmac_csr_assert_fpv

Module : hmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_hmac_csr_assert_0/hmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.hmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.hmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.71	100.00	93.33	100.00	100.00	98.90	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : hmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	501250558	1567035	0	0
intr_enable_rd_A	501250558	5744	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	501250558	1567035	0	0
T7	873278	141395	0	0
T11	140803	0	0	0
T14	10858	0	0	0
T16	0	174833	0	0
T17	0	65907	0	0
T20	0	267477	0	0
T22	0	74406	0	0
T30	88389	0	0	0
T34	161551	0	0	0
T35	660434	0	0	0
T72	0	67611	0	0
T73	0	309702	0	0
T74	0	52016	0	0
T75	0	130890	0	0
T76	0	49632	0	0
T77	103799	0	0	0
T78	96537	0	0	0
T79	446384	0	0	0
T80	133868	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	501250558	5744	0	0
T6	782026	47	0	0
T7	873278	87	0	0
T14	10858	0	0	0
T15	544241	0	0	0
T16	0	224	0	0
T19	154115	0	0	0
T30	88389	0	0	0
T35	0	68	0	0
T52	0	26	0	0
T77	103799	0	0	0
T78	96537	0	0	0
T79	446384	0	0	0
T80	133868	0	0	0
T81	0	22	0	0
T82	0	61	0	0
T83	0	65	0	0
T84	0	31	0	0
T85	0	60	0	0