Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	47521502	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

44937739

1

T1

941017

T2

58316

T3

53229

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	44110674	1			T1	895779		T2	49210		T3	60912
values[0x0]	22627237	1			T1	486968		T2	28745		T3	27504
values[0x1]	25721330	1			T1	536778		T2	30331		T3	32168

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	36594508	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

55864733

1

T1

116194

T2

69481

T3

68546

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	266153	1			T1	7785		T2	386		T3	457
valid_sources[0x01]	1155765	1			T1	7284		T2	418		T3	439
valid_sources[0x02]	271716	1			T1	7492		T2	455		T3	517
valid_sources[0x03]	267675	1			T1	7447		T2	437		T3	451
valid_sources[0x04]	278120	1			T1	7496		T2	479		T3	489
valid_sources[0x05]	282323	1			T1	7377		T2	388		T3	495
valid_sources[0x06]	310700	1			T1	7375		T2	421		T3	474
valid_sources[0x07]	271872	1			T1	7477		T2	420		T3	490
valid_sources[0x08]	750510	1			T1	7431		T2	455		T3	502
valid_sources[0x09]	370128	1			T1	7573		T2	429		T3	442
valid_sources[0x0a]	369766	1			T1	7547		T2	404		T3	429
valid_sources[0x0b]	271049	1			T1	7534		T2	388		T3	518
valid_sources[0x0c]	313231	1			T1	7491		T2	411		T3	454
valid_sources[0x0d]	318222	1			T1	7520		T2	480		T3	456
valid_sources[0x0e]	449195	1			T1	7564		T2	399		T3	488
valid_sources[0x0f]	265212	1			T1	7416		T2	416		T3	473
valid_sources[0x10]	277634	1			T1	7423		T2	453		T3	500
valid_sources[0x11]	278991	1			T1	7583		T2	383		T3	490
valid_sources[0x12]	328217	1			T1	7582		T2	394		T3	464
valid_sources[0x13]	383242	1			T1	7336		T2	460		T3	482
valid_sources[0x14]	270996	1			T1	7440		T2	402		T3	468
valid_sources[0x15]	1210729	1			T1	7392		T2	473		T3	480
valid_sources[0x16]	274586	1			T1	7593		T2	390		T3	504
valid_sources[0x17]	645459	1			T1	7375		T2	400		T3	481
valid_sources[0x18]	2215519	1			T1	7563		T2	349		T3	487
valid_sources[0x19]	271822	1			T1	7544		T2	398		T3	477
valid_sources[0x1a]	387155	1			T1	7657		T2	418		T3	466
valid_sources[0x1b]	266849	1			T1	7501		T2	347		T3	458
valid_sources[0x1c]	277658	1			T1	7427		T2	412		T3	457
valid_sources[0x1d]	281682	1			T1	7578		T2	461		T3	514
valid_sources[0x1e]	1047844	1			T1	7401		T2	439		T3	475
valid_sources[0x1f]	267615	1			T1	7391		T2	476		T3	470
valid_sources[0x20]	264808	1			T1	7482		T2	456		T3	474
valid_sources[0x21]	268382	1			T1	7434		T2	427		T3	452
valid_sources[0x22]	266551	1			T1	7567		T2	365		T3	475
valid_sources[0x23]	600680	1			T1	7341		T2	446		T3	460
valid_sources[0x24]	300858	1			T1	7497		T2	407		T3	488
valid_sources[0x25]	316915	1			T1	7445		T2	398		T3	486
valid_sources[0x26]	275112	1			T1	7530		T2	414		T3	450
valid_sources[0x27]	270755	1			T1	7392		T2	353		T3	480
valid_sources[0x28]	269113	1			T1	7499		T2	478		T3	501
valid_sources[0x29]	270601	1			T1	7487		T2	388		T3	465
valid_sources[0x2a]	279724	1			T1	7377		T2	466		T3	463
valid_sources[0x2b]	316467	1			T1	7387		T2	406		T3	499
valid_sources[0x2c]	262535	1			T1	7661		T2	415		T3	514
valid_sources[0x2d]	281586	1			T1	7594		T2	428		T3	513
valid_sources[0x2e]	337234	1			T1	7623		T2	420		T3	460
valid_sources[0x2f]	292664	1			T1	7443		T2	378		T3	439
valid_sources[0x30]	308283	1			T1	7374		T2	397		T3	464
valid_sources[0x31]	274299	1			T1	7562		T2	405		T3	516
valid_sources[0x32]	270184	1			T1	7426		T2	529		T3	494
valid_sources[0x33]	271165	1			T1	7692		T2	371		T3	472
valid_sources[0x34]	277648	1			T1	7347		T2	456		T3	502
valid_sources[0x35]	272245	1			T1	7472		T2	459		T3	470
valid_sources[0x36]	269243	1			T1	7461		T2	428		T3	429
valid_sources[0x37]	265434	1			T1	7441		T2	386		T3	470
valid_sources[0x38]	271086	1			T1	7454		T2	375		T3	468
valid_sources[0x39]	276376	1			T1	7509		T2	410		T3	425
valid_sources[0x3a]	270796	1			T1	7353		T2	404		T3	479
valid_sources[0x3b]	305347	1			T1	7540		T2	436		T3	458
valid_sources[0x3c]	292595	1			T1	7501		T2	378		T3	475
valid_sources[0x3d]	317642	1			T1	7485		T2	396		T3	469
valid_sources[0x3e]	393096	1			T1	7651		T2	454		T3	455
valid_sources[0x3f]	268402	1			T1	7540		T2	408		T3	440
valid_sources[0x40]	278909	1			T1	7389		T2	420		T3	464
valid_sources[0x41]	268929	1			T1	7669		T2	433		T3	461
valid_sources[0x42]	509790	1			T1	7344		T2	417		T3	484
valid_sources[0x43]	266663	1			T1	7582		T2	395		T3	439
valid_sources[0x44]	406090	1			T1	7637		T2	379		T3	459
valid_sources[0x45]	334158	1			T1	7591		T2	415		T3	480
valid_sources[0x46]	294460	1			T1	7585		T2	379		T3	466
valid_sources[0x47]	351634	1			T1	7409		T2	390		T3	486
valid_sources[0x48]	482924	1			T1	7452		T2	428		T3	491
valid_sources[0x49]	305024	1			T1	7503		T2	433		T3	471
valid_sources[0x4a]	271187	1			T1	7638		T2	423		T3	490
valid_sources[0x4b]	279099	1			T1	7445		T2	435		T3	501
valid_sources[0x4c]	303952	1			T1	7486		T2	471		T3	485
valid_sources[0x4d]	271607	1			T1	7588		T2	381		T3	488
valid_sources[0x4e]	272207	1			T1	7579		T2	408		T3	421
valid_sources[0x4f]	275336	1			T1	7464		T2	424		T3	452
valid_sources[0x50]	367139	1			T1	7691		T2	451		T3	483
valid_sources[0x51]	369397	1			T1	7610		T2	451		T3	495
valid_sources[0x52]	271229	1			T1	7604		T2	419		T3	435
valid_sources[0x53]	288205	1			T1	7516		T2	448		T3	500
valid_sources[0x54]	264014	1			T1	7482		T2	440		T3	490
valid_sources[0x55]	1110879	1			T1	7541		T2	439		T3	478
valid_sources[0x56]	268501	1			T1	7580		T2	400		T3	523
valid_sources[0x57]	419573	1			T1	7558		T2	461		T3	489
valid_sources[0x58]	275377	1			T1	7517		T2	439		T3	444
valid_sources[0x59]	550009	1			T1	7461		T2	387		T3	444
valid_sources[0x5a]	264711	1			T1	7686		T2	394		T3	446
valid_sources[0x5b]	267167	1			T1	7487		T2	426		T3	492
valid_sources[0x5c]	272249	1			T1	7609		T2	450		T3	461
valid_sources[0x5d]	265122	1			T1	7584		T2	410		T3	477
valid_sources[0x5e]	266878	1			T1	7625		T2	475		T3	488
valid_sources[0x5f]	266425	1			T1	7542		T2	428		T3	479
valid_sources[0x60]	272549	1			T1	7483		T2	439		T3	479
valid_sources[0x61]	269462	1			T1	7724		T2	426		T3	526
valid_sources[0x62]	277834	1			T1	7312		T2	453		T3	438
valid_sources[0x63]	491488	1			T1	7470		T2	447		T3	452
valid_sources[0x64]	275070	1			T1	7630		T2	468		T3	470
valid_sources[0x65]	268972	1			T1	7534		T2	413		T3	455
valid_sources[0x66]	261610	1			T1	7476		T2	461		T3	472
valid_sources[0x67]	282383	1			T1	7449		T2	419		T3	533
valid_sources[0x68]	540896	1			T1	7527		T2	438		T3	468
valid_sources[0x69]	277101	1			T1	7359		T2	448		T3	473
valid_sources[0x6a]	267541	1			T1	7532		T2	384		T3	466
valid_sources[0x6b]	264450	1			T1	7436		T2	366		T3	455
valid_sources[0x6c]	269927	1			T1	7429		T2	454		T3	459
valid_sources[0x6d]	276532	1			T1	7587		T2	423		T3	431
valid_sources[0x6e]	274255	1			T1	7454		T2	399		T3	512
valid_sources[0x6f]	277618	1			T1	7423		T2	397		T3	492
valid_sources[0x70]	363901	1			T1	7492		T2	420		T3	467
valid_sources[0x71]	290225	1			T1	7417		T2	430		T3	476
valid_sources[0x72]	275826	1			T1	7781		T2	444		T3	456
valid_sources[0x73]	343280	1			T1	7449		T2	389		T3	485
valid_sources[0x74]	321821	1			T1	7727		T2	417		T3	489
valid_sources[0x75]	1987759	1			T1	7589		T2	455		T3	488
valid_sources[0x76]	271107	1			T1	7479		T2	438		T3	448
valid_sources[0x77]	292087	1			T1	7796		T2	422		T3	456
valid_sources[0x78]	273617	1			T1	7396		T2	446		T3	478
valid_sources[0x79]	263638	1			T1	7563		T2	416		T3	445
valid_sources[0x7a]	264412	1			T1	7526		T2	499		T3	476
valid_sources[0x7b]	279683	1			T1	7269		T2	431		T3	497
valid_sources[0x7c]	266789	1			T1	7213		T2	418		T3	450
valid_sources[0x7d]	335586	1			T1	7530		T2	444		T3	474
valid_sources[0x7e]	316680	1			T1	7535		T2	387		T3	498
valid_sources[0x7f]	271229	1			T1	7533		T2	447		T3	516
valid_sources[0x80]	719954	1			T1	7687		T2	404		T3	429

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

21878401

1

T1

447800

T2

24301

T3

29897

values[0x0]

all_enables

biggest_size

12423253

1

T1

267228

T2

18071

T3

12830

values[0x1]

all_enables

biggest_size

10636085

1

T1

225989

T2

15944

T3

10502