Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

51236348

1

T1

978508

T2

49970

T3

67355

full_word

45178534

1

T1

941017

T2

58316

T3

53229

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	96414492	1			T1	191952		T2	108286		T3	120584
auto[TlIntgErrCmd]	124	1			T76	7		T77	11		T78	1
auto[TlIntgErrData]	141	1			T76	7		T77	10		T78	4
auto[TlIntgErrBoth]	125	1			T76	6		T77	9		T78	5

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

45360589

1

T1

895779

T2

49210

T3

60912

auto[1]

51054293

1

T1

102374

T2

59076

T3

59672

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	23387200	1			T1	447979		T2	24909		T3	31015
auto[TlIntgErrNone]	partial	auto[1]	27848790	1			T1	530529		T2	25061		T3	36340
auto[TlIntgErrNone]	full_word	auto[0]	21973212	1			T1	447800		T2	24301		T3	29897
auto[TlIntgErrNone]	full_word	auto[1]	23205290	1			T1	493217		T2	34015		T3	23332
auto[TlIntgErrCmd]	partial	auto[0]	46	1			T76	1		T77	4		T135	1
auto[TlIntgErrCmd]	partial	auto[1]	70	1			T76	6		T77	7		T78	1
auto[TlIntgErrCmd]	full_word	auto[0]	5	1			T140	1		T138	2		T141	1
auto[TlIntgErrCmd]	full_word	auto[1]	3	1			T140	1		T141	1		T142	1
auto[TlIntgErrData]	partial	auto[0]	70	1			T76	6		T77	5		T78	1
auto[TlIntgErrData]	partial	auto[1]	57	1			T76	1		T77	4		T78	3
auto[TlIntgErrData]	full_word	auto[0]	6	1			T77	1		T138	1		T143	2
auto[TlIntgErrData]	full_word	auto[1]	8	1			T138	3		T144	1		T139	2
auto[TlIntgErrBoth]	partial	auto[0]	47	1			T76	4		T77	4		T78	4
auto[TlIntgErrBoth]	partial	auto[1]	68	1			T76	2		T77	5		T78	1
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T138	1		T144	1		T145	1
auto[TlIntgErrBoth]	full_word	auto[1]	7	1			T144	1		T141	1		T143	1