Unified Coverage Report :: Module :: hmac_csr_assert_fpv

Module : hmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_hmac_csr_assert_0/hmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.hmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.hmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.71	100.00	93.33	100.00	100.00	98.90	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : hmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	508321592	2136759	0	0
intr_enable_rd_A	508321592	3372	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	508321592	2136759	0	0
T8	327237	70740	0	0
T9	0	78461	0	0
T10	0	170411	0	0
T13	0	353190	0	0
T14	0	252213	0	0
T15	0	82666	0	0
T24	0	241091	0	0
T29	0	358509	0	0
T31	0	255454	0	0
T71	119810	0	0	0
T72	448941	0	0	0
T73	40604	0	0	0
T74	2670	0	0	0
T75	873804	0	0	0
T80	0	56814	0	0
T81	25079	0	0	0
T82	308385	0	0	0
T83	453916	0	0	0
T84	148244	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	508321592	3372	0	0
T10	0	121	0	0
T14	0	146	0	0
T36	0	8	0	0
T85	105098	34	0	0
T86	0	26	0	0
T87	0	36	0	0
T88	0	39	0	0
T89	0	62	0	0
T90	0	24	0	0
T91	0	5	0	0
T92	28029	0	0	0
T93	870	0	0	0
T94	104564	0	0	0
T95	7813	0	0	0
T96	69250	0	0	0
T97	751695	0	0	0
T98	807	0	0	0
T99	297891	0	0	0
T100	640494	0	0	0