Unified Coverage Report :: Module :: hmac_csr_assert_fpv

Module : hmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_hmac_csr_assert_0/hmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.hmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.hmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.71	100.00	93.33	100.00	100.00	98.90	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : hmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	524015184	2045178	0	0
intr_enable_rd_A	524015184	4497	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	524015184	2045178	0	0
T11	614559	217447	0	0
T12	0	102202	0	0
T13	0	118728	0	0
T20	0	120144	0	0
T21	0	116938	0	0
T25	0	76050	0	0
T35	0	61161	0	0
T47	278353	0	0	0
T70	0	64560	0	0
T71	0	51485	0	0
T72	0	118479	0	0
T73	334878	0	0	0
T74	721758	0	0	0
T75	448208	0	0	0
T76	600143	0	0	0
T77	130979	0	0	0
T78	222289	0	0	0
T79	584125	0	0	0
T80	108399	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	524015184	4497	0	0
T20	0	57	0	0
T21	0	152	0	0
T27	731665	55	0	0
T49	805549	0	0	0
T50	54187	0	0	0
T69	63314	0	0	0
T81	0	39	0	0
T82	0	67	0	0
T83	0	20	0	0
T84	0	99	0	0
T85	0	1	0	0
T86	0	4	0	0
T87	0	10	0	0
T88	195846	0	0	0
T89	55489	0	0	0
T90	11122	0	0	0
T91	31752	0	0	0
T92	363843	0	0	0
T93	100626	0	0	0