Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

42616043

1

T1

34713

T2

10418

T3

3357

full_word

38705312

1

T1

27919

T2

9608

T3

5066

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	81320965	1			T1	62632		T2	20026		T3	8423
auto[TlIntgErrCmd]	126	1			T69	3		T70	2		T71	11
auto[TlIntgErrData]	128	1			T69	5		T70	6		T71	8
auto[TlIntgErrBoth]	136	1			T69	2		T70	12		T71	11

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

38440996

1

T1

31582

T2

9822

T3

3520

auto[1]

42880359

1

T1

31050

T2

10204

T3

4903

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	19657032	1			T1	15906		T2	4853		T3	1837
auto[TlIntgErrNone]	partial	auto[1]	22958647	1			T1	18807		T2	5565		T3	1520
auto[TlIntgErrNone]	full_word	auto[0]	18783772	1			T1	15676		T2	4969		T3	1683
auto[TlIntgErrNone]	full_word	auto[1]	19921514	1			T1	12243		T2	4639		T3	3383
auto[TlIntgErrCmd]	partial	auto[0]	52	1			T69	1		T71	2		T133	3
auto[TlIntgErrCmd]	partial	auto[1]	64	1			T69	2		T70	2		T71	8
auto[TlIntgErrCmd]	full_word	auto[0]	7	1			T71	1		T136	2		T137	1
auto[TlIntgErrCmd]	full_word	auto[1]	3	1			T133	1		T134	1		T136	1
auto[TlIntgErrData]	partial	auto[0]	66	1			T69	4		T70	3		T71	2
auto[TlIntgErrData]	partial	auto[1]	54	1			T69	1		T70	3		T71	6
auto[TlIntgErrData]	full_word	auto[0]	6	1			T133	1		T135	1		T137	4
auto[TlIntgErrData]	full_word	auto[1]	2	1			T138	1		T139	1		-	-
auto[TlIntgErrBoth]	partial	auto[0]	56	1			T70	3		T71	4		T133	1
auto[TlIntgErrBoth]	partial	auto[1]	72	1			T69	1		T70	8		T71	7
auto[TlIntgErrBoth]	full_word	auto[0]	5	1			T69	1		T70	1		T134	1
auto[TlIntgErrBoth]	full_word	auto[1]	3	1			T136	1		T137	1		T140	1