Unified Coverage Report :: Module :: hmac_csr_assert_fpv

Module : hmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_hmac_csr_assert_0/hmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.hmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.hmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.71	100.00	93.33	100.00	100.00	98.90	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : hmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	466230707	991076	0	0
intr_enable_rd_A	466230707	4302	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	466230707	991076	0	0
T7	237597	6553	0	0
T8	0	4673	0	0
T9	0	4265	0	0
T13	0	4780	0	0
T22	0	9413	0	0
T23	0	27111	0	0
T27	0	6987	0	0
T63	1295	0	0	0
T73	0	7018	0	0
T74	0	12	0	0
T75	0	903	0	0
T76	66183	0	0	0
T77	125945	0	0	0
T78	908	0	0	0
T79	187295	0	0	0
T80	1009	0	0	0
T81	154046	0	0	0
T82	862142	0	0	0
T83	7598	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	466230707	4302	0	0
T9	618151	97	0	0
T13	0	31	0	0
T84	431385	56	0	0
T85	221267	23	0	0
T86	0	46	0	0
T87	0	9	0	0
T88	0	9	0	0
T89	0	103	0	0
T90	0	49	0	0
T91	0	17	0	0
T92	301938	0	0	0
T93	58103	0	0	0
T94	60540	0	0	0
T95	994515	0	0	0
T96	124588	0	0	0
T97	203320	0	0	0
T98	690043	0	0	0