Unified Coverage Report :: Module :: hmac_csr_assert_fpv

Module : hmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_hmac_csr_assert_0/hmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.hmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.hmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.71	100.00	93.33	100.00	100.00	98.90	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : hmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	458564261	499161	0	0
intr_enable_rd_A	458564261	4005	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	458564261	499161	0	0
T10	429543	5105	0	0
T11	482395	3585	0	0
T12	0	2924	0	0
T23	188104	0	0	0
T24	0	3834	0	0
T25	0	18398	0	0
T26	0	20643	0	0
T59	481801	0	0	0
T68	0	4	0	0
T74	0	11456	0	0
T75	0	604	0	0
T76	0	4	0	0
T77	785298	0	0	0
T78	60992	0	0	0
T79	328687	0	0	0
T80	888	0	0	0
T81	205461	0	0	0
T82	52219	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	458564261	4005	0	0
T10	429543	7	0	0
T11	482395	26	0	0
T23	188104	0	0	0
T59	481801	0	0	0
T77	785298	0	0	0
T78	60992	0	0	0
T79	328687	0	0	0
T80	888	0	0	0
T81	205461	0	0	0
T82	52219	0	0	0
T83	0	11	0	0
T84	0	10	0	0
T85	0	10	0	0
T86	0	64	0	0
T87	0	29	0	0
T88	0	32	0	0
T89	0	111	0	0
T90	0	2	0	0