Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	38058594	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

35874358

1

T1

4

T2

1223

T4

4432

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	35314705	1			T1	1		T2	1299		T3	1
values[0x0]	18144444	1			T1	9		T2	589		T4	2002
values[0x1]	20473803	1			T1	5		T2	678		T4	2093

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	29379166	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

44553786

1

T1

4

T2

1549

T3

1

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	219806	1			T2	9		T4	16		T5	39
valid_sources[0x01]	346262	1			T2	7		T4	21		T5	46
valid_sources[0x02]	223073	1			T2	8		T4	16		T5	50
valid_sources[0x03]	337814	1			T2	13		T4	24		T5	47
valid_sources[0x04]	232254	1			T2	12		T4	31		T5	53
valid_sources[0x05]	220769	1			T2	9		T4	19		T5	48
valid_sources[0x06]	221793	1			T2	16		T4	23		T5	35
valid_sources[0x07]	322739	1			T2	7		T4	14		T5	54
valid_sources[0x08]	308802	1			T2	10		T4	34		T5	53
valid_sources[0x09]	222016	1			T2	10		T4	14		T5	32
valid_sources[0x0a]	221180	1			T2	10		T4	24		T5	37
valid_sources[0x0b]	220439	1			T2	10		T4	24		T5	49
valid_sources[0x0c]	245092	1			T2	7		T4	16		T5	34
valid_sources[0x0d]	248362	1			T2	12		T4	28		T5	33
valid_sources[0x0e]	262154	1			T2	14		T4	15		T5	37
valid_sources[0x0f]	217752	1			T2	13		T4	7		T5	27
valid_sources[0x10]	221836	1			T2	11		T4	28		T5	36
valid_sources[0x11]	222500	1			T2	6		T4	55		T5	50
valid_sources[0x12]	220736	1			T2	9		T4	30		T5	52
valid_sources[0x13]	2295521	1			T2	8		T4	37		T5	41
valid_sources[0x14]	251037	1			T2	9		T4	22		T5	42
valid_sources[0x15]	230828	1			T2	14		T4	13		T5	45
valid_sources[0x16]	222223	1			T2	12		T4	28		T5	30
valid_sources[0x17]	221822	1			T2	15		T4	23		T5	33
valid_sources[0x18]	583959	1			T2	9		T4	7		T5	52
valid_sources[0x19]	221325	1			T2	9		T4	36		T5	58
valid_sources[0x1a]	220683	1			T2	14		T4	27		T5	18
valid_sources[0x1b]	232254	1			T2	9		T4	29		T5	50
valid_sources[0x1c]	346954	1			T2	8		T4	31		T5	56
valid_sources[0x1d]	237292	1			T2	7		T4	21		T5	38
valid_sources[0x1e]	218179	1			T2	13		T4	25		T5	37
valid_sources[0x1f]	221495	1			T2	10		T4	18		T5	68
valid_sources[0x20]	219530	1			T2	5		T4	22		T5	51
valid_sources[0x21]	219674	1			T2	13		T4	25		T5	52
valid_sources[0x22]	221387	1			T2	16		T4	18		T5	55
valid_sources[0x23]	246654	1			T2	16		T4	20		T5	36
valid_sources[0x24]	220097	1			T2	11		T4	26		T5	42
valid_sources[0x25]	221641	1			T2	5		T4	35		T5	21
valid_sources[0x26]	241370	1			T2	9		T4	36		T5	62
valid_sources[0x27]	219201	1			T2	12		T4	26		T5	37
valid_sources[0x28]	221249	1			T2	6		T4	10		T5	43
valid_sources[0x29]	221194	1			T2	8		T4	57		T5	46
valid_sources[0x2a]	221452	1			T2	9		T4	30		T5	40
valid_sources[0x2b]	219937	1			T2	8		T4	25		T5	44
valid_sources[0x2c]	227925	1			T2	16		T4	32		T5	32
valid_sources[0x2d]	219872	1			T2	8		T4	10		T5	37
valid_sources[0x2e]	221680	1			T2	8		T4	30		T5	33
valid_sources[0x2f]	221301	1			T2	7		T4	16		T5	58
valid_sources[0x30]	645759	1			T2	8		T4	25		T5	54
valid_sources[0x31]	220336	1			T2	11		T4	17		T5	39
valid_sources[0x32]	219752	1			T2	13		T4	28		T5	38
valid_sources[0x33]	219622	1			T2	11		T4	23		T5	44
valid_sources[0x34]	221910	1			T2	14		T4	22		T5	36
valid_sources[0x35]	220610	1			T2	10		T4	10		T5	79
valid_sources[0x36]	448538	1			T2	16		T4	33		T5	60
valid_sources[0x37]	219140	1			T2	9		T4	19		T5	52
valid_sources[0x38]	220787	1			T2	13		T4	18		T5	41
valid_sources[0x39]	222538	1			T2	9		T4	48		T5	38
valid_sources[0x3a]	221822	1			T2	5		T4	18		T5	32
valid_sources[0x3b]	271927	1			T2	12		T4	15		T5	45
valid_sources[0x3c]	219501	1			T2	13		T4	19		T5	27
valid_sources[0x3d]	222184	1			T2	8		T4	22		T5	39
valid_sources[0x3e]	220849	1			T2	7		T4	22		T5	47
valid_sources[0x3f]	218568	1			T2	10		T4	27		T5	29
valid_sources[0x40]	220843	1			T2	11		T4	31		T5	82
valid_sources[0x41]	225880	1			T2	12		T4	16		T5	42
valid_sources[0x42]	220062	1			T2	7		T4	17		T5	31
valid_sources[0x43]	299435	1			T2	15		T4	20		T5	28
valid_sources[0x44]	221040	1			T2	3		T4	33		T5	33
valid_sources[0x45]	373613	1			T2	7		T4	22		T5	30
valid_sources[0x46]	222189	1			T2	13		T4	20		T5	41
valid_sources[0x47]	356376	1			T2	8		T4	16		T5	52
valid_sources[0x48]	223232	1			T2	7		T4	25		T5	41
valid_sources[0x49]	506759	1			T2	7		T4	37		T5	45
valid_sources[0x4a]	221026	1			T2	9		T4	37		T5	34
valid_sources[0x4b]	222030	1			T2	11		T4	14		T5	34
valid_sources[0x4c]	285028	1			T2	16		T4	14		T5	31
valid_sources[0x4d]	492684	1			T2	11		T4	28		T5	36
valid_sources[0x4e]	219562	1			T2	11		T3	1		T4	35
valid_sources[0x4f]	248922	1			T2	8		T4	8		T5	49
valid_sources[0x50]	230947	1			T2	4		T4	21		T5	54
valid_sources[0x51]	221622	1			T2	10		T4	16		T5	61
valid_sources[0x52]	249077	1			T2	10		T4	46		T5	41
valid_sources[0x53]	221340	1			T2	6		T4	28		T5	17
valid_sources[0x54]	221097	1			T2	10		T4	36		T5	36
valid_sources[0x55]	279545	1			T2	13		T4	13		T5	40
valid_sources[0x56]	363432	1			T2	11		T4	11		T5	53
valid_sources[0x57]	219126	1			T2	11		T4	24		T5	56
valid_sources[0x58]	248161	1			T2	10		T4	21		T5	43
valid_sources[0x59]	257766	1			T2	10		T4	16		T5	43
valid_sources[0x5a]	260863	1			T2	15		T4	12		T5	45
valid_sources[0x5b]	221396	1			T2	6		T4	32		T5	44
valid_sources[0x5c]	221724	1			T2	10		T4	17		T5	39
valid_sources[0x5d]	220101	1			T2	11		T4	26		T5	27
valid_sources[0x5e]	219402	1			T2	12		T4	31		T5	47
valid_sources[0x5f]	222234	1			T2	12		T4	22		T5	28
valid_sources[0x60]	222362	1			T2	14		T4	23		T5	36
valid_sources[0x61]	219442	1			T2	7		T4	30		T5	36
valid_sources[0x62]	219823	1			T2	13		T4	20		T5	40
valid_sources[0x63]	229640	1			T2	8		T4	21		T5	53
valid_sources[0x64]	221495	1			T2	8		T4	23		T5	22
valid_sources[0x65]	222154	1			T2	8		T4	37		T5	50
valid_sources[0x66]	220413	1			T2	10		T4	17		T5	32
valid_sources[0x67]	219911	1			T2	1		T4	27		T5	34
valid_sources[0x68]	219395	1			T2	18		T4	14		T5	68
valid_sources[0x69]	252461	1			T2	9		T4	28		T5	38
valid_sources[0x6a]	219864	1			T2	7		T4	12		T5	44
valid_sources[0x6b]	223100	1			T2	10		T4	17		T5	42
valid_sources[0x6c]	221506	1			T2	11		T4	44		T5	29
valid_sources[0x6d]	220180	1			T2	13		T4	27		T5	41
valid_sources[0x6e]	221136	1			T2	6		T4	17		T5	36
valid_sources[0x6f]	221774	1			T2	7		T4	19		T5	52
valid_sources[0x70]	221331	1			T2	7		T4	30		T5	30
valid_sources[0x71]	221198	1			T2	9		T4	20		T5	42
valid_sources[0x72]	331842	1			T2	8		T4	13		T5	38
valid_sources[0x73]	273137	1			T2	10		T4	16		T5	39
valid_sources[0x74]	241888	1			T2	12		T4	14		T5	38
valid_sources[0x75]	220902	1			T2	8		T4	20		T5	33
valid_sources[0x76]	516091	1			T2	10		T4	20		T5	44
valid_sources[0x77]	365634	1			T2	11		T4	15		T5	44
valid_sources[0x78]	219732	1			T2	15		T4	21		T5	43
valid_sources[0x79]	233961	1			T2	12		T4	11		T5	30
valid_sources[0x7a]	220405	1			T2	13		T4	19		T5	56
valid_sources[0x7b]	222576	1			T2	12		T4	8		T5	58
valid_sources[0x7c]	284666	1			T2	9		T4	20		T5	47
valid_sources[0x7d]	221332	1			T2	7		T4	18		T5	53
valid_sources[0x7e]	220555	1			T2	10		T4	20		T5	38
valid_sources[0x7f]	280509	1			T2	13		T4	39		T5	59
valid_sources[0x80]	222458	1			T2	7		T4	21		T5	41

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

17458823

1

T1

1

T2

663

T4

795

values[0x0]

all_enables

biggest_size

9931575

1

T1

2

T2

307

T4

1826

values[0x1]

all_enables

biggest_size

8483960

1

T1

1

T2

253

T4

1811