Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_08/hmac-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

38917566

1

T1

11

T2

1343

T3

1

full_word

35929362

1

T1

4

T2

1223

T4

4432

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	74846578	1			T1	15		T2	2566		T3	1
auto[TlIntgErrCmd]	109	1			T68	3		T69	3		T70	5
auto[TlIntgErrData]	122	1			T68	2		T69	6		T70	9
auto[TlIntgErrBoth]	119	1			T68	5		T69	1		T70	6

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

35601837

1

T1

1

T2

1299

T3

1

auto[1]

39245091

1

T1

14

T2

1267

T4

4095

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	18121253	1			T2	636		T3	1		T4	1244
auto[TlIntgErrNone]	partial	auto[1]	20795991	1			T1	11		T2	707		T4	458
auto[TlIntgErrNone]	full_word	auto[0]	17480425	1			T1	1		T2	663		T4	795
auto[TlIntgErrNone]	full_word	auto[1]	18448909	1			T1	3		T2	560		T4	3637
auto[TlIntgErrCmd]	partial	auto[0]	43	1			T68	1		T69	3		T138	3
auto[TlIntgErrCmd]	partial	auto[1]	58	1			T68	2		T70	5		T138	1
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T139	1		T140	2		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	5	1			T135	1		T133	1		T141	1
auto[TlIntgErrData]	partial	auto[0]	61	1			T68	1		T69	5		T70	4
auto[TlIntgErrData]	partial	auto[1]	48	1			T68	1		T70	3		T138	4
auto[TlIntgErrData]	full_word	auto[0]	4	1			T69	1		T137	2		T140	1
auto[TlIntgErrData]	full_word	auto[1]	9	1			T70	2		T136	2		T137	2
auto[TlIntgErrBoth]	partial	auto[0]	46	1			T68	1		T70	2		T135	5
auto[TlIntgErrBoth]	partial	auto[1]	66	1			T68	4		T69	1		T70	4
auto[TlIntgErrBoth]	full_word	auto[0]	2	1			T136	1		T139	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	5	1			T134	2		T139	1		T72	1