Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	40933348	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

38261619

1

T1

4

T2

1

T4

2913

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	37804195	1			T1	1		T2	1		T3	1
values[0x0]	19410946	1			T1	7		T4	1273		T21	8
values[0x1]	21979826	1			T1	8		T4	1426		T21	6

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	31561063	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

47633904

1

T1

6

T2

1

T4

3648

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	297112	1			T4	19		T5	92		T7	154
valid_sources[0x01]	249062	1			T5	77		T7	100		T8	91
valid_sources[0x02]	258183	1			T5	33		T7	86		T8	49
valid_sources[0x03]	245528	1			T5	48		T7	65		T8	34
valid_sources[0x04]	247338	1			T5	56		T7	46		T8	58
valid_sources[0x05]	262265	1			T5	64		T7	122		T8	48
valid_sources[0x06]	248800	1			T1	1		T5	131		T7	94
valid_sources[0x07]	246269	1			T5	26		T7	122		T8	35
valid_sources[0x08]	245944	1			T4	61		T5	37		T7	68
valid_sources[0x09]	247134	1			T5	27		T7	86		T8	81
valid_sources[0x0a]	248465	1			T5	45		T7	72		T8	64
valid_sources[0x0b]	489416	1			T5	73		T7	64		T8	62
valid_sources[0x0c]	272066	1			T5	31		T7	111		T8	80
valid_sources[0x0d]	248248	1			T5	37		T7	55		T8	56
valid_sources[0x0e]	298490	1			T5	17		T7	147		T8	33
valid_sources[0x0f]	243225	1			T4	54		T5	66		T7	53
valid_sources[0x10]	489476	1			T5	23		T7	38		T8	40
valid_sources[0x11]	476878	1			T5	70		T7	69		T8	52
valid_sources[0x12]	249161	1			T5	27		T7	83		T8	49
valid_sources[0x13]	247280	1			T5	10		T7	31		T8	67
valid_sources[0x14]	247223	1			T5	54		T7	128		T8	72
valid_sources[0x15]	249198	1			T4	209		T5	56		T7	75
valid_sources[0x16]	283969	1			T5	41		T7	69		T8	53
valid_sources[0x17]	247319	1			T4	6		T5	68		T7	73
valid_sources[0x18]	249392	1			T5	35		T7	138		T8	49
valid_sources[0x19]	246831	1			T5	34		T7	57		T8	86
valid_sources[0x1a]	321490	1			T5	95		T7	52		T8	63
valid_sources[0x1b]	2291747	1			T1	1		T5	8		T7	107
valid_sources[0x1c]	245410	1			T4	8		T5	53		T7	100
valid_sources[0x1d]	351646	1			T4	37		T5	129		T7	74
valid_sources[0x1e]	248275	1			T5	19		T7	105		T8	43
valid_sources[0x1f]	295463	1			T4	52		T5	113		T7	101
valid_sources[0x20]	245843	1			T5	37		T7	99		T8	66
valid_sources[0x21]	246134	1			T5	54		T7	57		T8	45
valid_sources[0x22]	243781	1			T5	110		T7	103		T8	49
valid_sources[0x23]	246171	1			T5	104		T7	60		T8	57
valid_sources[0x24]	248146	1			T1	1		T5	50		T7	113
valid_sources[0x25]	248900	1			T5	91		T7	85		T8	61
valid_sources[0x26]	248446	1			T5	72		T7	78		T8	104
valid_sources[0x27]	313210	1			T5	53		T7	80		T8	63
valid_sources[0x28]	252080	1			T5	126		T7	49		T8	42
valid_sources[0x29]	243671	1			T4	64		T5	36		T7	69
valid_sources[0x2a]	257871	1			T5	196		T7	106		T8	87
valid_sources[0x2b]	348272	1			T5	13		T7	56		T8	82
valid_sources[0x2c]	247285	1			T4	28		T5	8		T7	84
valid_sources[0x2d]	300792	1			T5	58		T7	57		T8	53
valid_sources[0x2e]	317753	1			T5	85		T7	135		T8	75
valid_sources[0x2f]	248274	1			T5	114		T7	86		T8	84
valid_sources[0x30]	246248	1			T4	237		T5	34		T7	82
valid_sources[0x31]	248604	1			T5	74		T7	129		T8	15
valid_sources[0x32]	246799	1			T5	23		T7	75		T8	49
valid_sources[0x33]	247371	1			T5	89		T7	16		T8	25
valid_sources[0x34]	511206	1			T5	122		T7	93		T8	53
valid_sources[0x35]	247982	1			T4	70		T5	91		T7	120
valid_sources[0x36]	248117	1			T4	20		T5	39		T7	66
valid_sources[0x37]	246809	1			T4	28		T5	12		T7	179
valid_sources[0x38]	249418	1			T5	33		T7	171		T8	67
valid_sources[0x39]	304680	1			T5	68		T7	120		T8	22
valid_sources[0x3a]	2296679	1			T5	61		T7	64		T8	47
valid_sources[0x3b]	247345	1			T5	41		T7	109		T8	78
valid_sources[0x3c]	247872	1			T5	38		T7	55		T8	93
valid_sources[0x3d]	247581	1			T4	81		T5	38		T7	58
valid_sources[0x3e]	243008	1			T4	336		T5	39		T7	74
valid_sources[0x3f]	245722	1			T5	110		T7	63		T8	26
valid_sources[0x40]	2170412	1			T5	44		T7	83		T8	58
valid_sources[0x41]	247313	1			T5	84		T7	54		T8	52
valid_sources[0x42]	390041	1			T5	29		T7	46		T8	58
valid_sources[0x43]	272153	1			T4	246		T5	23		T7	38
valid_sources[0x44]	248789	1			T5	63		T7	96		T8	29
valid_sources[0x45]	248341	1			T5	51		T7	75		T8	67
valid_sources[0x46]	249626	1			T5	78		T7	86		T8	46
valid_sources[0x47]	266145	1			T5	60		T7	160		T8	48
valid_sources[0x48]	248123	1			T4	17		T5	6		T7	90
valid_sources[0x49]	248569	1			T5	46		T7	52		T8	87
valid_sources[0x4a]	246479	1			T1	1		T4	6		T5	50
valid_sources[0x4b]	246921	1			T4	289		T5	118		T7	106
valid_sources[0x4c]	246373	1			T4	97		T5	40		T7	87
valid_sources[0x4d]	255998	1			T5	41		T7	82		T8	36
valid_sources[0x4e]	245144	1			T5	61		T7	132		T8	70
valid_sources[0x4f]	518157	1			T5	19		T7	77		T8	65
valid_sources[0x50]	246749	1			T4	29		T5	43		T7	132
valid_sources[0x51]	245343	1			T4	10		T5	17		T7	67
valid_sources[0x52]	326309	1			T1	1		T4	70		T5	79
valid_sources[0x53]	244145	1			T1	1		T4	25		T5	73
valid_sources[0x54]	246879	1			T5	11		T7	153		T8	38
valid_sources[0x55]	247065	1			T5	61		T7	60		T8	15
valid_sources[0x56]	268797	1			T5	2		T7	105		T8	16
valid_sources[0x57]	321676	1			T5	97		T7	34		T8	21
valid_sources[0x58]	244432	1			T4	40		T5	61		T7	58
valid_sources[0x59]	367077	1			T4	5		T5	11		T7	73
valid_sources[0x5a]	249297	1			T4	76		T5	84		T7	51
valid_sources[0x5b]	247698	1			T5	80		T7	87		T8	30
valid_sources[0x5c]	244656	1			T4	18		T5	117		T7	68
valid_sources[0x5d]	528335	1			T4	24		T5	14		T7	113
valid_sources[0x5e]	248507	1			T5	72		T7	87		T8	77
valid_sources[0x5f]	254452	1			T4	23		T5	33		T7	62
valid_sources[0x60]	247499	1			T4	76		T5	42		T7	33
valid_sources[0x61]	247572	1			T5	89		T7	133		T8	21
valid_sources[0x62]	247665	1			T5	17		T7	26		T8	68
valid_sources[0x63]	245645	1			T5	33		T7	85		T8	69
valid_sources[0x64]	245382	1			T5	89		T7	9		T8	64
valid_sources[0x65]	249117	1			T5	64		T7	47		T8	78
valid_sources[0x66]	246641	1			T1	2		T5	28		T7	110
valid_sources[0x67]	299580	1			T5	44		T7	90		T8	31
valid_sources[0x68]	247624	1			T5	77		T7	41		T8	13
valid_sources[0x69]	248029	1			T5	30		T7	162		T8	103
valid_sources[0x6a]	248280	1			T5	90		T7	59		T8	40
valid_sources[0x6b]	274616	1			T4	9		T5	62		T6	12213
valid_sources[0x6c]	244338	1			T5	79		T7	38		T8	68
valid_sources[0x6d]	401183	1			T5	108		T7	56		T8	29
valid_sources[0x6e]	250326	1			T4	87		T5	63		T7	112
valid_sources[0x6f]	245923	1			T4	41		T21	15		T5	50
valid_sources[0x70]	246877	1			T1	1		T4	34		T5	51
valid_sources[0x71]	250033	1			T5	42		T7	108		T8	29
valid_sources[0x72]	254020	1			T5	35		T7	91		T8	35
valid_sources[0x73]	244892	1			T5	63		T7	75		T8	58
valid_sources[0x74]	244901	1			T5	11		T7	99		T8	101
valid_sources[0x75]	255991	1			T5	11		T7	22		T8	25
valid_sources[0x76]	245917	1			T5	54		T7	125		T8	136
valid_sources[0x77]	357119	1			T5	121		T7	33		T8	98
valid_sources[0x78]	246225	1			T4	53		T5	42		T7	68
valid_sources[0x79]	247487	1			T4	43		T5	47		T7	50
valid_sources[0x7a]	247374	1			T4	6		T5	4		T7	43
valid_sources[0x7b]	244970	1			T4	64		T5	33		T7	68
valid_sources[0x7c]	246144	1			T5	238		T7	62		T8	34
valid_sources[0x7d]	245169	1			T4	18		T5	29		T7	110
valid_sources[0x7e]	247109	1			T5	33		T7	14		T8	46
valid_sources[0x7f]	244780	1			T4	7		T5	36		T7	97
valid_sources[0x80]	277125	1			T4	13		T5	82		T7	72

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

18685463

1

T2

1

T4

1406

T5

3596

values[0x0]

all_enables

biggest_size

10570319

1

T1

2

T4

808

T21

4

values[0x1]

all_enables

biggest_size

9005837

1

T1

2

T4

699

T5

1277