Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

42484620

1

T1

12

T3

1

T4

3051

full_word

38362014

1

T1

4

T2

1

T4

2913

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	80846214	1			T1	16		T2	1		T3	1
auto[TlIntgErrCmd]	136	1			T68	3		T69	10		T70	7
auto[TlIntgErrData]	139	1			T68	2		T69	10		T70	7
auto[TlIntgErrBoth]	145	1			T68	5		T69	10		T70	6

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

38322606

1

T1

1

T2

1

T3

1

auto[1]

42524028

1

T1

15

T4

2699

T21

14

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	19597580	1			T1	1		T3	1		T4	1859
auto[TlIntgErrNone]	partial	auto[1]	22886646	1			T1	11		T4	1192		T21	10
auto[TlIntgErrNone]	full_word	auto[0]	18724831	1			T2	1		T4	1406		T5	3596
auto[TlIntgErrNone]	full_word	auto[1]	19637157	1			T1	4		T4	1507		T21	4
auto[TlIntgErrCmd]	partial	auto[0]	58	1			T68	2		T69	5		T70	1
auto[TlIntgErrCmd]	partial	auto[1]	70	1			T68	1		T69	4		T70	4
auto[TlIntgErrCmd]	full_word	auto[0]	4	1			T69	1		T150	1		T151	1
auto[TlIntgErrCmd]	full_word	auto[1]	4	1			T70	2		T151	1		T152	1
auto[TlIntgErrData]	partial	auto[0]	64	1			T68	1		T69	2		T70	3
auto[TlIntgErrData]	partial	auto[1]	66	1			T68	1		T69	8		T70	4
auto[TlIntgErrData]	full_word	auto[0]	8	1			T149	1		T148	1		T150	2
auto[TlIntgErrData]	full_word	auto[1]	1	1			T148	1		-	-		-	-
auto[TlIntgErrBoth]	partial	auto[0]	57	1			T68	3		T69	2		T70	2
auto[TlIntgErrBoth]	partial	auto[1]	79	1			T68	2		T69	7		T70	3
auto[TlIntgErrBoth]	full_word	auto[0]	4	1			T70	1		T148	1		T153	1
auto[TlIntgErrBoth]	full_word	auto[1]	5	1			T69	1		T147	1		T153	1