Unified Coverage Report :: Module :: hmac_csr_assert_fpv

Module : hmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_02/hmac-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_hmac_csr_assert_0/hmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.hmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.hmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.71	100.00	93.33	100.00	100.00	98.90	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : hmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	491090868	885694	0	0
intr_enable_rd_A	491090868	3474	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491090868	885694	0	0
T14	144962	0	0	0
T15	89958	0	0	0
T18	156828	4046	0	0
T19	0	4078	0	0
T20	0	1690	0	0
T24	78483	0	0	0
T37	538634	0	0	0
T38	44617	0	0	0
T39	607950	0	0	0
T67	8617	0	0	0
T68	0	3	0	0
T69	0	10	0	0
T72	0	587	0	0
T74	0	413	0	0
T75	0	266	0	0
T76	0	17	0	0
T77	0	21	0	0
T78	683498	0	0	0
T79	952	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491090868	3474	0	0
T20	733500	25	0	0
T58	80661	0	0	0
T80	0	40	0	0
T81	0	65	0	0
T82	0	47	0	0
T83	0	29	0	0
T84	0	25	0	0
T85	0	54	0	0
T86	0	32	0	0
T87	0	29	0	0
T88	0	92	0	0
T89	58329	0	0	0
T90	54929	0	0	0
T91	76247	0	0	0
T92	196163	0	0	0
T93	135694	0	0	0
T94	1250	0	0	0
T95	23580	0	0	0
T96	230036	0	0	0