Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	37764728	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

35764701

1

T1

227

T4

58

T5

8638

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	35004356	1			T1	270		T2	1		T3	1
values[0x0]	18079880	1			T1	105		T2	2		T4	19
values[0x1]	20445193	1			T1	107		T2	3		T4	19

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	29081720	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

44447709

1

T1

290

T2

1

T3

1

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	293857	1			T5	61		T7	120		T8	142
valid_sources[0x01]	285097	1			T1	3		T5	71		T6	7
valid_sources[0x02]	266569	1			T1	1		T5	106		T6	5
valid_sources[0x03]	220299	1			T1	2		T5	71		T6	2
valid_sources[0x04]	221916	1			T1	2		T5	30		T6	6
valid_sources[0x05]	220437	1			T1	2		T5	97		T7	109
valid_sources[0x06]	327771	1			T1	3		T5	74		T6	3
valid_sources[0x07]	227547	1			T1	1		T5	38		T7	116
valid_sources[0x08]	222137	1			T1	1		T5	101		T6	5
valid_sources[0x09]	327003	1			T5	68		T6	4		T7	89
valid_sources[0x0a]	219678	1			T1	4		T5	131		T7	103
valid_sources[0x0b]	222560	1			T1	4		T5	75		T6	3
valid_sources[0x0c]	410185	1			T1	2		T5	97		T6	2
valid_sources[0x0d]	222623	1			T1	2		T5	58		T6	6
valid_sources[0x0e]	223661	1			T5	46		T6	3		T7	98
valid_sources[0x0f]	219885	1			T5	64		T6	15		T7	113
valid_sources[0x10]	508373	1			T1	1		T5	95		T7	117
valid_sources[0x11]	221711	1			T1	3		T5	40		T7	97
valid_sources[0x12]	386329	1			T1	3		T5	43		T6	2
valid_sources[0x13]	221825	1			T1	1		T4	2		T5	59
valid_sources[0x14]	221939	1			T1	1		T5	99		T6	1
valid_sources[0x15]	225960	1			T1	2		T5	86		T7	127
valid_sources[0x16]	278313	1			T5	43		T6	10		T7	107
valid_sources[0x17]	222679	1			T1	1		T5	73		T7	128
valid_sources[0x18]	221327	1			T1	5		T5	51		T7	79
valid_sources[0x19]	226390	1			T5	115		T7	100		T8	103
valid_sources[0x1a]	221938	1			T1	3		T5	44		T6	6
valid_sources[0x1b]	222793	1			T1	2		T5	42		T7	130
valid_sources[0x1c]	240790	1			T1	2		T5	33		T6	18
valid_sources[0x1d]	221699	1			T5	75		T7	91		T8	119
valid_sources[0x1e]	221237	1			T1	1		T5	63		T6	3
valid_sources[0x1f]	221965	1			T1	1		T5	79		T6	1
valid_sources[0x20]	683152	1			T1	2		T5	54		T7	116
valid_sources[0x21]	221273	1			T1	1		T5	65		T6	10
valid_sources[0x22]	222559	1			T5	95		T6	13		T7	123
valid_sources[0x23]	421445	1			T1	2		T5	54		T6	1
valid_sources[0x24]	222300	1			T1	2		T5	53		T6	22
valid_sources[0x25]	220963	1			T1	3		T5	71		T6	6
valid_sources[0x26]	221913	1			T1	1		T5	116		T6	2
valid_sources[0x27]	221208	1			T1	1		T5	95		T6	3
valid_sources[0x28]	222695	1			T1	1		T5	58		T6	2
valid_sources[0x29]	220921	1			T5	56		T7	112		T8	97
valid_sources[0x2a]	221925	1			T1	1		T5	79		T6	19
valid_sources[0x2b]	390376	1			T1	2		T5	22		T6	1
valid_sources[0x2c]	325369	1			T1	5		T5	48		T7	122
valid_sources[0x2d]	221137	1			T5	65		T6	1		T7	96
valid_sources[0x2e]	220987	1			T1	2		T5	98		T6	1
valid_sources[0x2f]	223193	1			T5	23		T6	3		T7	102
valid_sources[0x30]	223200	1			T5	54		T6	1		T7	87
valid_sources[0x31]	221849	1			T1	3		T5	82		T28	4
valid_sources[0x32]	221429	1			T5	72		T6	6		T7	121
valid_sources[0x33]	221806	1			T1	6		T5	30		T7	115
valid_sources[0x34]	263332	1			T1	3		T5	71		T6	10
valid_sources[0x35]	371590	1			T1	1		T5	114		T6	5
valid_sources[0x36]	296241	1			T1	2		T5	88		T7	114
valid_sources[0x37]	221822	1			T1	2		T5	95		T7	102
valid_sources[0x38]	222448	1			T5	57		T6	1		T7	113
valid_sources[0x39]	277294	1			T1	8		T5	73		T7	104
valid_sources[0x3a]	222532	1			T1	3		T5	52		T7	98
valid_sources[0x3b]	239011	1			T1	2		T5	41		T6	9
valid_sources[0x3c]	221122	1			T1	1		T5	71		T7	122
valid_sources[0x3d]	228780	1			T1	4		T5	44		T6	5
valid_sources[0x3e]	220698	1			T5	144		T7	97		T8	131
valid_sources[0x3f]	226181	1			T1	1		T5	47		T7	107
valid_sources[0x40]	597709	1			T1	1		T5	62		T7	121
valid_sources[0x41]	227744	1			T1	1		T5	37		T7	110
valid_sources[0x42]	492952	1			T5	69		T7	119		T8	154
valid_sources[0x43]	221258	1			T1	3		T5	39		T6	1
valid_sources[0x44]	221697	1			T1	1		T5	68		T7	106
valid_sources[0x45]	296743	1			T5	70		T7	115		T8	101
valid_sources[0x46]	274061	1			T1	5		T5	115		T6	13
valid_sources[0x47]	232665	1			T1	2		T5	122		T7	107
valid_sources[0x48]	741335	1			T1	2		T5	47		T7	113
valid_sources[0x49]	241716	1			T5	32		T6	1		T7	110
valid_sources[0x4a]	1175044	1			T1	1		T5	48		T7	135
valid_sources[0x4b]	221967	1			T1	1		T5	69		T6	16
valid_sources[0x4c]	222166	1			T1	3		T5	63		T28	3
valid_sources[0x4d]	301826	1			T5	56		T7	119		T8	115
valid_sources[0x4e]	305858	1			T1	3		T5	108		T6	9
valid_sources[0x4f]	222826	1			T5	138		T7	100		T8	120
valid_sources[0x50]	237674	1			T1	1		T5	18		T6	3
valid_sources[0x51]	235187	1			T1	2		T5	19		T7	119
valid_sources[0x52]	442731	1			T1	2		T5	134		T6	3
valid_sources[0x53]	222185	1			T1	1		T5	65		T6	1
valid_sources[0x54]	225115	1			T1	5		T5	39		T6	1
valid_sources[0x55]	222337	1			T1	2		T5	35		T7	107
valid_sources[0x56]	221452	1			T1	1		T5	90		T7	120
valid_sources[0x57]	222256	1			T5	83		T7	108		T8	105
valid_sources[0x58]	221623	1			T1	1		T5	24		T6	4
valid_sources[0x59]	222046	1			T1	2		T5	31		T6	6
valid_sources[0x5a]	223083	1			T1	1		T5	48		T7	106
valid_sources[0x5b]	221598	1			T5	47		T6	7		T7	94
valid_sources[0x5c]	220431	1			T5	70		T7	104		T8	112
valid_sources[0x5d]	221087	1			T1	2		T5	96		T7	95
valid_sources[0x5e]	696965	1			T1	1		T5	124		T7	105
valid_sources[0x5f]	379766	1			T1	4		T5	53		T7	103
valid_sources[0x60]	313757	1			T1	2		T5	37		T6	2
valid_sources[0x61]	221268	1			T1	1		T5	23		T7	123
valid_sources[0x62]	219544	1			T5	117		T7	101		T8	121
valid_sources[0x63]	637172	1			T5	61		T7	98		T8	132
valid_sources[0x64]	477114	1			T1	6		T4	4		T5	108
valid_sources[0x65]	219375	1			T1	1		T5	53		T7	102
valid_sources[0x66]	222604	1			T5	63		T7	99		T8	136
valid_sources[0x67]	220898	1			T1	2		T4	10		T5	69
valid_sources[0x68]	223828	1			T5	37		T6	1		T7	118
valid_sources[0x69]	221066	1			T1	4		T5	41		T7	99
valid_sources[0x6a]	252118	1			T5	73		T6	1		T7	122
valid_sources[0x6b]	222264	1			T1	1		T5	56		T6	16
valid_sources[0x6c]	222256	1			T1	5		T5	58		T6	13
valid_sources[0x6d]	255223	1			T1	7		T5	105		T6	4
valid_sources[0x6e]	402485	1			T1	1		T5	53		T6	3
valid_sources[0x6f]	220806	1			T1	4		T5	47		T6	8
valid_sources[0x70]	239564	1			T1	1		T5	92		T7	100
valid_sources[0x71]	222698	1			T1	2		T5	124		T6	3
valid_sources[0x72]	222461	1			T4	2		T5	67		T6	4
valid_sources[0x73]	613644	1			T5	30		T7	112		T8	116
valid_sources[0x74]	221901	1			T1	1		T5	70		T7	100
valid_sources[0x75]	222271	1			T1	3		T5	44		T7	104
valid_sources[0x76]	247989	1			T5	59		T6	10		T7	85
valid_sources[0x77]	221097	1			T1	6		T5	96		T6	2
valid_sources[0x78]	219463	1			T1	5		T4	17		T5	53
valid_sources[0x79]	300401	1			T1	5		T5	87		T7	106
valid_sources[0x7a]	220625	1			T5	87		T6	7		T7	110
valid_sources[0x7b]	219260	1			T1	2		T5	44		T7	106
valid_sources[0x7c]	219437	1			T1	1		T5	52		T6	1
valid_sources[0x7d]	222787	1			T4	4		T5	55		T7	102
valid_sources[0x7e]	222848	1			T1	1		T5	124		T7	104
valid_sources[0x7f]	221430	1			T5	64		T7	77		T8	98
valid_sources[0x80]	221220	1			T1	1		T5	82		T7	110

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

17283397

1

T1

98

T4

25

T5

4512

values[0x0]

all_enables

biggest_size

9961643

1

T1

77

T4

18

T5

2243

values[0x1]

all_enables

biggest_size

8519661

1

T1

52

T4

15

T5

1883