Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

39694388

1

T1

255

T2

6

T3

1

full_word

35889950

1

T1

227

T4

58

T5

8638

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	75583928	1			T1	482		T2	6		T3	1
auto[TlIntgErrCmd]	141	1			T64	3		T65	12		T66	12
auto[TlIntgErrData]	141	1			T64	5		T65	8		T66	11
auto[TlIntgErrBoth]	128	1			T64	2		T65	10		T66	7

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

35650861

1

T1

270

T2

1

T3

1

auto[1]

39933477

1

T1

212

T2

5

T4

38

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	18318072	1			T1	172		T2	1		T3	1
auto[TlIntgErrNone]	partial	auto[1]	21375943	1			T1	83		T2	5		T4	5
auto[TlIntgErrNone]	full_word	auto[0]	17332594	1			T1	98		T4	25		T5	4512
auto[TlIntgErrNone]	full_word	auto[1]	18557319	1			T1	129		T4	33		T5	4126
auto[TlIntgErrCmd]	partial	auto[0]	52	1			T65	3		T66	5		T144	1
auto[TlIntgErrCmd]	partial	auto[1]	79	1			T64	3		T65	7		T66	6
auto[TlIntgErrCmd]	full_word	auto[0]	1	1			T145	1		-	-		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	9	1			T65	2		T66	1		T146	1
auto[TlIntgErrData]	partial	auto[0]	70	1			T64	4		T65	3		T66	6
auto[TlIntgErrData]	partial	auto[1]	53	1			T64	1		T65	5		T66	3
auto[TlIntgErrData]	full_word	auto[0]	10	1			T66	2		T147	3		T143	2
auto[TlIntgErrData]	full_word	auto[1]	8	1			T148	1		T142	2		T147	1
auto[TlIntgErrBoth]	partial	auto[0]	58	1			T65	2		T66	4		T144	4
auto[TlIntgErrBoth]	partial	auto[1]	61	1			T64	2		T65	7		T66	2
auto[TlIntgErrBoth]	full_word	auto[0]	4	1			T144	1		T141	1		T142	1
auto[TlIntgErrBoth]	full_word	auto[1]	5	1			T65	1		T66	1		T144	1