Unified Coverage Report :: Module :: hmac_csr_assert_fpv

Module : hmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_08/hmac-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_hmac_csr_assert_0/hmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.hmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.hmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.71	100.00	93.33	100.00	100.00	98.90	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : hmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	437823102	1103460	0	0
intr_enable_rd_A	437823102	2967	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437823102	1103460	0	0
T20	475812	4108	0	0
T21	0	11200	0	0
T22	0	27263	0	0
T23	0	7762	0	0
T24	0	2543	0	0
T50	101418	0	0	0
T64	0	3	0	0
T69	0	136	0	0
T70	0	389	0	0
T71	0	14	0	0
T72	0	16	0	0
T73	23333	0	0	0
T74	329164	0	0	0
T75	875	0	0	0
T76	86907	0	0	0
T77	36204	0	0	0
T78	134246	0	0	0
T79	944662	0	0	0
T80	155549	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437823102	2967	0	0
T22	0	169	0	0
T24	717231	14	0	0
T67	168418	56	0	0
T81	0	38	0	0
T82	0	9	0	0
T83	0	77	0	0
T84	0	17	0	0
T85	0	28	0	0
T86	0	64	0	0
T87	0	107	0	0
T88	167849	0	0	0
T89	86109	0	0	0
T90	27681	0	0	0
T91	1405	0	0	0
T92	229114	0	0	0
T93	22673	0	0	0
T94	47720	0	0	0
T95	188780	0	0	0